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feat[vdpp]: Add vdpp module and vdpp_test

Browse source 
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
Change-Id: I8bd74ad9b4404864ea3d88c7f2e57eecc4c0e35d
Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
This commit is contained in:
xueman.ruan 2024-02-27 12:02:21 +08:00 • committed by Herman Chen
parent bbce74ebc5
commit 677b2a877e
13 changed files with 4452 additions and 1 deletions
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7
mpp/vproc.cmake
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@ -3,3 +3,10 @@ if( ENABLE_VPROC )
set(HAVE_VPROC true)
add_definitions(-DHAVE_VPROC)
endif()
option(ENABLE_VPROC_VDPP "Enable video display post processor" OFF)
if( ENABLE_VPROC_VDPP )
set(HAVE_VPROC_VDPP true)
set(VPROC_VDPP vproc_vdpp)
add_definitions(-DHAVE_VPROC_VDPP)
endif()

3
mpp/vproc/CMakeLists.txt
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@ -4,8 +4,9 @@
# add mpp video process implement
# ----------------------------------------------------------------------------
add_library(mpp_vproc STATIC mpp_dec_vproc.cpp mpp_vproc_dev.cpp)
target_link_libraries(mpp_vproc vproc_rga vproc_iep vproc_iep2 mpp_base)
target_link_libraries(mpp_vproc vproc_rga vproc_iep vproc_iep2 ${VPROC_VDPP} mpp_base)
add_subdirectory(rga)
add_subdirectory(iep)
add_subdirectory(iep2)
add_subdirectory(vdpp)

370
mpp/vproc/inc/vdpp_api.h Normal file
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@ -0,0 +1,370 @@
/* SPDX-License-Identifier: Apache-2.0 OR MIT */
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*/
#ifndef __VDPP_API_H__
#define __VDPP_API_H__
#include <stdbool.h>
#include "mpp_debug.h"
#include "mpp_frame.h"
#define CEIL(a) (int)( (double)(a) > (int)(a) ? (int)((a)+1) : (int)(a) )
#define FLOOR(a) (int)( (double)(a) < (int)(a) ? (int)((a)-1) : (int)(a) )
#define ROUND(a) (int)( (a) > 0 ? ((double) (a) + 0.5) : ((double) (a) - 0.5) )
#define RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_BITS (8)
#define RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_NUMS (1 << (RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_BITS))
#define RKVOP_PQ_PREPROCESS_HIST_BITS_VERI (4)
#define RKVOP_PQ_PREPROCESS_HIST_BITS_HORI (4)
#define RKVOP_PQ_PREPROCESS_HIST_SIZE_VERI (1 << RKVOP_PQ_PREPROCESS_HIST_BITS_VERI) /* 16 */
#define RKVOP_PQ_PREPROCESS_HIST_SIZE_HORI (1 << RKVOP_PQ_PREPROCESS_HIST_BITS_HORI) /* 16 */
#define RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_BITS (4)
#define RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_NUMS (1 << (RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_BITS))
#define VDPP_COLOR_SPACE_LIMIT_RANGE (0)
#define VDPP_COLOR_SPACE_FULL_RANGE (1)
#define VDPP_WORK_MODE_2 (2)
#define VDPP_WORK_MODE_3 (3) /* hist mode */
#define VDPP_DMSR_EN (4)
#define VDPP_ES_EN (2)
#define VDPP_SHARP_EN (1)
/* DCI horizontal scale down mode select */
#define VDPP_DCI_HSD_DISABLE (0)
#define VDPP_DCI_HSD_MODE_1 (1)
/* DCI vertical scale down mode select */
#define VDPP_DCI_VSD_DISABLE (0)
#define VDPP_DCI_VSD_MODE_1 (1)
#define VDPP_DCI_VSD_MODE_2 (2)
enum VDPP_FMT {
VDPP_FMT_YUV444 = 0,
VDPP_FMT_YUV420 = 3,
};
enum VDPP_YUV_SWAP {
VDPP_YUV_SWAP_SP_UV,
VDPP_YUV_SWAP_SP_VU,
};
enum VDPP_PARAM_TYPE {
VDPP_PARAM_TYPE_COM,
VDPP_PARAM_TYPE_DMSR,
VDPP_PARAM_TYPE_ZME_COM,
VDPP_PARAM_TYPE_ZME_COEFF,
VDPP_PARAM_TYPE_COM2 = 0x10,
VDPP_PARAM_TYPE_ES,
VDPP_PARAM_TYPE_HIST,
VDPP_PARAM_TYPE_SHARP,
};
typedef enum VdppCmd_e {
VDPP_CMD_INIT, /* reset msg to all zero */
VDPP_CMD_SET_SRC, /* config source image info */
VDPP_CMD_SET_DST, /* config destination image info */
VDPP_CMD_SET_COM_CFG,
/* DMSR command */
VDPP_CMD_SET_DMSR_CFG = 0x0100, /* config DMSR configure */
/* ZME command */
VDPP_CMD_SET_ZME_COM_CFG = 0x0200, /* config ZME COM configure */
VDPP_CMD_SET_ZME_COEFF_CFG, /* config ZME COEFF configure */
/* hardware trigger command */
VDPP_CMD_RUN_SYNC = 0x1000, /* start sync mode process */
VDPP_CMD_SET_COM2_CFG = 0x2000, /* config common params for RK3576 */
VDPP_CMD_SET_DST_C, /* config destination chroma info */
VDPP_CMD_SET_HIST_FD, /* config dci hist fd */
VDPP_CMD_SET_ES, /* config ES configure */
VDPP_CMD_SET_DCI_HIST, /* config dci hist configure */
VDPP_CMD_SET_SHARP, /* config sharp configure */
} VdppCmd;
typedef void* VdppCtx;
typedef struct vdpp_com_ctx_t vdpp_com_ctx;
typedef struct VdppImg_t {
RK_U32 mem_addr; /* base address fd */
RK_U32 uv_addr; /* chroma address fd + (offset << 10) */
RK_U32 uv_off;
} VdppImg;
typedef struct vdpp_com_ops_t {
MPP_RET (*init)(VdppCtx *ctx);
MPP_RET (*deinit)(VdppCtx ctx);
MPP_RET (*control)(VdppCtx ctx, VdppCmd cmd, void *param);
void (*release)(vdpp_com_ctx *ctx);
} vdpp_com_ops;
typedef struct vdpp_com_ctx_t {
vdpp_com_ops *ops;
VdppCtx priv;
RK_S32 ver;
} vdpp_com_ctx;
union vdpp_api_content {
struct {
enum VDPP_YUV_SWAP sswap;
enum VDPP_FMT dfmt;
enum VDPP_YUV_SWAP dswap;
RK_S32 src_width;
RK_S32 src_height;
RK_S32 dst_width;
RK_S32 dst_height;
} com;
struct {
bool enable;
RK_U32 str_pri_y;
RK_U32 str_sec_y;
RK_U32 dumping_y;
RK_U32 wgt_pri_gain_even_1;
RK_U32 wgt_pri_gain_even_2;
RK_U32 wgt_pri_gain_odd_1;
RK_U32 wgt_pri_gain_odd_2;
RK_U32 wgt_sec_gain;
RK_U32 blk_flat_th;
RK_U32 contrast_to_conf_map_x0;
RK_U32 contrast_to_conf_map_x1;
RK_U32 contrast_to_conf_map_y0;
RK_U32 contrast_to_conf_map_y1;
RK_U32 diff_core_th0;
RK_U32 diff_core_th1;
RK_U32 diff_core_wgt0;
RK_U32 diff_core_wgt1;
RK_U32 diff_core_wgt2;
RK_U32 edge_th_low_arr[7];
RK_U32 edge_th_high_arr[7];
} dmsr;
struct {
bool bypass_enable;
bool dering_enable;
RK_U32 dering_sen_0;
RK_U32 dering_sen_1;
RK_U32 dering_blend_alpha;
RK_U32 dering_blend_beta;
RK_S16 (*tap8_coeff)[17][8];
RK_S16 (*tap6_coeff)[17][8];
} zme;
struct {
MppFrameFormat sfmt;
enum VDPP_YUV_SWAP sswap;
enum VDPP_FMT dfmt;
enum VDPP_YUV_SWAP dswap;
RK_U32 src_width;
RK_U32 src_height;
RK_U32 src_width_vir;
RK_U32 src_height_vir;
RK_U32 dst_width;
RK_U32 dst_height;
RK_U32 dst_width_vir;
RK_U32 dst_height_vir;
RK_U32 yuv_out_diff;
RK_U32 dst_c_width;
RK_U32 dst_c_height;
RK_U32 dst_c_width_vir;
RK_U32 dst_c_height_vir;
RK_U32 hist_mode_en; /* 0 - vdpp, 1 - hist */
/* high 16 bit: mask; low 3 bit: dmsr|es|sharp */
RK_U32 cfg_set;
} com2;
struct {
RK_U32 es_bEnabledES;
RK_U32 es_iAngleDelta;
RK_U32 es_iAngleDeltaExtra;
RK_U32 es_iGradNoDirTh;
RK_U32 es_iGradFlatTh;
RK_U32 es_iWgtGain;
RK_U32 es_iWgtDecay;
RK_U32 es_iLowConfTh;
RK_U32 es_iLowConfRatio;
RK_U32 es_iConfCntTh;
RK_U32 es_iWgtLocalTh;
RK_U32 es_iK1;
RK_U32 es_iK2;
RK_U32 es_iDeltaLimit;
RK_U32 es_iDiff2conf_lut_x[9];
RK_U32 es_iDiff2conf_lut_y[9];
RK_U32 es_bEndpointCheckEnable;
/* generated by es_iAngleDelta and es_iAngleDeltaExtra */
RK_U32 es_tan_hi_th;
RK_U32 es_tan_lo_th;
} es;
struct {
RK_U32 hist_cnt_en;
RK_U32 dci_hsd_mode;
RK_U32 dci_vsd_mode;
RK_U32 dci_yrgb_gather_num;
RK_U32 dci_yrgb_gather_en;
RK_U32 dci_csc_range;
} hist;
struct {
RK_S32 sharp_enable;
RK_S32 sharp_coloradj_bypass_en;
RK_S32 lti_h_enable;
RK_S32 lti_h_radius;
RK_S32 lti_h_slope;
RK_S32 lti_h_thresold;
RK_S32 lti_h_gain;
RK_S32 lti_h_noise_thr_pos;
RK_S32 lti_h_noise_thr_neg;
RK_S32 lti_v_enable;
RK_S32 lti_v_radius;
RK_S32 lti_v_slope;
RK_S32 lti_v_thresold;
RK_S32 lti_v_gain;
RK_S32 lti_v_noise_thr_pos;
RK_S32 lti_v_noise_thr_neg;
RK_S32 cti_h_enable;
RK_S32 cti_h_radius;
RK_S32 cti_h_slope;
RK_S32 cti_h_thresold;
RK_S32 cti_h_gain;
RK_S32 cti_h_noise_thr_pos;
RK_S32 cti_h_noise_thr_neg;
RK_S32 peaking_enable;
RK_S32 peaking_gain;
RK_S32 peaking_coring_enable;
RK_S32 peaking_coring_zero[8];
RK_S32 peaking_coring_thr[8];
RK_S32 peaking_coring_ratio[8];
RK_S32 peaking_gain_enable;
RK_S32 peaking_gain_pos[8];
RK_S32 peaking_gain_neg[8];
RK_S32 peaking_limit_ctrl_enable;
RK_S32 peaking_limit_ctrl_pos0[8];
RK_S32 peaking_limit_ctrl_pos1[8];
RK_S32 peaking_limit_ctrl_neg0[8];
RK_S32 peaking_limit_ctrl_neg1[8];
RK_S32 peaking_limit_ctrl_ratio[8];
RK_S32 peaking_limit_ctrl_bnd_pos[8];
RK_S32 peaking_limit_ctrl_bnd_neg[8];
RK_S32 peaking_edge_ctrl_enable;
RK_S32 peaking_edge_ctrl_non_dir_thr;
RK_S32 peaking_edge_ctrl_dir_cmp_ratio;
RK_S32 peaking_edge_ctrl_non_dir_wgt_offset;
RK_S32 peaking_edge_ctrl_non_dir_wgt_ratio;
RK_S32 peaking_edge_ctrl_dir_cnt_thr;
RK_S32 peaking_edge_ctrl_dir_cnt_avg;
RK_S32 peaking_edge_ctrl_dir_cnt_offset;
RK_S32 peaking_edge_ctrl_diag_dir_thr;
RK_S32 peaking_edge_ctrl_diag_adj_gain_tab[8];
RK_S32 peaking_estc_enable;
RK_S32 peaking_estc_delta_offset_h;
RK_S32 peaking_estc_alpha_over_h;
RK_S32 peaking_estc_alpha_under_h;
RK_S32 peaking_estc_alpha_over_unlimit_h;
RK_S32 peaking_estc_alpha_under_unlimit_h;
RK_S32 peaking_estc_delta_offset_v;
RK_S32 peaking_estc_alpha_over_v;
RK_S32 peaking_estc_alpha_under_v;
RK_S32 peaking_estc_alpha_over_unlimit_v;
RK_S32 peaking_estc_alpha_under_unlimit_v;
RK_S32 peaking_estc_delta_offset_d0;
RK_S32 peaking_estc_alpha_over_d0;
RK_S32 peaking_estc_alpha_under_d0;
RK_S32 peaking_estc_alpha_over_unlimit_d0;
RK_S32 peaking_estc_alpha_under_unlimit_d0;
RK_S32 peaking_estc_delta_offset_d1;
RK_S32 peaking_estc_alpha_over_d1;
RK_S32 peaking_estc_alpha_under_d1;
RK_S32 peaking_estc_alpha_over_unlimit_d1;
RK_S32 peaking_estc_alpha_under_unlimit_d1;
RK_S32 peaking_estc_delta_offset_non;
RK_S32 peaking_estc_alpha_over_non;
RK_S32 peaking_estc_alpha_under_non;
RK_S32 peaking_estc_alpha_over_unlimit_non;
RK_S32 peaking_estc_alpha_under_unlimit_non;
RK_S32 peaking_filter_cfg_diag_enh_coef;
RK_S32 peaking_filt_core_H0[6];
RK_S32 peaking_filt_core_H1[6];
RK_S32 peaking_filt_core_H2[6];
RK_S32 peaking_filt_core_H3[6];
RK_S32 peaking_filt_core_V0[3];
RK_S32 peaking_filt_core_V1[3];
RK_S32 peaking_filt_core_V2[3];
RK_S32 peaking_filt_core_USM[3];
RK_S32 shootctrl_enable;
RK_S32 shootctrl_filter_radius;
RK_S32 shootctrl_delta_offset;
RK_S32 shootctrl_alpha_over;
RK_S32 shootctrl_alpha_under;
RK_S32 shootctrl_alpha_over_unlimit;
RK_S32 shootctrl_alpha_under_unlimit;
RK_S32 global_gain_enable;
RK_S32 global_gain_lum_mode;
RK_S32 global_gain_lum_grd[6];
RK_S32 global_gain_lum_val[6];
RK_S32 global_gain_adp_grd[6];
RK_S32 global_gain_adp_val[6];
RK_S32 global_gain_var_grd[6];
RK_S32 global_gain_var_val[6];
RK_S32 color_ctrl_enable;
RK_S32 color_ctrl_p0_scaling_coef;
RK_S32 color_ctrl_p0_point_u;
RK_S32 color_ctrl_p0_point_v;
RK_S32 color_ctrl_p0_roll_tab[16];
RK_S32 color_ctrl_p1_scaling_coef;
RK_S32 color_ctrl_p1_point_u;
RK_S32 color_ctrl_p1_point_v;
RK_S32 color_ctrl_p1_roll_tab[16];
RK_S32 color_ctrl_p2_scaling_coef;
RK_S32 color_ctrl_p2_point_u;
RK_S32 color_ctrl_p2_point_v;
RK_S32 color_ctrl_p2_roll_tab[16];
RK_S32 color_ctrl_p3_scaling_coef;
RK_S32 color_ctrl_p3_point_u;
RK_S32 color_ctrl_p3_point_v;
RK_S32 color_ctrl_p3_roll_tab[16];
RK_S32 tex_adj_enable;
RK_S32 tex_adj_y_mode_select;
RK_S32 tex_adj_mode_select;
RK_S32 tex_adj_grd[6];
RK_S32 tex_adj_val[6];
} sharp;
};
struct vdpp_api_params {
enum VDPP_PARAM_TYPE ptype;
union vdpp_api_content param;
};
#ifdef __cplusplus
extern "C" {
#endif
vdpp_com_ctx* rockchip_vdpp_api_alloc_ctx(void);
void rockchip_vdpp_api_release_ctx(vdpp_com_ctx *com_ctx);
MPP_RET dci_hist_info_parser(RK_U8* p_pack_hist_addr, RK_U32* p_hist_local, RK_U32* p_hist_global);
#ifdef __cplusplus
}
#endif
#endif

11
mpp/vproc/vdpp/CMakeLists.txt Normal file
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@ -0,0 +1,11 @@
# vim: syntax=cmake
# ----------------------------------------------------------------------------
# add vdpp (Video Display Post Processor) implement
# ----------------------------------------------------------------------------
add_library(vproc_vdpp STATIC vdpp_api.c
vdpp.c
vdpp_common.c)
set_target_properties(vproc_vdpp PROPERTIES FOLDER "mpp/vproc/vdpp")
add_subdirectory(test)

10
mpp/vproc/vdpp/test/CMakeLists.txt Normal file
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@ -0,0 +1,10 @@
# vim: syntax=cmake
# ----------------------------------------------------------------------------
# mpp/vproc/vdpp built-in unit test case
# ----------------------------------------------------------------------------
# vdpp unit test
option(VDPP_TEST "Build base vdpp unit test" ON)
add_executable(vdpp_test vdpp_test.c)
target_link_libraries(vdpp_test ${MPP_SHARED} utils vproc_vdpp)
set_target_properties(vdpp_test PROPERTIES FOLDER "mpp/vproc/vdpp")
add_test(NAME vdpp_test COMMAND vdpp_test)

290
mpp/vproc/vdpp/test/vdpp_test.c Normal file
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@ -0,0 +1,290 @@
/* SPDX-License-Identifier: Apache-2.0 OR MIT */
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*/
#define MODULE_TAG "vdpp_test"
#include <string.h>
#include "mpp_common.h"
#include "mpp_buffer.h"
#include "utils.h"
#include "vdpp_api.h"
#define MAX_URL_LEN (256)
typedef struct VdppTestCfg_t {
RK_S32 src_width;
RK_S32 src_height;
RK_S32 src_width_vir; // 16 align
RK_S32 src_height_vir; // 8 align
RK_S32 src_swa;
RK_S32 dst_width;
RK_S32 dst_height;
RK_S32 dst_width_vir; // 16 align
RK_S32 dst_height_vir; // 2 align
RK_S32 dst_fmt;
RK_S32 dst_swa;
char src_url[MAX_URL_LEN];
char dst_url[MAX_URL_LEN];
FILE *fp_src;
FILE *fp_dst;
RK_U32 frame_num;
} VdppTestCfg;
static OptionInfo vdpp_test_cmd[] = {
{"w", "src_width", "input image width"},
{"h", "src_height", "input image height"},
{"s", "src_swap", "input image UV swap"},
{"i", "src_file", "input image file name"},
{"W", "dst_width", "output image width"},
{"H", "dst_height", "output image height"},
{"F", "dst_format", "output image format in ASCII string"},
{"S", "dst_swap", "output image UV swap"},
{"o", "dst_file", "output image file name"},
{"n", "frame_num", "frame number"}
};
static void vdpp_test_help()
{
mpp_log("usage: vdpp_test [options]\n");
mpp_log("*******************************\n");
show_options(vdpp_test_cmd);
mpp_log("*******************************\n");
mpp_log("supported ASCII format strings:\n");
mpp_log("1 - yuv444\n");
mpp_log("2 - yuv420 \n");
mpp_log("************ sample ***********\n");
mpp_log("vdpp_test -w 720 -h 480 -s 0 -i input.yuv -W 1920 -H 1080 -F yuv444 -S 0 -o output.yuv\n");
}
static RK_S32 str_to_vdpp_fmt(const char *str)
{
RK_S32 fmt = -1;
mpp_log("format %s\n", str);
if (!strcmp(str, "yuv420"))
fmt = VDPP_FMT_YUV420;
else if (!strcmp(str, "yuv444"))
fmt = VDPP_FMT_YUV444;
else
mpp_err("invalid format %s\n", str);
return fmt;
}
static MPP_RET check_input_cmd(VdppTestCfg *cfg)
{
MPP_RET ret = MPP_OK;
if (cfg->fp_src == NULL) {
mpp_err("failed to open input file %s\n", cfg->src_url);
ret = MPP_NOK;
}
return ret;
}
static inline size_t get_frm_size(RK_S32 fmt, RK_U32 w, RK_U32 h)
{
switch (fmt) {
case VDPP_FMT_YUV444:
return w * h * 3;
case VDPP_FMT_YUV420:
return w * h * 3 / 2;
default:
mpp_err("warning: unsupported input format %d", fmt);
return 0;
}
}
static void vdpp_test_set_img(vdpp_com_ctx *ctx, RK_U32 w, RK_U32 h,
VdppImg *img, RK_S32 fd, VdppCmd cmd)
{
RK_S32 y_size = w * h;
img->mem_addr = fd;
img->uv_addr = fd;
img->uv_off = y_size;
MPP_RET ret = ctx->ops->control(ctx->priv, cmd, img);
if (ret)
mpp_log_f("control %08x failed %d\n", cmd, ret);
}
void vdpp_test(VdppTestCfg *cfg)
{
vdpp_com_ctx* vdpp = rockchip_vdpp_api_alloc_ctx();
size_t srcfrmsize = get_frm_size(VDPP_FMT_YUV420, cfg->src_width_vir, cfg->src_height_vir);
size_t dstfrmsize = get_frm_size(cfg->dst_fmt, cfg->dst_width_vir, cfg->dst_height_vir);
MppBuffer srcbuf;
MppBuffer dstbuf;
RK_U8 *psrc;
RK_U8 *pdst;
RK_S32 fdsrc;
RK_S32 fddst;
struct vdpp_api_params params;
VdppImg imgsrc;
VdppImg imgdst;
mpp_assert(vdpp);
MppBufferGroup memGroup;
MPP_RET ret = MPP_NOK;
RK_U32 cnt = 0;
ret = mpp_buffer_group_get_internal(&memGroup, MPP_BUFFER_TYPE_DRM);
if (MPP_OK != ret) {
mpp_err("memGroup mpp_buffer_group_get failed\n");
mpp_assert(0);
}
mpp_buffer_get(memGroup, &srcbuf, srcfrmsize);
mpp_buffer_get(memGroup, &dstbuf, dstfrmsize);
mpp_assert(srcbuf && dstbuf);
psrc = mpp_buffer_get_ptr(srcbuf);
pdst = mpp_buffer_get_ptr(dstbuf);
fdsrc = mpp_buffer_get_fd(srcbuf);
fddst = mpp_buffer_get_fd(dstbuf);
vdpp->ops->init(&vdpp->priv);
/* use default dmsr and zme params */
/* set common params */
params.ptype = VDPP_PARAM_TYPE_COM;
params.param.com.src_width = cfg->src_width;
params.param.com.src_height = cfg->src_height;
params.param.com.sswap = cfg->src_swa;
params.param.com.dfmt = cfg->dst_fmt;
params.param.com.dst_width = cfg->dst_width;
params.param.com.dst_height = cfg->dst_height;
params.param.com.dswap = cfg->dst_swa;
vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_COM_CFG, &params);
while (1) {
if (srcfrmsize > fread(psrc, 1, srcfrmsize, cfg->fp_src)) {
mpp_log("source exhaused\n");
break;
}
if (cnt >= cfg->frame_num)
break;
/* notice the order of the input frames */
vdpp_test_set_img(vdpp, cfg->src_width_vir, cfg->src_height_vir,
&imgsrc, fdsrc, VDPP_CMD_SET_SRC);
vdpp_test_set_img(vdpp, cfg->dst_width_vir, cfg->dst_height_vir,
&imgdst, fddst, VDPP_CMD_SET_DST);
memset(pdst, 0, dstfrmsize);
vdpp->ops->control(vdpp->priv, VDPP_CMD_RUN_SYNC, NULL);
cnt ++;
if (dstfrmsize > fwrite(pdst, 1, dstfrmsize, cfg->fp_dst)) {
mpp_err("destination dump failed\n");
break;
}
}
mpp_buffer_put(srcbuf);
mpp_buffer_put(dstbuf);
if (memGroup) {
mpp_buffer_group_put(memGroup);
memGroup = NULL;
}
vdpp->ops->deinit(vdpp->priv);
rockchip_vdpp_api_release_ctx(vdpp);
}
int32_t main(int32_t argc, char **argv)
{
VdppTestCfg cfg;
int32_t ch;
if (argc < 2) {
vdpp_test_help();
return 0;
}
memset(&cfg, 0, sizeof(cfg));
cfg.src_swa = VDPP_YUV_SWAP_SP_UV;
cfg.dst_fmt = VDPP_FMT_YUV444;
cfg.dst_swa = VDPP_YUV_SWAP_SP_UV;
/* get options */
opterr = 0;
while ((ch = getopt(argc, argv, "w:h:s:i:W:H:F:S:o:n:")) != -1) {
switch (ch) {
case 'w': {
cfg.src_width = atoi(optarg);
} break;
case 'h': {
cfg.src_height = atoi(optarg);
} break;
case 's': {
cfg.src_swa = atoi(optarg);
} break;
case 'i': {
mpp_log("input filename: %s\n", optarg);
strncpy(cfg.src_url, optarg, sizeof(cfg.src_url));
cfg.fp_src = fopen(cfg.src_url, "rb");
} break;
case 'W': {
cfg.dst_width = atoi(optarg);
} break;
case 'H': {
cfg.dst_height = atoi(optarg);
} break;
case 'F': {
cfg.dst_fmt = str_to_vdpp_fmt(optarg);
} break;
case 'S': {
cfg.dst_swa = atoi(optarg);
} break;
case 'o': {
mpp_log("output filename: %s\n", optarg);
strncpy(cfg.dst_url, optarg, sizeof(cfg.dst_url));
cfg.fp_dst = fopen(cfg.dst_url, "w+b");
} break;
case 'n': {
cfg.frame_num = atoi(optarg);
} break;
default: {
} break;
}
}
cfg.src_width_vir = MPP_ALIGN(cfg.src_width, 16);
cfg.src_height_vir = MPP_ALIGN(cfg.src_height, 8);
cfg.dst_width_vir = MPP_ALIGN(cfg.dst_width, 16);
cfg.dst_height_vir = MPP_ALIGN(cfg.dst_height, 2);
if (check_input_cmd(&cfg)) {
mpp_err("failed to pass cmd line check\n");
vdpp_test_help();
return -1;
}
vdpp_test(&cfg);
if (cfg.fp_src) {
fclose(cfg.fp_src);
cfg.fp_src = NULL;
}
if (cfg.fp_dst) {
fclose(cfg.fp_dst);
cfg.fp_dst = NULL;
}
return 0;
}

458
mpp/vproc/vdpp/vdpp.c Normal file
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/* SPDX-License-Identifier: Apache-2.0 OR MIT */
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*/
#define MODULE_TAG "vdpp"
#include <sys/ioctl.h>
#include <errno.h>
#include "mpp_buffer.h"
#include "mpp_env.h"
#include "mpp_service.h"
#include "mpp_platform.h"
#include "vdpp.h"
RK_U32 vdpp_debug = 0;
static MPP_RET vdpp_params_to_reg(struct vdpp_params* src_params, struct vdpp_api_ctx *ctx)
{
struct vdpp_reg *dst_reg = &ctx->reg;
struct zme_params *zme_params = &src_params->zme_params;
memset(dst_reg, 0, sizeof(*dst_reg));
/* 1. set reg::common */
dst_reg->common.reg0.sw_vdpp_frm_en = 1;
/* 0x0004(reg1), TODO: add debug function */
dst_reg->common.reg1.sw_vdpp_src_fmt = VDPP_FMT_YUV420;
dst_reg->common.reg1.sw_vdpp_src_yuv_swap = src_params->src_yuv_swap;
dst_reg->common.reg1.sw_vdpp_dst_fmt = src_params->dst_fmt;
dst_reg->common.reg1.sw_vdpp_dst_yuv_swap = src_params->dst_yuv_swap;
dst_reg->common.reg1.sw_vdpp_dbmsr_en = src_params->dmsr_params.dmsr_enable;
/* 0x0008(reg2) */
dst_reg->common.reg2.sw_vdpp_working_mode = 2;
/* 0x000C ~ 0x001C(reg3 ~ reg7), skip */
dst_reg->common.reg4.sw_vdpp_clk_on = 1;
dst_reg->common.reg4.sw_md_clk_on = 1;
dst_reg->common.reg4.sw_dect_clk_on = 1;
dst_reg->common.reg4.sw_me_clk_on = 1;
dst_reg->common.reg4.sw_mc_clk_on = 1;
dst_reg->common.reg4.sw_eedi_clk_on = 1;
dst_reg->common.reg4.sw_ble_clk_on = 1;
dst_reg->common.reg4.sw_out_clk_on = 1;
dst_reg->common.reg4.sw_ctrl_clk_on = 1;
dst_reg->common.reg4.sw_ram_clk_on = 1;
dst_reg->common.reg4.sw_dma_clk_on = 1;
dst_reg->common.reg4.sw_reg_clk_on = 1;
/* 0x0020(reg8) */
dst_reg->common.reg8.sw_vdpp_frm_done_en = 1;
dst_reg->common.reg8.sw_vdpp_osd_max_en = 1;
dst_reg->common.reg8.sw_vdpp_bus_error_en = 1;
dst_reg->common.reg8.sw_vdpp_timeout_int_en = 1;
dst_reg->common.reg8.sw_vdpp_config_error_en = 1;
/* 0x0024 ~ 0x002C(reg9 ~ reg11), skip */
{
RK_U32 src_right_redundant = src_params->src_width % 16 == 0 ? 0 : 16 - src_params->src_width % 16;
RK_U32 src_down_redundant = src_params->src_height % 8 == 0 ? 0 : 8 - src_params->src_height % 8;
RK_U32 dst_right_redundant = src_params->dst_width % 16 == 0 ? 0 : 16 - src_params->dst_width % 16;
/* 0x0030(reg12) */
dst_reg->common.reg12.sw_vdpp_src_vir_y_stride = (src_params->src_width + src_right_redundant + 3) / 4;
/* 0x0034(reg13) */
dst_reg->common.reg13.sw_vdpp_dst_vir_y_stride = (src_params->dst_width + dst_right_redundant + 3) / 4;
/* 0x0038(reg14) */
dst_reg->common.reg14.sw_vdpp_src_pic_width = src_params->src_width + src_right_redundant - 1;
dst_reg->common.reg14.sw_vdpp_src_right_redundant = src_right_redundant;
dst_reg->common.reg14.sw_vdpp_src_pic_height = src_params->src_height + src_down_redundant - 1;
dst_reg->common.reg14.sw_vdpp_src_down_redundant = src_down_redundant;
/* 0x003C(reg15) */
dst_reg->common.reg15.sw_vdpp_dst_pic_width = src_params->dst_width + dst_right_redundant - 1;
dst_reg->common.reg15.sw_vdpp_dst_right_redundant = dst_right_redundant;
dst_reg->common.reg15.sw_vdpp_dst_pic_height = src_params->dst_height - 1;
}
/* 0x0040 ~ 0x005C(reg16 ~ reg23), skip */
dst_reg->common.reg20.sw_vdpp_timeout_en = 1;
dst_reg->common.reg20.sw_vdpp_timeout_cnt = 0x8FFFFFF;
/* 0x0060(reg24) */
dst_reg->common.reg24.sw_vdpp_src_addr_y = src_params->src.y;
/* 0x0064(reg25) */
dst_reg->common.reg25.sw_vdpp_src_addr_uv = src_params->src.cbcr;
/* 0x0068(reg26) */
dst_reg->common.reg26.sw_vdpp_dst_addr_y = src_params->dst.y;
/* 0x006C(reg27) */
dst_reg->common.reg27.sw_vdpp_dst_addr_uv = src_params->dst.cbcr;
set_dmsr_to_vdpp_reg(&src_params->dmsr_params, &ctx->dmsr);
zme_params->src_width = src_params->src_width;
zme_params->src_height = src_params->src_height;
zme_params->dst_width = src_params->dst_width;
zme_params->dst_height = src_params->dst_height;
zme_params->dst_fmt = src_params->dst_fmt;
set_zme_to_vdpp_reg(zme_params, &ctx->zme);
return MPP_OK;
}
static void vdpp_set_default_dmsr_param(struct dmsr_params* p_dmsr_param)
{
p_dmsr_param->dmsr_enable = 1;
p_dmsr_param->dmsr_str_pri_y = 10;
p_dmsr_param->dmsr_str_sec_y = 4;
p_dmsr_param->dmsr_dumping_y = 6;
p_dmsr_param->dmsr_wgt_pri_gain_even_1 = 12;
p_dmsr_param->dmsr_wgt_pri_gain_even_2 = 12;
p_dmsr_param->dmsr_wgt_pri_gain_odd_1 = 8;
p_dmsr_param->dmsr_wgt_pri_gain_odd_2 = 16;
p_dmsr_param->dmsr_wgt_sec_gain = 5;
p_dmsr_param->dmsr_blk_flat_th = 20;
p_dmsr_param->dmsr_contrast_to_conf_map_x0 = 1680;
p_dmsr_param->dmsr_contrast_to_conf_map_x1 = 6720;
p_dmsr_param->dmsr_contrast_to_conf_map_y0 = 0;
p_dmsr_param->dmsr_contrast_to_conf_map_y1 = 65535;
p_dmsr_param->dmsr_diff_core_th0 = 2;
p_dmsr_param->dmsr_diff_core_th1 = 5;
p_dmsr_param->dmsr_diff_core_wgt0 = 16;
p_dmsr_param->dmsr_diff_core_wgt1 = 12;
p_dmsr_param->dmsr_diff_core_wgt2 = 8;
p_dmsr_param->dmsr_edge_th_low_arr[0] = 30;
p_dmsr_param->dmsr_edge_th_low_arr[1] = 10;
p_dmsr_param->dmsr_edge_th_low_arr[2] = 0;
p_dmsr_param->dmsr_edge_th_low_arr[3] = 0;
p_dmsr_param->dmsr_edge_th_low_arr[4] = 0;
p_dmsr_param->dmsr_edge_th_low_arr[5] = 0;
p_dmsr_param->dmsr_edge_th_low_arr[6] = 0;
p_dmsr_param->dmsr_edge_th_high_arr[0] = 60;
p_dmsr_param->dmsr_edge_th_high_arr[1] = 40;
p_dmsr_param->dmsr_edge_th_high_arr[2] = 20;
p_dmsr_param->dmsr_edge_th_high_arr[3] = 10;
p_dmsr_param->dmsr_edge_th_high_arr[4] = 10;
p_dmsr_param->dmsr_edge_th_high_arr[5] = 10;
p_dmsr_param->dmsr_edge_th_high_arr[6] = 10;
}
static MPP_RET vdpp_set_default_param(struct vdpp_params *param)
{
/* src_fmt only NV12 supported */
param->src_yuv_swap = VDPP_YUV_SWAP_SP_UV;
param->dst_fmt = VDPP_FMT_YUV444;
param->dst_yuv_swap = VDPP_YUV_SWAP_SP_UV;
param->src_width = 1920;
param->src_height = 1080;
param->dst_width = 1920;
param->dst_height = 1080;
vdpp_set_default_dmsr_param(&param->dmsr_params);
vdpp_set_default_zme_param(&param->zme_params);
return MPP_OK;
}
MPP_RET vdpp_init(VdppCtx *ictx)
{
MPP_RET ret;
MppReqV1 mpp_req;
RK_U32 client_data = VDPP_CLIENT_TYPE;
struct vdpp_api_ctx *ctx = NULL;
if (NULL == *ictx) {
mpp_err_f("found NULL input vdpp ctx %p\n", *ictx);
return MPP_ERR_NULL_PTR;
}
ctx = *ictx;
mpp_env_get_u32("vdpp_debug", &vdpp_debug, 0);
ctx->fd = open("/dev/mpp_service", O_RDWR | O_CLOEXEC);
if (ctx->fd < 0) {
mpp_err("can NOT find device /dev/vdpp\n");
return MPP_NOK;
}
mpp_req.cmd = MPP_CMD_INIT_CLIENT_TYPE;
mpp_req.flag = 0;
mpp_req.size = sizeof(client_data);
mpp_req.data_ptr = REQ_DATA_PTR(&client_data);
memset(&ctx->params, 0, sizeof(struct vdpp_params));
/* set default parameters */
vdpp_set_default_param(&ctx->params);
ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req);
if (ret) {
mpp_err("ioctl set_client failed\n");
return MPP_NOK;
}
return MPP_OK;
}
MPP_RET vdpp_deinit(VdppCtx ictx)
{
struct vdpp_api_ctx *ctx = NULL;
if (NULL == ictx) {
mpp_err_f("found NULL input vdpp ctx %p\n", ictx);
return MPP_ERR_NULL_PTR;
}
ctx = ictx;
if (ctx->fd >= 0) {
close(ctx->fd);
ctx->fd = -1;
}
return MPP_OK;
}
static MPP_RET vdpp_set_param(struct vdpp_api_ctx *ctx,
union vdpp_api_content *param,
enum VDPP_PARAM_TYPE type)
{
MPP_RET ret = MPP_OK;
switch (type) {
case VDPP_PARAM_TYPE_COM :
ctx->params.src_yuv_swap = param->com.sswap;
ctx->params.dst_fmt = param->com.dfmt;
ctx->params.dst_yuv_swap = param->com.dswap;
ctx->params.src_width = param->com.src_width;
ctx->params.src_height = param->com.src_height;
ctx->params.dst_width = param->com.dst_width;
ctx->params.dst_height = param->com.dst_height;
break;
case VDPP_PARAM_TYPE_DMSR :
memcpy(&ctx->params.dmsr_params, &param->dmsr, sizeof(struct dmsr_params));
break;
case VDPP_PARAM_TYPE_ZME_COM :
ctx->params.zme_params.zme_bypass_en = param->zme.bypass_enable;
ctx->params.zme_params.zme_dering_enable = param->zme.dering_enable;
ctx->params.zme_params.zme_dering_sen_0 = param->zme.dering_sen_0;
ctx->params.zme_params.zme_dering_sen_1 = param->zme.dering_sen_1;
ctx->params.zme_params.zme_dering_blend_alpha = param->zme.dering_blend_alpha;
ctx->params.zme_params.zme_dering_blend_beta = param->zme.dering_blend_beta;
break;
case VDPP_PARAM_TYPE_ZME_COEFF :
if (param->zme.tap8_coeff != NULL)
ctx->params.zme_params.zme_tap8_coeff = param->zme.tap8_coeff;
if (param->zme.tap6_coeff != NULL)
ctx->params.zme_params.zme_tap6_coeff = param->zme.tap6_coeff;
break;
default:
break;
}
return ret;
}
static MPP_RET vdpp_start(struct vdpp_api_ctx *ctx)
{
MPP_RET ret;
RegOffsetInfo reg_off[2];
MppReqV1 mpp_req[9];
RK_U32 req_cnt = 0;
struct vdpp_reg *reg = NULL;
struct zme_reg *zme = NULL;
if (NULL == ctx) {
mpp_err_f("found NULL input vdpp ctx %p\n", ctx);
return MPP_ERR_NULL_PTR;
}
reg = &ctx->reg;
zme = &ctx->zme;
memset(reg_off, 0, sizeof(reg_off));
memset(mpp_req, 0, sizeof(mpp_req));
memset(reg, 0, sizeof(*reg));
vdpp_params_to_reg(&ctx->params, ctx);
mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
mpp_req[req_cnt].size = sizeof(zme->yrgb_hor_coe);
mpp_req[req_cnt].offset = VDPP_REG_OFF_YRGB_HOR_COE;
mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->yrgb_hor_coe);
req_cnt++;
mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
mpp_req[req_cnt].size = sizeof(zme->yrgb_ver_coe);
mpp_req[req_cnt].offset = VDPP_REG_OFF_YRGB_VER_COE;
mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->yrgb_ver_coe);
req_cnt++;
mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
mpp_req[req_cnt].size = sizeof(zme->cbcr_hor_coe);
mpp_req[req_cnt].offset = VDPP_REG_OFF_CBCR_HOR_COE;
mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->cbcr_hor_coe);
req_cnt++;
mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
mpp_req[req_cnt].size = sizeof(zme->cbcr_ver_coe);
mpp_req[req_cnt].offset = VDPP_REG_OFF_CBCR_VER_COE;
mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->cbcr_ver_coe);
req_cnt++;
mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
mpp_req[req_cnt].size = sizeof(zme->common);
mpp_req[req_cnt].offset = VDPP_REG_OFF_ZME_COMMON;
mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->common);
req_cnt++;
mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
mpp_req[req_cnt].size = sizeof(ctx->dmsr);
mpp_req[req_cnt].offset = VDPP_REG_OFF_DMSR;
mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&ctx->dmsr);
/* set reg offset */
reg_off[0].reg_idx = 25;
reg_off[0].offset = ctx->params.src.cbcr_offset;
reg_off[1].reg_idx = 27;
reg_off[1].offset = ctx->params.dst.cbcr_offset;
req_cnt++;
mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_ADDR_OFFSET;
mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG | MPP_FLAGS_REG_OFFSET_ALONE;
mpp_req[req_cnt].size = sizeof(reg_off);
mpp_req[req_cnt].offset = 0;
mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(reg_off);
req_cnt++;
mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
mpp_req[req_cnt].size = sizeof(reg->common);
mpp_req[req_cnt].offset = 0;
mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->common);
req_cnt++;
mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_READ;
mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG | MPP_FLAGS_LAST_MSG;
mpp_req[req_cnt].size = sizeof(&reg->common);
mpp_req[req_cnt].offset = 0;
mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->common);
ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req[0]);
if (ret) {
mpp_err_f("ioctl SET_REG failed ret %d errno %d %s\n",
ret, errno, strerror(errno));
ret = errno;
}
return ret;
}
static MPP_RET vdpp_wait(struct vdpp_api_ctx *ctx)
{
MPP_RET ret;
MppReqV1 mpp_req;
if (NULL == ctx) {
mpp_err_f("found NULL input vdpp ctx %p\n", ctx);
return MPP_ERR_NULL_PTR;
}
memset(&mpp_req, 0, sizeof(mpp_req));
mpp_req.cmd = MPP_CMD_POLL_HW_FINISH;
mpp_req.flag |= MPP_FLAGS_LAST_MSG;
ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req);
return ret;
}
static MPP_RET vdpp_done(struct vdpp_api_ctx *ctx)
{
struct vdpp_reg *reg = NULL;
if (NULL == ctx) {
mpp_err_f("found NULL input vdpp ctx %p\n", ctx);
return MPP_ERR_NULL_PTR;
}
reg = &ctx->reg;
VDPP_DBG(VDPP_DBG_INT, "ro_frm_done_sts=%d\n", reg->common.reg10.ro_frm_done_sts);
VDPP_DBG(VDPP_DBG_INT, "ro_osd_max_sts=%d\n", reg->common.reg10.ro_osd_max_sts);
VDPP_DBG(VDPP_DBG_INT, "ro_bus_error_sts=%d\n", reg->common.reg10.ro_bus_error_sts);
VDPP_DBG(VDPP_DBG_INT, "ro_timeout_sts=%d\n", reg->common.reg10.ro_timeout_sts);
VDPP_DBG(VDPP_DBG_INT, "ro_config_error_sts=%d\n", reg->common.reg10.ro_timeout_sts);
return MPP_OK;
}
static MPP_RET set_addr(struct vdpp_addr *addr, VdppImg *img)
{
if (NULL == addr || NULL == img) {
mpp_err_f("found NULL vdpp_addr %p img %p\n", addr, img);
return MPP_ERR_NULL_PTR;
}
addr->y = img->mem_addr;
addr->cbcr = img->uv_addr;
addr->cbcr_offset = img->uv_off;
return MPP_OK;
}
MPP_RET vdpp_control(VdppCtx ictx, VdppCmd cmd, void *iparam)
{
struct vdpp_api_ctx *ctx = ictx;
if ((NULL == iparam && VDPP_CMD_RUN_SYNC != cmd) ||
(NULL == ictx)) {
mpp_err_f("found NULL iparam %p cmd %d ctx %p\n", iparam, cmd, ictx);
return MPP_ERR_NULL_PTR;
}
switch (cmd) {
case VDPP_CMD_SET_COM_CFG:
case VDPP_CMD_SET_DMSR_CFG:
case VDPP_CMD_SET_ZME_COM_CFG:
case VDPP_CMD_SET_ZME_COEFF_CFG: {
struct vdpp_api_params *param = (struct vdpp_api_params *)iparam;
vdpp_set_param(ctx, &param->param, param->ptype);
break;
}
case VDPP_CMD_SET_SRC:
set_addr(&ctx->params.src, (VdppImg *)iparam);
break;
case VDPP_CMD_SET_DST:
set_addr(&ctx->params.dst, (VdppImg *)iparam);
break;
case VDPP_CMD_RUN_SYNC:
if (0 > vdpp_start(ctx))
return MPP_NOK;
vdpp_wait(ctx);
vdpp_done(ctx);
break;
default:
;
}
return MPP_OK;
}

60
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/* SPDX-License-Identifier: Apache-2.0 OR MIT */
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*/
#ifndef __VDPP_H__
#define __VDPP_H__
#include "vdpp_reg.h"
#include "vdpp_common.h"
/* vdpp log marco */
#define VDPP_DBG_TRACE (0x00000001)
#define VDPP_DBG_INT (0x00000002)
extern RK_U32 vdpp_debug;
#define VDPP_DBG(level, fmt, ...)\
do {\
if (level & vdpp_debug)\
{ mpp_log(fmt, ## __VA_ARGS__); }\
} while (0)
struct vdpp_params {
RK_U32 src_yuv_swap;
RK_U32 dst_fmt;
RK_U32 dst_yuv_swap;
RK_U32 src_width;
RK_U32 src_height;
RK_U32 dst_width;
RK_U32 dst_height;
struct vdpp_addr src; // src frame
struct vdpp_addr dst; // dst frame
struct dmsr_params dmsr_params;
struct zme_params zme_params;
};
struct vdpp_api_ctx {
RK_S32 fd;
struct vdpp_params params;
struct vdpp_reg reg;
struct dmsr_reg dmsr;
struct zme_reg zme;
};
#ifdef __cplusplus
extern "C" {
#endif
MPP_RET vdpp_init(VdppCtx *ictx);
MPP_RET vdpp_deinit(VdppCtx ictx);
MPP_RET vdpp_control(VdppCtx ictx, VdppCmd cmd, void *iparam);
#ifdef __cplusplus
}
#endif
#endif

108
mpp/vproc/vdpp/vdpp_api.c Normal file
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@ -0,0 +1,108 @@
/* SPDX-License-Identifier: Apache-2.0 OR MIT */
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*/
#include "mpp_soc.h"
#include "mpp_mem.h"
#include "vdpp_api.h"
#include "vdpp.h"
vdpp_com_ctx *rockchip_vdpp_api_alloc_ctx(void)
{
vdpp_com_ctx *com_ctx = mpp_calloc(vdpp_com_ctx, 1);
vdpp_com_ops *ops = mpp_calloc(vdpp_com_ops, 1);
VdppCtx ctx = NULL;
if (NULL == com_ctx || NULL == ops) {
mpp_err_f("failed to calloc com_ctx %p ops %p\n", com_ctx, ops);
goto __ERR;
}
ctx = mpp_calloc(struct vdpp_api_ctx, 1);
if (NULL == ctx) {
mpp_err_f("failed to calloc vdpp_api_ctx %p\n", ctx);
goto __ERR;
}
ops->init = vdpp_init;
ops->deinit = vdpp_deinit;
ops->control = vdpp_control;
com_ctx->ops = ops;
com_ctx->priv = ctx;
return com_ctx;
__ERR:
MPP_FREE(com_ctx);
MPP_FREE(ops);
MPP_FREE(ctx);
return NULL;
}
void rockchip_vdpp_api_release_ctx(vdpp_com_ctx *com_ctx)
{
if (NULL == com_ctx)
return;
MPP_FREE(com_ctx->ops);
MPP_FREE(com_ctx->priv);
MPP_FREE(com_ctx);
}
MPP_RET dci_hist_info_parser(RK_U8* p_pack_hist_addr, RK_U32* p_hist_local, RK_U32* p_hist_global)
{
RK_U32 hw_hist_idx = 0;
RK_U32 idx;
if (NULL == p_pack_hist_addr || NULL == p_hist_local || NULL == p_hist_global) {
mpp_err_f("found NULL ptr, pack_hist %p hist_local %p hist_global %p\n", p_pack_hist_addr, p_hist_local, p_hist_global);
return MPP_ERR_NULL_PTR;
}
/* Hist packed (10240 byte) -> unpacked (local: 16 * 16 * 16 * U32 + global: 256 * U32) */
for (idx = 0; idx < RKVOP_PQ_PREPROCESS_HIST_SIZE_VERI * RKVOP_PQ_PREPROCESS_HIST_SIZE_HORI * RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_NUMS; idx = idx + 4) {
RK_U32 tmp0_u18, tmp1_u18, tmp2_u18, tmp3_u18;
RK_U32 tmp0_u8, tmp1_u8, tmp2_u8, tmp3_u8, tmp4_u8, tmp5_u8, tmp6_u8, tmp7_u8, tmp8_u8;
tmp0_u8 = *(p_pack_hist_addr + hw_hist_idx + 0);
tmp1_u8 = *(p_pack_hist_addr + hw_hist_idx + 1);
tmp2_u8 = *(p_pack_hist_addr + hw_hist_idx + 2);
tmp3_u8 = *(p_pack_hist_addr + hw_hist_idx + 3);
tmp4_u8 = *(p_pack_hist_addr + hw_hist_idx + 4);
tmp5_u8 = *(p_pack_hist_addr + hw_hist_idx + 5);
tmp6_u8 = *(p_pack_hist_addr + hw_hist_idx + 6);
tmp7_u8 = *(p_pack_hist_addr + hw_hist_idx + 7);
tmp8_u8 = *(p_pack_hist_addr + hw_hist_idx + 8);
tmp0_u18 = ((tmp2_u8 & ((1 << 2) - 1)) << 16) + (tmp1_u8 << 8) + tmp0_u8;
tmp1_u18 = ((tmp4_u8 & ((1 << 4) - 1)) << 14) + (tmp3_u8 << 6) + (tmp2_u8 >> 2);
tmp2_u18 = ((tmp6_u8 & ((1 << 6) - 1)) << 12) + (tmp5_u8 << 4) + (tmp4_u8 >> 4);
tmp3_u18 = (tmp8_u8 << 10) + (tmp7_u8 << 2) + (tmp6_u8 >> 6);
*(p_hist_local + idx + 0) = tmp0_u18;
*(p_hist_local + idx + 1) = tmp1_u18;
*(p_hist_local + idx + 2) = tmp2_u18;
*(p_hist_local + idx + 3) = tmp3_u18;
hw_hist_idx += 9;
}
for (idx = 0; idx < RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_NUMS; idx++) {
RK_U32 tmp0_u8, tmp1_u8, tmp2_u8, tmp3_u8;
RK_U32 tmp_u32;
tmp0_u8 = *(p_pack_hist_addr + hw_hist_idx + 0);
tmp1_u8 = *(p_pack_hist_addr + hw_hist_idx + 1);
tmp2_u8 = *(p_pack_hist_addr + hw_hist_idx + 2);
tmp3_u8 = *(p_pack_hist_addr + hw_hist_idx + 3);
tmp_u32 = (tmp3_u8 << 24) + (tmp2_u8 << 16) + (tmp1_u8 << 8) + tmp0_u8;
*(p_hist_global + idx + 0) = tmp_u32;
hw_hist_idx += 4;
}
return MPP_OK;
}

1190
mpp/vproc/vdpp/vdpp_common.c Normal file
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File diff suppressed because it is too large Load diff

1769
mpp/vproc/vdpp/vdpp_common.h Normal file
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File diff suppressed because it is too large Load diff

174
mpp/vproc/vdpp/vdpp_reg.h Normal file
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@ -0,0 +1,174 @@
/* SPDX-License-Identifier: Apache-2.0 OR MIT */
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*/
#ifndef __VDPP_REG_H__
#define __VDPP_REG_H__
#include "rk_type.h"
#define VDPP_REG_OFF_DMSR (0x80)
#define VDPP_REG_OFF_YRGB_HOR_COE (0x2000)
#define VDPP_REG_OFF_YRGB_VER_COE (0x2200)
#define VDPP_REG_OFF_CBCR_HOR_COE (0x2400)
#define VDPP_REG_OFF_CBCR_VER_COE (0x2600)
#define VDPP_REG_OFF_ZME_COMMON (0x2800)
struct vdpp_reg {
struct {
struct {
RK_U32 sw_vdpp_frm_en : 1;
} reg0; // 0x0000
struct {
RK_U32 sw_vdpp_src_fmt : 2;
RK_U32 sw_reserved_1 : 2;
RK_U32 sw_vdpp_src_yuv_swap : 2;
RK_U32 sw_reserved_2 : 2;
RK_U32 sw_vdpp_dst_fmt : 2;
RK_U32 sw_reserved_3 : 2;
RK_U32 sw_vdpp_dst_yuv_swap : 2;
RK_U32 sw_reserved_4 : 2;
RK_U32 sw_vdpp_debug_data_en: 1;
RK_U32 sw_reserved_5 : 3;
RK_U32 sw_vdpp_rst_protect_dis : 1;
RK_U32 sys_vdpp_sreset_p : 1;
RK_U32 sw_vdpp_init_dis : 1;
RK_U32 sw_reserved_6 : 1;
RK_U32 sw_vdpp_dbmsr_en : 1;
} reg1; // 0x0004
struct {
RK_U32 sw_vdpp_working_mode : 2;
} reg2; // 0x0008
RK_U32 reg3; // 0x000C
struct {
RK_U32 sw_vdpp_clk_on : 1;
RK_U32 sw_md_clk_on : 1;
RK_U32 sw_dect_clk_on : 1;
RK_U32 sw_me_clk_on : 1;
RK_U32 sw_mc_clk_on : 1;
RK_U32 sw_eedi_clk_on : 1;
RK_U32 sw_ble_clk_on : 1;
RK_U32 sw_out_clk_on : 1;
RK_U32 sw_ctrl_clk_on : 1;
RK_U32 sw_ram_clk_on : 1;
RK_U32 sw_dma_clk_on : 1;
RK_U32 sw_reg_clk_on : 1;
} reg4; // 0x0010
struct {
RK_U32 ro_arst_finish_done : 1;
} reg5; // 0x0014
RK_U32 reg6; // 0x0018
RK_U32 reg7; // 0x001c
struct {
RK_U32 sw_vdpp_frm_done_en : 1;
RK_U32 sw_vdpp_osd_max_en : 1;
RK_U32 sw_reserved_1 : 2;
RK_U32 sw_vdpp_bus_error_en : 1;
RK_U32 sw_vdpp_timeout_int_en : 1;
RK_U32 sw_vdpp_config_error_en : 1;
} reg8; // 0x0020
struct {
RK_U32 sw_vdpp_frm_done_clr : 1;
RK_U32 sw_vdpp_osd_max_clr : 1;
RK_U32 sw_reserved_1 : 2;
RK_U32 sw_vdpp_bus_error_clr: 1;
RK_U32 sw_vdpp_timeout_int_clr : 1;
RK_U32 sw_vdpp_config_error_clr : 1;
} reg9; // 0x0024
struct {
RK_U32 ro_frm_done_sts : 1;
RK_U32 ro_osd_max_sts : 1;
RK_U32 sw_reserved_1 : 2;
RK_U32 ro_bus_error_sts : 1;
RK_U32 ro_timeout_sts : 1;
RK_U32 ro_config_error_sts : 1;
} reg10; // 0x0028, read only
struct {
RK_U32 ro_frm_done_raw : 1;
RK_U32 ro_osd_max_raw : 1;
RK_U32 sw_reserved_1 : 2;
RK_U32 ro_bus_error_raw : 1;
RK_U32 ro_timeout_raw : 1;
RK_U32 ro_config_error_raw : 1;
} reg11; // 0x002C, read only
struct {
RK_U32 sw_vdpp_src_vir_y_stride : 16;
} reg12; // 0x0030
struct {
RK_U32 sw_vdpp_dst_vir_y_stride : 16;
} reg13; // 0x0034
struct {
RK_U32 sw_vdpp_src_pic_width : 11;
RK_U32 sw_reserved_1 : 1;
RK_U32 sw_vdpp_src_right_redundant : 4;
RK_U32 sw_vdpp_src_pic_height : 11;
RK_U32 sw_reserved_2 : 1;
RK_U32 sw_vdpp_src_down_redundant : 3;
} reg14; // 0x0038
struct {
RK_U32 sw_vdpp_dst_pic_width : 11;
RK_U32 sw_reserved_1 : 1;
RK_U32 sw_vdpp_dst_right_redundant : 4;
RK_U32 sw_vdpp_dst_pic_height : 11;
} reg15; // 0x003C
RK_U32 reg16; // 0x0040
RK_U32 reg17; // 0x0044
RK_U32 reg18; // 0x0048
RK_U32 reg19; // 0x004C
struct {
RK_U32 sw_vdpp_timeout_cnt : 31;
RK_U32 sw_vdpp_timeout_en : 1;
} reg20; // 0x0050
struct {
RK_U32 svnbuild : 20;
RK_U32 minor : 8;
RK_U32 major : 4;
} reg21; // 0x0054
struct {
RK_U32 dbg_frm_cnt : 16;
} reg22; // 0x0058
RK_U32 reg23; // 0x005C
struct {
RK_U32 sw_vdpp_src_addr_y : 32;
} reg24; // 0x0060
struct {
RK_U32 sw_vdpp_src_addr_uv : 32;
} reg25; // 0x0064
struct {
RK_U32 sw_vdpp_dst_addr_y : 32;
} reg26; // 0x0068
struct {
RK_U32 sw_vdpp_dst_addr_uv : 32;
} reg27; // 0x006C
} common; // offset: 0x1000
RK_U32 reg_common_28_31[4];
};
#endif

3
osal/inc/mpp_dev_defs.h
View file

@ -43,6 +43,7 @@ typedef enum MppClientType_e {
VPU_CLIENT_VEPU22 = 24, /* 0x01000000 */
IEP_CLIENT_TYPE = 28, /* 0x10000000 */
VDPP_CLIENT_TYPE = 29, /* 0x20000000 */
VPU_CLIENT_BUTT,
} MppClientType;
@ -68,6 +69,8 @@ typedef enum MppClientType_e {
#define HAVE_VEPU22 (1 << VPU_CLIENT_VEPU22) /* 0x01000000 */
/* RK Image Enhance Processor for deinterlacing */
#define HAVE_IEP (1 << IEP_CLIENT_TYPE) /* 0x10000000 */
/* RK Image Enhance Processor for dispaly */
#define HAVE_VDPP (1 << VDPP_CLIENT_TYPE) /* 0x20000000 */
/* Platform image process hardware feature */
#define HAVE_IPP (0x00000001)