From 677b2a877ecd9d8e73743bccea57cf57d671b08e Mon Sep 17 00:00:00 2001 From: "xueman.ruan" Date: Tue, 27 Feb 2024 12:02:21 +0800 Subject: [PATCH] feat[vdpp]: Add vdpp module and vdpp_test Signed-off-by: Ding Wei Change-Id: I8bd74ad9b4404864ea3d88c7f2e57eecc4c0e35d Signed-off-by: xueman.ruan --- mpp/vproc.cmake | 7 + mpp/vproc/CMakeLists.txt | 3 +- mpp/vproc/inc/vdpp_api.h | 370 ++++++ mpp/vproc/vdpp/CMakeLists.txt | 11 + mpp/vproc/vdpp/test/CMakeLists.txt | 10 + mpp/vproc/vdpp/test/vdpp_test.c | 290 +++++ mpp/vproc/vdpp/vdpp.c | 458 +++++++ mpp/vproc/vdpp/vdpp.h | 60 + mpp/vproc/vdpp/vdpp_api.c | 108 ++ mpp/vproc/vdpp/vdpp_common.c | 1190 +++++++++++++++++++ mpp/vproc/vdpp/vdpp_common.h | 1769 ++++++++++++++++++++++++++++ mpp/vproc/vdpp/vdpp_reg.h | 174 +++ osal/inc/mpp_dev_defs.h | 3 + 13 files changed, 4452 insertions(+), 1 deletion(-) create mode 100644 mpp/vproc/inc/vdpp_api.h create mode 100644 mpp/vproc/vdpp/CMakeLists.txt create mode 100644 mpp/vproc/vdpp/test/CMakeLists.txt create mode 100644 mpp/vproc/vdpp/test/vdpp_test.c create mode 100644 mpp/vproc/vdpp/vdpp.c create mode 100644 mpp/vproc/vdpp/vdpp.h create mode 100644 mpp/vproc/vdpp/vdpp_api.c create mode 100644 mpp/vproc/vdpp/vdpp_common.c create mode 100644 mpp/vproc/vdpp/vdpp_common.h create mode 100644 mpp/vproc/vdpp/vdpp_reg.h diff --git a/mpp/vproc.cmake b/mpp/vproc.cmake index ff352e6d..dd4ef6c7 100644 --- a/mpp/vproc.cmake +++ b/mpp/vproc.cmake @@ -3,3 +3,10 @@ if( ENABLE_VPROC ) set(HAVE_VPROC true) add_definitions(-DHAVE_VPROC) endif() + +option(ENABLE_VPROC_VDPP "Enable video display post processor" OFF) +if( ENABLE_VPROC_VDPP ) + set(HAVE_VPROC_VDPP true) + set(VPROC_VDPP vproc_vdpp) + add_definitions(-DHAVE_VPROC_VDPP) +endif() diff --git a/mpp/vproc/CMakeLists.txt b/mpp/vproc/CMakeLists.txt index 5004ad2d..f860067b 100644 --- a/mpp/vproc/CMakeLists.txt +++ b/mpp/vproc/CMakeLists.txt @@ -4,8 +4,9 @@ # add mpp video process implement # ---------------------------------------------------------------------------- add_library(mpp_vproc STATIC mpp_dec_vproc.cpp mpp_vproc_dev.cpp) -target_link_libraries(mpp_vproc vproc_rga vproc_iep vproc_iep2 mpp_base) +target_link_libraries(mpp_vproc vproc_rga vproc_iep vproc_iep2 ${VPROC_VDPP} mpp_base) add_subdirectory(rga) add_subdirectory(iep) add_subdirectory(iep2) +add_subdirectory(vdpp) \ No newline at end of file diff --git a/mpp/vproc/inc/vdpp_api.h b/mpp/vproc/inc/vdpp_api.h new file mode 100644 index 00000000..f48d9698 --- /dev/null +++ b/mpp/vproc/inc/vdpp_api.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#ifndef __VDPP_API_H__ +#define __VDPP_API_H__ + +#include + +#include "mpp_debug.h" +#include "mpp_frame.h" + +#define CEIL(a) (int)( (double)(a) > (int)(a) ? (int)((a)+1) : (int)(a) ) +#define FLOOR(a) (int)( (double)(a) < (int)(a) ? (int)((a)-1) : (int)(a) ) +#define ROUND(a) (int)( (a) > 0 ? ((double) (a) + 0.5) : ((double) (a) - 0.5) ) + +#define RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_BITS (8) +#define RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_NUMS (1 << (RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_BITS)) +#define RKVOP_PQ_PREPROCESS_HIST_BITS_VERI (4) +#define RKVOP_PQ_PREPROCESS_HIST_BITS_HORI (4) +#define RKVOP_PQ_PREPROCESS_HIST_SIZE_VERI (1 << RKVOP_PQ_PREPROCESS_HIST_BITS_VERI) /* 16 */ +#define RKVOP_PQ_PREPROCESS_HIST_SIZE_HORI (1 << RKVOP_PQ_PREPROCESS_HIST_BITS_HORI) /* 16 */ +#define RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_BITS (4) +#define RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_NUMS (1 << (RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_BITS)) + +#define VDPP_COLOR_SPACE_LIMIT_RANGE (0) +#define VDPP_COLOR_SPACE_FULL_RANGE (1) + +#define VDPP_WORK_MODE_2 (2) +#define VDPP_WORK_MODE_3 (3) /* hist mode */ + +#define VDPP_DMSR_EN (4) +#define VDPP_ES_EN (2) +#define VDPP_SHARP_EN (1) + +/* DCI horizontal scale down mode select */ +#define VDPP_DCI_HSD_DISABLE (0) +#define VDPP_DCI_HSD_MODE_1 (1) +/* DCI vertical scale down mode select */ +#define VDPP_DCI_VSD_DISABLE (0) +#define VDPP_DCI_VSD_MODE_1 (1) +#define VDPP_DCI_VSD_MODE_2 (2) + +enum VDPP_FMT { + VDPP_FMT_YUV444 = 0, + VDPP_FMT_YUV420 = 3, +}; + +enum VDPP_YUV_SWAP { + VDPP_YUV_SWAP_SP_UV, + VDPP_YUV_SWAP_SP_VU, +}; + +enum VDPP_PARAM_TYPE { + VDPP_PARAM_TYPE_COM, + VDPP_PARAM_TYPE_DMSR, + VDPP_PARAM_TYPE_ZME_COM, + VDPP_PARAM_TYPE_ZME_COEFF, + VDPP_PARAM_TYPE_COM2 = 0x10, + VDPP_PARAM_TYPE_ES, + VDPP_PARAM_TYPE_HIST, + VDPP_PARAM_TYPE_SHARP, +}; + +typedef enum VdppCmd_e { + VDPP_CMD_INIT, /* reset msg to all zero */ + VDPP_CMD_SET_SRC, /* config source image info */ + VDPP_CMD_SET_DST, /* config destination image info */ + VDPP_CMD_SET_COM_CFG, + /* DMSR command */ + VDPP_CMD_SET_DMSR_CFG = 0x0100, /* config DMSR configure */ + /* ZME command */ + VDPP_CMD_SET_ZME_COM_CFG = 0x0200, /* config ZME COM configure */ + VDPP_CMD_SET_ZME_COEFF_CFG, /* config ZME COEFF configure */ + /* hardware trigger command */ + VDPP_CMD_RUN_SYNC = 0x1000, /* start sync mode process */ + VDPP_CMD_SET_COM2_CFG = 0x2000, /* config common params for RK3576 */ + VDPP_CMD_SET_DST_C, /* config destination chroma info */ + VDPP_CMD_SET_HIST_FD, /* config dci hist fd */ + VDPP_CMD_SET_ES, /* config ES configure */ + VDPP_CMD_SET_DCI_HIST, /* config dci hist configure */ + VDPP_CMD_SET_SHARP, /* config sharp configure */ +} VdppCmd; + +typedef void* VdppCtx; +typedef struct vdpp_com_ctx_t vdpp_com_ctx; + +typedef struct VdppImg_t { + RK_U32 mem_addr; /* base address fd */ + RK_U32 uv_addr; /* chroma address fd + (offset << 10) */ + RK_U32 uv_off; +} VdppImg; + +typedef struct vdpp_com_ops_t { + MPP_RET (*init)(VdppCtx *ctx); + MPP_RET (*deinit)(VdppCtx ctx); + MPP_RET (*control)(VdppCtx ctx, VdppCmd cmd, void *param); + void (*release)(vdpp_com_ctx *ctx); +} vdpp_com_ops; + +typedef struct vdpp_com_ctx_t { + vdpp_com_ops *ops; + VdppCtx priv; + RK_S32 ver; +} vdpp_com_ctx; + +union vdpp_api_content { + struct { + enum VDPP_YUV_SWAP sswap; + enum VDPP_FMT dfmt; + enum VDPP_YUV_SWAP dswap; + RK_S32 src_width; + RK_S32 src_height; + RK_S32 dst_width; + RK_S32 dst_height; + } com; + + struct { + bool enable; + RK_U32 str_pri_y; + RK_U32 str_sec_y; + RK_U32 dumping_y; + RK_U32 wgt_pri_gain_even_1; + RK_U32 wgt_pri_gain_even_2; + RK_U32 wgt_pri_gain_odd_1; + RK_U32 wgt_pri_gain_odd_2; + RK_U32 wgt_sec_gain; + RK_U32 blk_flat_th; + RK_U32 contrast_to_conf_map_x0; + RK_U32 contrast_to_conf_map_x1; + RK_U32 contrast_to_conf_map_y0; + RK_U32 contrast_to_conf_map_y1; + RK_U32 diff_core_th0; + RK_U32 diff_core_th1; + RK_U32 diff_core_wgt0; + RK_U32 diff_core_wgt1; + RK_U32 diff_core_wgt2; + RK_U32 edge_th_low_arr[7]; + RK_U32 edge_th_high_arr[7]; + } dmsr; + + struct { + bool bypass_enable; + bool dering_enable; + RK_U32 dering_sen_0; + RK_U32 dering_sen_1; + RK_U32 dering_blend_alpha; + RK_U32 dering_blend_beta; + RK_S16 (*tap8_coeff)[17][8]; + RK_S16 (*tap6_coeff)[17][8]; + } zme; + + struct { + MppFrameFormat sfmt; + enum VDPP_YUV_SWAP sswap; + enum VDPP_FMT dfmt; + enum VDPP_YUV_SWAP dswap; + RK_U32 src_width; + RK_U32 src_height; + RK_U32 src_width_vir; + RK_U32 src_height_vir; + RK_U32 dst_width; + RK_U32 dst_height; + RK_U32 dst_width_vir; + RK_U32 dst_height_vir; + RK_U32 yuv_out_diff; + RK_U32 dst_c_width; + RK_U32 dst_c_height; + RK_U32 dst_c_width_vir; + RK_U32 dst_c_height_vir; + RK_U32 hist_mode_en; /* 0 - vdpp, 1 - hist */ + /* high 16 bit: mask; low 3 bit: dmsr|es|sharp */ + RK_U32 cfg_set; + } com2; + + struct { + RK_U32 es_bEnabledES; + RK_U32 es_iAngleDelta; + RK_U32 es_iAngleDeltaExtra; + RK_U32 es_iGradNoDirTh; + RK_U32 es_iGradFlatTh; + RK_U32 es_iWgtGain; + RK_U32 es_iWgtDecay; + RK_U32 es_iLowConfTh; + RK_U32 es_iLowConfRatio; + RK_U32 es_iConfCntTh; + RK_U32 es_iWgtLocalTh; + RK_U32 es_iK1; + RK_U32 es_iK2; + RK_U32 es_iDeltaLimit; + RK_U32 es_iDiff2conf_lut_x[9]; + RK_U32 es_iDiff2conf_lut_y[9]; + RK_U32 es_bEndpointCheckEnable; + /* generated by es_iAngleDelta and es_iAngleDeltaExtra */ + RK_U32 es_tan_hi_th; + RK_U32 es_tan_lo_th; + } es; + + struct { + RK_U32 hist_cnt_en; + RK_U32 dci_hsd_mode; + RK_U32 dci_vsd_mode; + RK_U32 dci_yrgb_gather_num; + RK_U32 dci_yrgb_gather_en; + RK_U32 dci_csc_range; + } hist; + + struct { + RK_S32 sharp_enable; + RK_S32 sharp_coloradj_bypass_en; + + RK_S32 lti_h_enable; + RK_S32 lti_h_radius; + RK_S32 lti_h_slope; + RK_S32 lti_h_thresold; + RK_S32 lti_h_gain; + RK_S32 lti_h_noise_thr_pos; + RK_S32 lti_h_noise_thr_neg; + + RK_S32 lti_v_enable; + RK_S32 lti_v_radius; + RK_S32 lti_v_slope; + RK_S32 lti_v_thresold; + RK_S32 lti_v_gain; + RK_S32 lti_v_noise_thr_pos; + RK_S32 lti_v_noise_thr_neg; + + RK_S32 cti_h_enable; + RK_S32 cti_h_radius; + RK_S32 cti_h_slope; + RK_S32 cti_h_thresold; + RK_S32 cti_h_gain; + RK_S32 cti_h_noise_thr_pos; + RK_S32 cti_h_noise_thr_neg; + + RK_S32 peaking_enable; + RK_S32 peaking_gain; + + RK_S32 peaking_coring_enable; + RK_S32 peaking_coring_zero[8]; + RK_S32 peaking_coring_thr[8]; + RK_S32 peaking_coring_ratio[8]; + + RK_S32 peaking_gain_enable; + RK_S32 peaking_gain_pos[8]; + RK_S32 peaking_gain_neg[8]; + + RK_S32 peaking_limit_ctrl_enable; + RK_S32 peaking_limit_ctrl_pos0[8]; + RK_S32 peaking_limit_ctrl_pos1[8]; + RK_S32 peaking_limit_ctrl_neg0[8]; + RK_S32 peaking_limit_ctrl_neg1[8]; + RK_S32 peaking_limit_ctrl_ratio[8]; + RK_S32 peaking_limit_ctrl_bnd_pos[8]; + RK_S32 peaking_limit_ctrl_bnd_neg[8]; + + RK_S32 peaking_edge_ctrl_enable; + RK_S32 peaking_edge_ctrl_non_dir_thr; + RK_S32 peaking_edge_ctrl_dir_cmp_ratio; + RK_S32 peaking_edge_ctrl_non_dir_wgt_offset; + RK_S32 peaking_edge_ctrl_non_dir_wgt_ratio; + RK_S32 peaking_edge_ctrl_dir_cnt_thr; + RK_S32 peaking_edge_ctrl_dir_cnt_avg; + RK_S32 peaking_edge_ctrl_dir_cnt_offset; + RK_S32 peaking_edge_ctrl_diag_dir_thr; + RK_S32 peaking_edge_ctrl_diag_adj_gain_tab[8]; + + RK_S32 peaking_estc_enable; + RK_S32 peaking_estc_delta_offset_h; + RK_S32 peaking_estc_alpha_over_h; + RK_S32 peaking_estc_alpha_under_h; + RK_S32 peaking_estc_alpha_over_unlimit_h; + RK_S32 peaking_estc_alpha_under_unlimit_h; + RK_S32 peaking_estc_delta_offset_v; + RK_S32 peaking_estc_alpha_over_v; + RK_S32 peaking_estc_alpha_under_v; + RK_S32 peaking_estc_alpha_over_unlimit_v; + RK_S32 peaking_estc_alpha_under_unlimit_v; + RK_S32 peaking_estc_delta_offset_d0; + RK_S32 peaking_estc_alpha_over_d0; + RK_S32 peaking_estc_alpha_under_d0; + RK_S32 peaking_estc_alpha_over_unlimit_d0; + RK_S32 peaking_estc_alpha_under_unlimit_d0; + RK_S32 peaking_estc_delta_offset_d1; + RK_S32 peaking_estc_alpha_over_d1; + RK_S32 peaking_estc_alpha_under_d1; + RK_S32 peaking_estc_alpha_over_unlimit_d1; + RK_S32 peaking_estc_alpha_under_unlimit_d1; + RK_S32 peaking_estc_delta_offset_non; + RK_S32 peaking_estc_alpha_over_non; + RK_S32 peaking_estc_alpha_under_non; + RK_S32 peaking_estc_alpha_over_unlimit_non; + RK_S32 peaking_estc_alpha_under_unlimit_non; + RK_S32 peaking_filter_cfg_diag_enh_coef; + + RK_S32 peaking_filt_core_H0[6]; + RK_S32 peaking_filt_core_H1[6]; + RK_S32 peaking_filt_core_H2[6]; + RK_S32 peaking_filt_core_H3[6]; + RK_S32 peaking_filt_core_V0[3]; + RK_S32 peaking_filt_core_V1[3]; + RK_S32 peaking_filt_core_V2[3]; + RK_S32 peaking_filt_core_USM[3]; + + RK_S32 shootctrl_enable; + RK_S32 shootctrl_filter_radius; + RK_S32 shootctrl_delta_offset; + RK_S32 shootctrl_alpha_over; + RK_S32 shootctrl_alpha_under; + RK_S32 shootctrl_alpha_over_unlimit; + RK_S32 shootctrl_alpha_under_unlimit; + + RK_S32 global_gain_enable; + RK_S32 global_gain_lum_mode; + RK_S32 global_gain_lum_grd[6]; + RK_S32 global_gain_lum_val[6]; + RK_S32 global_gain_adp_grd[6]; + RK_S32 global_gain_adp_val[6]; + RK_S32 global_gain_var_grd[6]; + RK_S32 global_gain_var_val[6]; + + RK_S32 color_ctrl_enable; + + RK_S32 color_ctrl_p0_scaling_coef; + RK_S32 color_ctrl_p0_point_u; + RK_S32 color_ctrl_p0_point_v; + RK_S32 color_ctrl_p0_roll_tab[16]; + + RK_S32 color_ctrl_p1_scaling_coef; + RK_S32 color_ctrl_p1_point_u; + RK_S32 color_ctrl_p1_point_v; + RK_S32 color_ctrl_p1_roll_tab[16]; + + RK_S32 color_ctrl_p2_scaling_coef; + RK_S32 color_ctrl_p2_point_u; + RK_S32 color_ctrl_p2_point_v; + RK_S32 color_ctrl_p2_roll_tab[16]; + + RK_S32 color_ctrl_p3_scaling_coef; + RK_S32 color_ctrl_p3_point_u; + RK_S32 color_ctrl_p3_point_v; + RK_S32 color_ctrl_p3_roll_tab[16]; + + RK_S32 tex_adj_enable; + RK_S32 tex_adj_y_mode_select; + RK_S32 tex_adj_mode_select; + RK_S32 tex_adj_grd[6]; + RK_S32 tex_adj_val[6]; + } sharp; +}; + +struct vdpp_api_params { + enum VDPP_PARAM_TYPE ptype; + union vdpp_api_content param; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +vdpp_com_ctx* rockchip_vdpp_api_alloc_ctx(void); +void rockchip_vdpp_api_release_ctx(vdpp_com_ctx *com_ctx); +MPP_RET dci_hist_info_parser(RK_U8* p_pack_hist_addr, RK_U32* p_hist_local, RK_U32* p_hist_global); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/mpp/vproc/vdpp/CMakeLists.txt b/mpp/vproc/vdpp/CMakeLists.txt new file mode 100644 index 00000000..97e93ce4 --- /dev/null +++ b/mpp/vproc/vdpp/CMakeLists.txt @@ -0,0 +1,11 @@ +# vim: syntax=cmake + +# ---------------------------------------------------------------------------- +# add vdpp (Video Display Post Processor) implement +# ---------------------------------------------------------------------------- +add_library(vproc_vdpp STATIC vdpp_api.c + vdpp.c + vdpp_common.c) +set_target_properties(vproc_vdpp PROPERTIES FOLDER "mpp/vproc/vdpp") + +add_subdirectory(test) diff --git a/mpp/vproc/vdpp/test/CMakeLists.txt b/mpp/vproc/vdpp/test/CMakeLists.txt new file mode 100644 index 00000000..b6cc15c5 --- /dev/null +++ b/mpp/vproc/vdpp/test/CMakeLists.txt @@ -0,0 +1,10 @@ +# vim: syntax=cmake +# ---------------------------------------------------------------------------- +# mpp/vproc/vdpp built-in unit test case +# ---------------------------------------------------------------------------- +# vdpp unit test +option(VDPP_TEST "Build base vdpp unit test" ON) +add_executable(vdpp_test vdpp_test.c) +target_link_libraries(vdpp_test ${MPP_SHARED} utils vproc_vdpp) +set_target_properties(vdpp_test PROPERTIES FOLDER "mpp/vproc/vdpp") +add_test(NAME vdpp_test COMMAND vdpp_test) \ No newline at end of file diff --git a/mpp/vproc/vdpp/test/vdpp_test.c b/mpp/vproc/vdpp/test/vdpp_test.c new file mode 100644 index 00000000..081da0b5 --- /dev/null +++ b/mpp/vproc/vdpp/test/vdpp_test.c @@ -0,0 +1,290 @@ +/* SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#define MODULE_TAG "vdpp_test" + +#include + +#include "mpp_common.h" +#include "mpp_buffer.h" + +#include "utils.h" +#include "vdpp_api.h" + +#define MAX_URL_LEN (256) + +typedef struct VdppTestCfg_t { + RK_S32 src_width; + RK_S32 src_height; + RK_S32 src_width_vir; // 16 align + RK_S32 src_height_vir; // 8 align + RK_S32 src_swa; + + RK_S32 dst_width; + RK_S32 dst_height; + RK_S32 dst_width_vir; // 16 align + RK_S32 dst_height_vir; // 2 align + RK_S32 dst_fmt; + RK_S32 dst_swa; + + char src_url[MAX_URL_LEN]; + char dst_url[MAX_URL_LEN]; + + FILE *fp_src; + FILE *fp_dst; + + RK_U32 frame_num; +} VdppTestCfg; + +static OptionInfo vdpp_test_cmd[] = { + {"w", "src_width", "input image width"}, + {"h", "src_height", "input image height"}, + {"s", "src_swap", "input image UV swap"}, + {"i", "src_file", "input image file name"}, + {"W", "dst_width", "output image width"}, + {"H", "dst_height", "output image height"}, + {"F", "dst_format", "output image format in ASCII string"}, + {"S", "dst_swap", "output image UV swap"}, + {"o", "dst_file", "output image file name"}, + {"n", "frame_num", "frame number"} +}; + +static void vdpp_test_help() +{ + mpp_log("usage: vdpp_test [options]\n"); + mpp_log("*******************************\n"); + show_options(vdpp_test_cmd); + mpp_log("*******************************\n"); + mpp_log("supported ASCII format strings:\n"); + mpp_log("1 - yuv444\n"); + mpp_log("2 - yuv420 \n"); + mpp_log("************ sample ***********\n"); + mpp_log("vdpp_test -w 720 -h 480 -s 0 -i input.yuv -W 1920 -H 1080 -F yuv444 -S 0 -o output.yuv\n"); +} + +static RK_S32 str_to_vdpp_fmt(const char *str) +{ + RK_S32 fmt = -1; + + mpp_log("format %s\n", str); + + if (!strcmp(str, "yuv420")) + fmt = VDPP_FMT_YUV420; + else if (!strcmp(str, "yuv444")) + fmt = VDPP_FMT_YUV444; + else + mpp_err("invalid format %s\n", str); + + return fmt; +} + +static MPP_RET check_input_cmd(VdppTestCfg *cfg) +{ + MPP_RET ret = MPP_OK; + + if (cfg->fp_src == NULL) { + mpp_err("failed to open input file %s\n", cfg->src_url); + ret = MPP_NOK; + } + + return ret; +} + +static inline size_t get_frm_size(RK_S32 fmt, RK_U32 w, RK_U32 h) +{ + switch (fmt) { + case VDPP_FMT_YUV444: + return w * h * 3; + case VDPP_FMT_YUV420: + return w * h * 3 / 2; + default: + mpp_err("warning: unsupported input format %d", fmt); + return 0; + } +} + +static void vdpp_test_set_img(vdpp_com_ctx *ctx, RK_U32 w, RK_U32 h, + VdppImg *img, RK_S32 fd, VdppCmd cmd) +{ + RK_S32 y_size = w * h; + + img->mem_addr = fd; + img->uv_addr = fd; + img->uv_off = y_size; + + MPP_RET ret = ctx->ops->control(ctx->priv, cmd, img); + if (ret) + mpp_log_f("control %08x failed %d\n", cmd, ret); +} + +void vdpp_test(VdppTestCfg *cfg) +{ + vdpp_com_ctx* vdpp = rockchip_vdpp_api_alloc_ctx(); + size_t srcfrmsize = get_frm_size(VDPP_FMT_YUV420, cfg->src_width_vir, cfg->src_height_vir); + size_t dstfrmsize = get_frm_size(cfg->dst_fmt, cfg->dst_width_vir, cfg->dst_height_vir); + MppBuffer srcbuf; + MppBuffer dstbuf; + RK_U8 *psrc; + RK_U8 *pdst; + RK_S32 fdsrc; + RK_S32 fddst; + struct vdpp_api_params params; + + VdppImg imgsrc; + VdppImg imgdst; + + mpp_assert(vdpp); + MppBufferGroup memGroup; + MPP_RET ret = MPP_NOK; + RK_U32 cnt = 0; + + ret = mpp_buffer_group_get_internal(&memGroup, MPP_BUFFER_TYPE_DRM); + if (MPP_OK != ret) { + mpp_err("memGroup mpp_buffer_group_get failed\n"); + mpp_assert(0); + } + + mpp_buffer_get(memGroup, &srcbuf, srcfrmsize); + mpp_buffer_get(memGroup, &dstbuf, dstfrmsize); + mpp_assert(srcbuf && dstbuf); + + psrc = mpp_buffer_get_ptr(srcbuf); + pdst = mpp_buffer_get_ptr(dstbuf); + fdsrc = mpp_buffer_get_fd(srcbuf); + fddst = mpp_buffer_get_fd(dstbuf); + vdpp->ops->init(&vdpp->priv); + + /* use default dmsr and zme params */ + /* set common params */ + params.ptype = VDPP_PARAM_TYPE_COM; + params.param.com.src_width = cfg->src_width; + params.param.com.src_height = cfg->src_height; + params.param.com.sswap = cfg->src_swa; + params.param.com.dfmt = cfg->dst_fmt; + params.param.com.dst_width = cfg->dst_width; + params.param.com.dst_height = cfg->dst_height; + params.param.com.dswap = cfg->dst_swa; + vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_COM_CFG, ¶ms); + + while (1) { + if (srcfrmsize > fread(psrc, 1, srcfrmsize, cfg->fp_src)) { + mpp_log("source exhaused\n"); + break; + } + if (cnt >= cfg->frame_num) + break; + + /* notice the order of the input frames */ + vdpp_test_set_img(vdpp, cfg->src_width_vir, cfg->src_height_vir, + &imgsrc, fdsrc, VDPP_CMD_SET_SRC); + vdpp_test_set_img(vdpp, cfg->dst_width_vir, cfg->dst_height_vir, + &imgdst, fddst, VDPP_CMD_SET_DST); + + memset(pdst, 0, dstfrmsize); + vdpp->ops->control(vdpp->priv, VDPP_CMD_RUN_SYNC, NULL); + cnt ++; + + if (dstfrmsize > fwrite(pdst, 1, dstfrmsize, cfg->fp_dst)) { + mpp_err("destination dump failed\n"); + break; + } + + } + + mpp_buffer_put(srcbuf); + mpp_buffer_put(dstbuf); + + if (memGroup) { + mpp_buffer_group_put(memGroup); + memGroup = NULL; + } + + vdpp->ops->deinit(vdpp->priv); + + rockchip_vdpp_api_release_ctx(vdpp); +} + +int32_t main(int32_t argc, char **argv) +{ + VdppTestCfg cfg; + int32_t ch; + + if (argc < 2) { + vdpp_test_help(); + return 0; + } + + memset(&cfg, 0, sizeof(cfg)); + cfg.src_swa = VDPP_YUV_SWAP_SP_UV; + cfg.dst_fmt = VDPP_FMT_YUV444; + cfg.dst_swa = VDPP_YUV_SWAP_SP_UV; + + /* get options */ + opterr = 0; + while ((ch = getopt(argc, argv, "w:h:s:i:W:H:F:S:o:n:")) != -1) { + switch (ch) { + case 'w': { + cfg.src_width = atoi(optarg); + } break; + case 'h': { + cfg.src_height = atoi(optarg); + } break; + case 's': { + cfg.src_swa = atoi(optarg); + } break; + case 'i': { + mpp_log("input filename: %s\n", optarg); + strncpy(cfg.src_url, optarg, sizeof(cfg.src_url)); + cfg.fp_src = fopen(cfg.src_url, "rb"); + } break; + case 'W': { + cfg.dst_width = atoi(optarg); + } break; + case 'H': { + cfg.dst_height = atoi(optarg); + } break; + case 'F': { + cfg.dst_fmt = str_to_vdpp_fmt(optarg); + } break; + case 'S': { + cfg.dst_swa = atoi(optarg); + } break; + case 'o': { + mpp_log("output filename: %s\n", optarg); + strncpy(cfg.dst_url, optarg, sizeof(cfg.dst_url)); + cfg.fp_dst = fopen(cfg.dst_url, "w+b"); + } break; + case 'n': { + cfg.frame_num = atoi(optarg); + } break; + default: { + } break; + } + } + cfg.src_width_vir = MPP_ALIGN(cfg.src_width, 16); + cfg.src_height_vir = MPP_ALIGN(cfg.src_height, 8); + cfg.dst_width_vir = MPP_ALIGN(cfg.dst_width, 16); + cfg.dst_height_vir = MPP_ALIGN(cfg.dst_height, 2); + + if (check_input_cmd(&cfg)) { + mpp_err("failed to pass cmd line check\n"); + vdpp_test_help(); + return -1; + } + + vdpp_test(&cfg); + + if (cfg.fp_src) { + fclose(cfg.fp_src); + cfg.fp_src = NULL; + } + + if (cfg.fp_dst) { + fclose(cfg.fp_dst); + cfg.fp_dst = NULL; + } + + return 0; +} diff --git a/mpp/vproc/vdpp/vdpp.c b/mpp/vproc/vdpp/vdpp.c new file mode 100644 index 00000000..bb4d47f8 --- /dev/null +++ b/mpp/vproc/vdpp/vdpp.c @@ -0,0 +1,458 @@ +/* SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#define MODULE_TAG "vdpp" + +#include +#include + +#include "mpp_buffer.h" +#include "mpp_env.h" +#include "mpp_service.h" +#include "mpp_platform.h" + +#include "vdpp.h" + +RK_U32 vdpp_debug = 0; + +static MPP_RET vdpp_params_to_reg(struct vdpp_params* src_params, struct vdpp_api_ctx *ctx) +{ + struct vdpp_reg *dst_reg = &ctx->reg; + struct zme_params *zme_params = &src_params->zme_params; + + memset(dst_reg, 0, sizeof(*dst_reg)); + + /* 1. set reg::common */ + dst_reg->common.reg0.sw_vdpp_frm_en = 1; + + /* 0x0004(reg1), TODO: add debug function */ + dst_reg->common.reg1.sw_vdpp_src_fmt = VDPP_FMT_YUV420; + dst_reg->common.reg1.sw_vdpp_src_yuv_swap = src_params->src_yuv_swap; + dst_reg->common.reg1.sw_vdpp_dst_fmt = src_params->dst_fmt; + dst_reg->common.reg1.sw_vdpp_dst_yuv_swap = src_params->dst_yuv_swap; + dst_reg->common.reg1.sw_vdpp_dbmsr_en = src_params->dmsr_params.dmsr_enable; + + /* 0x0008(reg2) */ + dst_reg->common.reg2.sw_vdpp_working_mode = 2; + + /* 0x000C ~ 0x001C(reg3 ~ reg7), skip */ + dst_reg->common.reg4.sw_vdpp_clk_on = 1; + dst_reg->common.reg4.sw_md_clk_on = 1; + dst_reg->common.reg4.sw_dect_clk_on = 1; + dst_reg->common.reg4.sw_me_clk_on = 1; + dst_reg->common.reg4.sw_mc_clk_on = 1; + dst_reg->common.reg4.sw_eedi_clk_on = 1; + dst_reg->common.reg4.sw_ble_clk_on = 1; + dst_reg->common.reg4.sw_out_clk_on = 1; + dst_reg->common.reg4.sw_ctrl_clk_on = 1; + dst_reg->common.reg4.sw_ram_clk_on = 1; + dst_reg->common.reg4.sw_dma_clk_on = 1; + dst_reg->common.reg4.sw_reg_clk_on = 1; + + /* 0x0020(reg8) */ + dst_reg->common.reg8.sw_vdpp_frm_done_en = 1; + dst_reg->common.reg8.sw_vdpp_osd_max_en = 1; + dst_reg->common.reg8.sw_vdpp_bus_error_en = 1; + dst_reg->common.reg8.sw_vdpp_timeout_int_en = 1; + dst_reg->common.reg8.sw_vdpp_config_error_en = 1; + /* 0x0024 ~ 0x002C(reg9 ~ reg11), skip */ + { + RK_U32 src_right_redundant = src_params->src_width % 16 == 0 ? 0 : 16 - src_params->src_width % 16; + RK_U32 src_down_redundant = src_params->src_height % 8 == 0 ? 0 : 8 - src_params->src_height % 8; + RK_U32 dst_right_redundant = src_params->dst_width % 16 == 0 ? 0 : 16 - src_params->dst_width % 16; + /* 0x0030(reg12) */ + dst_reg->common.reg12.sw_vdpp_src_vir_y_stride = (src_params->src_width + src_right_redundant + 3) / 4; + + /* 0x0034(reg13) */ + dst_reg->common.reg13.sw_vdpp_dst_vir_y_stride = (src_params->dst_width + dst_right_redundant + 3) / 4; + + /* 0x0038(reg14) */ + dst_reg->common.reg14.sw_vdpp_src_pic_width = src_params->src_width + src_right_redundant - 1; + dst_reg->common.reg14.sw_vdpp_src_right_redundant = src_right_redundant; + dst_reg->common.reg14.sw_vdpp_src_pic_height = src_params->src_height + src_down_redundant - 1; + dst_reg->common.reg14.sw_vdpp_src_down_redundant = src_down_redundant; + + /* 0x003C(reg15) */ + dst_reg->common.reg15.sw_vdpp_dst_pic_width = src_params->dst_width + dst_right_redundant - 1; + dst_reg->common.reg15.sw_vdpp_dst_right_redundant = dst_right_redundant; + dst_reg->common.reg15.sw_vdpp_dst_pic_height = src_params->dst_height - 1; + } + /* 0x0040 ~ 0x005C(reg16 ~ reg23), skip */ + dst_reg->common.reg20.sw_vdpp_timeout_en = 1; + dst_reg->common.reg20.sw_vdpp_timeout_cnt = 0x8FFFFFF; + + /* 0x0060(reg24) */ + dst_reg->common.reg24.sw_vdpp_src_addr_y = src_params->src.y; + + /* 0x0064(reg25) */ + dst_reg->common.reg25.sw_vdpp_src_addr_uv = src_params->src.cbcr; + + /* 0x0068(reg26) */ + dst_reg->common.reg26.sw_vdpp_dst_addr_y = src_params->dst.y; + + /* 0x006C(reg27) */ + dst_reg->common.reg27.sw_vdpp_dst_addr_uv = src_params->dst.cbcr; + + set_dmsr_to_vdpp_reg(&src_params->dmsr_params, &ctx->dmsr); + + zme_params->src_width = src_params->src_width; + zme_params->src_height = src_params->src_height; + zme_params->dst_width = src_params->dst_width; + zme_params->dst_height = src_params->dst_height; + zme_params->dst_fmt = src_params->dst_fmt; + set_zme_to_vdpp_reg(zme_params, &ctx->zme); + + return MPP_OK; +} + +static void vdpp_set_default_dmsr_param(struct dmsr_params* p_dmsr_param) +{ + p_dmsr_param->dmsr_enable = 1; + p_dmsr_param->dmsr_str_pri_y = 10; + p_dmsr_param->dmsr_str_sec_y = 4; + p_dmsr_param->dmsr_dumping_y = 6; + p_dmsr_param->dmsr_wgt_pri_gain_even_1 = 12; + p_dmsr_param->dmsr_wgt_pri_gain_even_2 = 12; + p_dmsr_param->dmsr_wgt_pri_gain_odd_1 = 8; + p_dmsr_param->dmsr_wgt_pri_gain_odd_2 = 16; + p_dmsr_param->dmsr_wgt_sec_gain = 5; + p_dmsr_param->dmsr_blk_flat_th = 20; + p_dmsr_param->dmsr_contrast_to_conf_map_x0 = 1680; + p_dmsr_param->dmsr_contrast_to_conf_map_x1 = 6720; + p_dmsr_param->dmsr_contrast_to_conf_map_y0 = 0; + p_dmsr_param->dmsr_contrast_to_conf_map_y1 = 65535; + p_dmsr_param->dmsr_diff_core_th0 = 2; + p_dmsr_param->dmsr_diff_core_th1 = 5; + p_dmsr_param->dmsr_diff_core_wgt0 = 16; + p_dmsr_param->dmsr_diff_core_wgt1 = 12; + p_dmsr_param->dmsr_diff_core_wgt2 = 8; + p_dmsr_param->dmsr_edge_th_low_arr[0] = 30; + p_dmsr_param->dmsr_edge_th_low_arr[1] = 10; + p_dmsr_param->dmsr_edge_th_low_arr[2] = 0; + p_dmsr_param->dmsr_edge_th_low_arr[3] = 0; + p_dmsr_param->dmsr_edge_th_low_arr[4] = 0; + p_dmsr_param->dmsr_edge_th_low_arr[5] = 0; + p_dmsr_param->dmsr_edge_th_low_arr[6] = 0; + p_dmsr_param->dmsr_edge_th_high_arr[0] = 60; + p_dmsr_param->dmsr_edge_th_high_arr[1] = 40; + p_dmsr_param->dmsr_edge_th_high_arr[2] = 20; + p_dmsr_param->dmsr_edge_th_high_arr[3] = 10; + p_dmsr_param->dmsr_edge_th_high_arr[4] = 10; + p_dmsr_param->dmsr_edge_th_high_arr[5] = 10; + p_dmsr_param->dmsr_edge_th_high_arr[6] = 10; +} + +static MPP_RET vdpp_set_default_param(struct vdpp_params *param) +{ + /* src_fmt only NV12 supported */ + param->src_yuv_swap = VDPP_YUV_SWAP_SP_UV; + param->dst_fmt = VDPP_FMT_YUV444; + param->dst_yuv_swap = VDPP_YUV_SWAP_SP_UV; + param->src_width = 1920; + param->src_height = 1080; + param->dst_width = 1920; + param->dst_height = 1080; + + + vdpp_set_default_dmsr_param(¶m->dmsr_params); + vdpp_set_default_zme_param(¶m->zme_params); + + return MPP_OK; +} + +MPP_RET vdpp_init(VdppCtx *ictx) +{ + MPP_RET ret; + MppReqV1 mpp_req; + RK_U32 client_data = VDPP_CLIENT_TYPE; + struct vdpp_api_ctx *ctx = NULL; + + if (NULL == *ictx) { + mpp_err_f("found NULL input vdpp ctx %p\n", *ictx); + return MPP_ERR_NULL_PTR; + } + + ctx = *ictx; + + mpp_env_get_u32("vdpp_debug", &vdpp_debug, 0); + + ctx->fd = open("/dev/mpp_service", O_RDWR | O_CLOEXEC); + if (ctx->fd < 0) { + mpp_err("can NOT find device /dev/vdpp\n"); + return MPP_NOK; + } + + mpp_req.cmd = MPP_CMD_INIT_CLIENT_TYPE; + mpp_req.flag = 0; + mpp_req.size = sizeof(client_data); + mpp_req.data_ptr = REQ_DATA_PTR(&client_data); + + memset(&ctx->params, 0, sizeof(struct vdpp_params)); + /* set default parameters */ + vdpp_set_default_param(&ctx->params); + + ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req); + if (ret) { + mpp_err("ioctl set_client failed\n"); + return MPP_NOK; + } + + return MPP_OK; +} + +MPP_RET vdpp_deinit(VdppCtx ictx) +{ + struct vdpp_api_ctx *ctx = NULL; + + if (NULL == ictx) { + mpp_err_f("found NULL input vdpp ctx %p\n", ictx); + return MPP_ERR_NULL_PTR; + } + + ctx = ictx; + + if (ctx->fd >= 0) { + close(ctx->fd); + ctx->fd = -1; + } + + return MPP_OK; +} + +static MPP_RET vdpp_set_param(struct vdpp_api_ctx *ctx, + union vdpp_api_content *param, + enum VDPP_PARAM_TYPE type) +{ + MPP_RET ret = MPP_OK; + + switch (type) { + case VDPP_PARAM_TYPE_COM : + ctx->params.src_yuv_swap = param->com.sswap; + ctx->params.dst_fmt = param->com.dfmt; + ctx->params.dst_yuv_swap = param->com.dswap; + ctx->params.src_width = param->com.src_width; + ctx->params.src_height = param->com.src_height; + ctx->params.dst_width = param->com.dst_width; + ctx->params.dst_height = param->com.dst_height; + break; + + case VDPP_PARAM_TYPE_DMSR : + memcpy(&ctx->params.dmsr_params, ¶m->dmsr, sizeof(struct dmsr_params)); + break; + + case VDPP_PARAM_TYPE_ZME_COM : + ctx->params.zme_params.zme_bypass_en = param->zme.bypass_enable; + ctx->params.zme_params.zme_dering_enable = param->zme.dering_enable; + ctx->params.zme_params.zme_dering_sen_0 = param->zme.dering_sen_0; + ctx->params.zme_params.zme_dering_sen_1 = param->zme.dering_sen_1; + ctx->params.zme_params.zme_dering_blend_alpha = param->zme.dering_blend_alpha; + ctx->params.zme_params.zme_dering_blend_beta = param->zme.dering_blend_beta; + break; + + case VDPP_PARAM_TYPE_ZME_COEFF : + if (param->zme.tap8_coeff != NULL) + ctx->params.zme_params.zme_tap8_coeff = param->zme.tap8_coeff; + if (param->zme.tap6_coeff != NULL) + ctx->params.zme_params.zme_tap6_coeff = param->zme.tap6_coeff; + break; + + default: + break; + } + + return ret; +} + +static MPP_RET vdpp_start(struct vdpp_api_ctx *ctx) +{ + MPP_RET ret; + RegOffsetInfo reg_off[2]; + MppReqV1 mpp_req[9]; + RK_U32 req_cnt = 0; + struct vdpp_reg *reg = NULL; + struct zme_reg *zme = NULL; + + if (NULL == ctx) { + mpp_err_f("found NULL input vdpp ctx %p\n", ctx); + return MPP_ERR_NULL_PTR; + } + + reg = &ctx->reg; + zme = &ctx->zme; + + memset(reg_off, 0, sizeof(reg_off)); + memset(mpp_req, 0, sizeof(mpp_req)); + memset(reg, 0, sizeof(*reg)); + + vdpp_params_to_reg(&ctx->params, ctx); + + mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE; + mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG; + mpp_req[req_cnt].size = sizeof(zme->yrgb_hor_coe); + mpp_req[req_cnt].offset = VDPP_REG_OFF_YRGB_HOR_COE; + mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->yrgb_hor_coe); + + req_cnt++; + mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE; + mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG; + mpp_req[req_cnt].size = sizeof(zme->yrgb_ver_coe); + mpp_req[req_cnt].offset = VDPP_REG_OFF_YRGB_VER_COE; + mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->yrgb_ver_coe); + + req_cnt++; + mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE; + mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG; + mpp_req[req_cnt].size = sizeof(zme->cbcr_hor_coe); + mpp_req[req_cnt].offset = VDPP_REG_OFF_CBCR_HOR_COE; + mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->cbcr_hor_coe); + + req_cnt++; + mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE; + mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG; + mpp_req[req_cnt].size = sizeof(zme->cbcr_ver_coe); + mpp_req[req_cnt].offset = VDPP_REG_OFF_CBCR_VER_COE; + mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->cbcr_ver_coe); + + req_cnt++; + mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE; + mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG; + mpp_req[req_cnt].size = sizeof(zme->common); + mpp_req[req_cnt].offset = VDPP_REG_OFF_ZME_COMMON; + mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->common); + + req_cnt++; + mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE; + mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG; + mpp_req[req_cnt].size = sizeof(ctx->dmsr); + mpp_req[req_cnt].offset = VDPP_REG_OFF_DMSR; + mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&ctx->dmsr); + + /* set reg offset */ + reg_off[0].reg_idx = 25; + reg_off[0].offset = ctx->params.src.cbcr_offset; + reg_off[1].reg_idx = 27; + reg_off[1].offset = ctx->params.dst.cbcr_offset; + req_cnt++; + mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_ADDR_OFFSET; + mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG | MPP_FLAGS_REG_OFFSET_ALONE; + mpp_req[req_cnt].size = sizeof(reg_off); + mpp_req[req_cnt].offset = 0; + mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(reg_off); + + req_cnt++; + mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE; + mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG; + mpp_req[req_cnt].size = sizeof(reg->common); + mpp_req[req_cnt].offset = 0; + mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(®->common); + + req_cnt++; + mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_READ; + mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG | MPP_FLAGS_LAST_MSG; + mpp_req[req_cnt].size = sizeof(®->common); + mpp_req[req_cnt].offset = 0; + mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(®->common); + + ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req[0]); + + if (ret) { + mpp_err_f("ioctl SET_REG failed ret %d errno %d %s\n", + ret, errno, strerror(errno)); + ret = errno; + } + + return ret; +} + +static MPP_RET vdpp_wait(struct vdpp_api_ctx *ctx) +{ + MPP_RET ret; + MppReqV1 mpp_req; + + if (NULL == ctx) { + mpp_err_f("found NULL input vdpp ctx %p\n", ctx); + return MPP_ERR_NULL_PTR; + } + + memset(&mpp_req, 0, sizeof(mpp_req)); + mpp_req.cmd = MPP_CMD_POLL_HW_FINISH; + mpp_req.flag |= MPP_FLAGS_LAST_MSG; + + ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req); + + return ret; +} + +static MPP_RET vdpp_done(struct vdpp_api_ctx *ctx) +{ + struct vdpp_reg *reg = NULL; + + if (NULL == ctx) { + mpp_err_f("found NULL input vdpp ctx %p\n", ctx); + return MPP_ERR_NULL_PTR; + } + + reg = &ctx->reg; + + VDPP_DBG(VDPP_DBG_INT, "ro_frm_done_sts=%d\n", reg->common.reg10.ro_frm_done_sts); + VDPP_DBG(VDPP_DBG_INT, "ro_osd_max_sts=%d\n", reg->common.reg10.ro_osd_max_sts); + VDPP_DBG(VDPP_DBG_INT, "ro_bus_error_sts=%d\n", reg->common.reg10.ro_bus_error_sts); + VDPP_DBG(VDPP_DBG_INT, "ro_timeout_sts=%d\n", reg->common.reg10.ro_timeout_sts); + VDPP_DBG(VDPP_DBG_INT, "ro_config_error_sts=%d\n", reg->common.reg10.ro_timeout_sts); + + return MPP_OK; +} + +static MPP_RET set_addr(struct vdpp_addr *addr, VdppImg *img) +{ + if (NULL == addr || NULL == img) { + mpp_err_f("found NULL vdpp_addr %p img %p\n", addr, img); + return MPP_ERR_NULL_PTR; + } + + addr->y = img->mem_addr; + addr->cbcr = img->uv_addr; + addr->cbcr_offset = img->uv_off; + + return MPP_OK; +} + +MPP_RET vdpp_control(VdppCtx ictx, VdppCmd cmd, void *iparam) +{ + struct vdpp_api_ctx *ctx = ictx; + + if ((NULL == iparam && VDPP_CMD_RUN_SYNC != cmd) || + (NULL == ictx)) { + mpp_err_f("found NULL iparam %p cmd %d ctx %p\n", iparam, cmd, ictx); + return MPP_ERR_NULL_PTR; + } + + switch (cmd) { + case VDPP_CMD_SET_COM_CFG: + case VDPP_CMD_SET_DMSR_CFG: + case VDPP_CMD_SET_ZME_COM_CFG: + case VDPP_CMD_SET_ZME_COEFF_CFG: { + struct vdpp_api_params *param = (struct vdpp_api_params *)iparam; + vdpp_set_param(ctx, ¶m->param, param->ptype); + break; + } + case VDPP_CMD_SET_SRC: + set_addr(&ctx->params.src, (VdppImg *)iparam); + break; + case VDPP_CMD_SET_DST: + set_addr(&ctx->params.dst, (VdppImg *)iparam); + break; + case VDPP_CMD_RUN_SYNC: + if (0 > vdpp_start(ctx)) + return MPP_NOK; + vdpp_wait(ctx); + vdpp_done(ctx); + break; + default: + ; + } + + return MPP_OK; +} diff --git a/mpp/vproc/vdpp/vdpp.h b/mpp/vproc/vdpp/vdpp.h new file mode 100644 index 00000000..0dde80ae --- /dev/null +++ b/mpp/vproc/vdpp/vdpp.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#ifndef __VDPP_H__ +#define __VDPP_H__ + +#include "vdpp_reg.h" +#include "vdpp_common.h" + +/* vdpp log marco */ +#define VDPP_DBG_TRACE (0x00000001) +#define VDPP_DBG_INT (0x00000002) + +extern RK_U32 vdpp_debug; + +#define VDPP_DBG(level, fmt, ...)\ + do {\ + if (level & vdpp_debug)\ + { mpp_log(fmt, ## __VA_ARGS__); }\ + } while (0) + +struct vdpp_params { + RK_U32 src_yuv_swap; + RK_U32 dst_fmt; + RK_U32 dst_yuv_swap; + RK_U32 src_width; + RK_U32 src_height; + RK_U32 dst_width; + RK_U32 dst_height; + + struct vdpp_addr src; // src frame + struct vdpp_addr dst; // dst frame + + struct dmsr_params dmsr_params; + struct zme_params zme_params; +}; + +struct vdpp_api_ctx { + RK_S32 fd; + struct vdpp_params params; + struct vdpp_reg reg; + struct dmsr_reg dmsr; + struct zme_reg zme; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET vdpp_init(VdppCtx *ictx); +MPP_RET vdpp_deinit(VdppCtx ictx); +MPP_RET vdpp_control(VdppCtx ictx, VdppCmd cmd, void *iparam); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/mpp/vproc/vdpp/vdpp_api.c b/mpp/vproc/vdpp/vdpp_api.c new file mode 100644 index 00000000..2744c4fd --- /dev/null +++ b/mpp/vproc/vdpp/vdpp_api.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include "mpp_soc.h" +#include "mpp_mem.h" + +#include "vdpp_api.h" +#include "vdpp.h" + +vdpp_com_ctx *rockchip_vdpp_api_alloc_ctx(void) +{ + vdpp_com_ctx *com_ctx = mpp_calloc(vdpp_com_ctx, 1); + vdpp_com_ops *ops = mpp_calloc(vdpp_com_ops, 1); + VdppCtx ctx = NULL; + + if (NULL == com_ctx || NULL == ops) { + mpp_err_f("failed to calloc com_ctx %p ops %p\n", com_ctx, ops); + goto __ERR; + } + + ctx = mpp_calloc(struct vdpp_api_ctx, 1); + + if (NULL == ctx) { + mpp_err_f("failed to calloc vdpp_api_ctx %p\n", ctx); + goto __ERR; + } + + ops->init = vdpp_init; + ops->deinit = vdpp_deinit; + ops->control = vdpp_control; + + com_ctx->ops = ops; + com_ctx->priv = ctx; + + return com_ctx; + +__ERR: + MPP_FREE(com_ctx); + MPP_FREE(ops); + MPP_FREE(ctx); + return NULL; +} + +void rockchip_vdpp_api_release_ctx(vdpp_com_ctx *com_ctx) +{ + if (NULL == com_ctx) + return; + + MPP_FREE(com_ctx->ops); + MPP_FREE(com_ctx->priv); + MPP_FREE(com_ctx); +} + +MPP_RET dci_hist_info_parser(RK_U8* p_pack_hist_addr, RK_U32* p_hist_local, RK_U32* p_hist_global) +{ + RK_U32 hw_hist_idx = 0; + RK_U32 idx; + + if (NULL == p_pack_hist_addr || NULL == p_hist_local || NULL == p_hist_global) { + mpp_err_f("found NULL ptr, pack_hist %p hist_local %p hist_global %p\n", p_pack_hist_addr, p_hist_local, p_hist_global); + return MPP_ERR_NULL_PTR; + } + + /* Hist packed (10240 byte) -> unpacked (local: 16 * 16 * 16 * U32 + global: 256 * U32) */ + for (idx = 0; idx < RKVOP_PQ_PREPROCESS_HIST_SIZE_VERI * RKVOP_PQ_PREPROCESS_HIST_SIZE_HORI * RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_NUMS; idx = idx + 4) { + RK_U32 tmp0_u18, tmp1_u18, tmp2_u18, tmp3_u18; + RK_U32 tmp0_u8, tmp1_u8, tmp2_u8, tmp3_u8, tmp4_u8, tmp5_u8, tmp6_u8, tmp7_u8, tmp8_u8; + + tmp0_u8 = *(p_pack_hist_addr + hw_hist_idx + 0); + tmp1_u8 = *(p_pack_hist_addr + hw_hist_idx + 1); + tmp2_u8 = *(p_pack_hist_addr + hw_hist_idx + 2); + tmp3_u8 = *(p_pack_hist_addr + hw_hist_idx + 3); + tmp4_u8 = *(p_pack_hist_addr + hw_hist_idx + 4); + tmp5_u8 = *(p_pack_hist_addr + hw_hist_idx + 5); + tmp6_u8 = *(p_pack_hist_addr + hw_hist_idx + 6); + tmp7_u8 = *(p_pack_hist_addr + hw_hist_idx + 7); + tmp8_u8 = *(p_pack_hist_addr + hw_hist_idx + 8); + + tmp0_u18 = ((tmp2_u8 & ((1 << 2) - 1)) << 16) + (tmp1_u8 << 8) + tmp0_u8; + tmp1_u18 = ((tmp4_u8 & ((1 << 4) - 1)) << 14) + (tmp3_u8 << 6) + (tmp2_u8 >> 2); + tmp2_u18 = ((tmp6_u8 & ((1 << 6) - 1)) << 12) + (tmp5_u8 << 4) + (tmp4_u8 >> 4); + tmp3_u18 = (tmp8_u8 << 10) + (tmp7_u8 << 2) + (tmp6_u8 >> 6); + + *(p_hist_local + idx + 0) = tmp0_u18; + *(p_hist_local + idx + 1) = tmp1_u18; + *(p_hist_local + idx + 2) = tmp2_u18; + *(p_hist_local + idx + 3) = tmp3_u18; + hw_hist_idx += 9; + } + + for (idx = 0; idx < RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_NUMS; idx++) { + RK_U32 tmp0_u8, tmp1_u8, tmp2_u8, tmp3_u8; + RK_U32 tmp_u32; + + tmp0_u8 = *(p_pack_hist_addr + hw_hist_idx + 0); + tmp1_u8 = *(p_pack_hist_addr + hw_hist_idx + 1); + tmp2_u8 = *(p_pack_hist_addr + hw_hist_idx + 2); + tmp3_u8 = *(p_pack_hist_addr + hw_hist_idx + 3); + + tmp_u32 = (tmp3_u8 << 24) + (tmp2_u8 << 16) + (tmp1_u8 << 8) + tmp0_u8; + *(p_hist_global + idx + 0) = tmp_u32; + hw_hist_idx += 4; + } + + return MPP_OK; +} diff --git a/mpp/vproc/vdpp/vdpp_common.c b/mpp/vproc/vdpp/vdpp_common.c new file mode 100644 index 00000000..8d24b5f4 --- /dev/null +++ b/mpp/vproc/vdpp/vdpp_common.c @@ -0,0 +1,1190 @@ +/* SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#define MODULE_TAG "vdpp_common" + +#include "vdpp_common.h" + +#define VDPP_SET_ZME_COEF(index, row, col) \ + do { \ + zme->yrgb_hor_coe.reg##index.yrgb_hor_coe##row##_##col = \ + yrgb_scl_info.xscl_zme_coe[row][col]; \ + zme->yrgb_ver_coe.reg##index.yrgb_ver_coe##row##_##col = \ + yrgb_scl_info.yscl_zme_coe[row][col]; \ + zme->cbcr_hor_coe.reg##index.cbcr_hor_coe##row##_##col = \ + cbcr_scl_info.xscl_zme_coe[row][col]; \ + zme->cbcr_ver_coe.reg##index.cbcr_ver_coe##row##_##col = \ + cbcr_scl_info.yscl_zme_coe[row][col]; \ + } while (0); + +static RK_U16 vdpp_scale_threshold[] = { + 2667, 2000, 1500, 1000, 833, 700, 500, 330, 250, +}; + +static RK_S16 g_zme_tap8_coeff[11][17][8] = { +//>=2.667 + { + { 4, -12, 20, 488, 20, -12, 4, 0}, + { 4, -8, 8, 484, 36, -16, 4, 0}, + { 4, -4, -4, 476, 52, -20, 8, 0}, + { 0, 0, -16, 480, 68, -28, 8, 0}, + { 0, 4, -24, 472, 84, -32, 8, 0}, + { 0, 4, -36, 468, 100, -36, 12, 0}, + { 0, 8, -44, 456, 120, -40, 12, 0}, + { 0, 12, -52, 448, 136, -44, 12, 0}, + { 0, 12, -56, 436, 156, -48, 16, -4}, + { -4, 16, -60, 424, 176, -52, 16, -4}, + { -4, 16, -64, 412, 196, -56, 16, -4}, + { -4, 16, -68, 400, 216, -60, 16, -4}, + { -4, 20, -72, 380, 236, -64, 20, -4}, + { -4, 20, -72, 364, 256, -68, 20, -4}, + { -4, 20, -72, 348, 272, -68, 20, -4}, + { -4, 20, -72, 332, 292, -72, 20, -4}, + { -4, 20, -72, 312, 312, -72, 20, -4}, + }, +//>=2 + { + { 8, -24, 44, 456, 44, -24, 8, 0}, + { 8, -20, 28, 460, 56, -28, 8, 0}, + { 8, -16, 16, 452, 72, -32, 12, 0}, + { 4, -12, 8, 448, 88, -36, 12, 0}, + { 4, -8, -4, 444, 104, -40, 12, 0}, + { 4, -8, -16, 444, 120, -44, 12, 0}, + { 4, -4, -24, 432, 136, -48, 16, 0}, + { 4, 0, -32, 428, 152, -52, 16, -4}, + { 0, 4, -40, 424, 168, -56, 16, -4}, + { 0, 4, -44, 412, 188, -60, 16, -4}, + { 0, 8, -52, 400, 204, -60, 16, -4}, + { 0, 8, -56, 388, 224, -64, 16, -4}, + { 0, 12, -60, 372, 240, -64, 16, -4}, + { 0, 12, -64, 356, 264, -68, 16, -4}, + { 0, 12, -64, 340, 280, -68, 16, -4}, + { 0, 16, -68, 324, 296, -68, 16, -4}, + { 0, 16, -68, 308, 308, -68, 16, 0}, + }, +//>=1.5 + { + { 12, -32, 64, 424, 64, -32, 12, 0}, + { 8, -32, 52, 432, 76, -36, 12, 0}, + { 8, -28, 40, 432, 88, -40, 12, 0}, + { 8, -24, 28, 428, 104, -44, 12, 0}, + { 8, -20, 16, 424, 120, -48, 12, 0}, + { 8, -16, 8, 416, 132, -48, 12, 0}, + { 4, -16, -4, 420, 148, -52, 12, 0}, + { 4, -12, -12, 412, 164, -56, 12, 0}, + { 4, -8, -20, 400, 180, -56, 12, 0}, + { 4, -4, -28, 388, 196, -56, 12, 0}, + { 4, -4, -32, 380, 212, -60, 12, 0}, + { 4, 0, -40, 368, 228, -60, 12, 0}, + { 4, 0, -44, 356, 244, -60, 12, 0}, + { 0, 4, -48, 344, 260, -60, 12, 0}, + { 0, 4, -52, 332, 276, -60, 12, 0}, + { 0, 8, -56, 320, 292, -60, 8, 0}, + { 0, 8, -56, 304, 304, -56, 8, 0}, + }, +//>1 + { + { 12, -40, 84, 400, 84, -40, 12, 0}, + { 12, -40, 72, 404, 96, -44, 12, 0}, + { 12, -36, 60, 404, 108, -48, 12, 0}, + { 8, -32, 48, 404, 120, -48, 12, 0}, + { 8, -32, 36, 404, 136, -52, 12, 0}, + { 8, -28, 28, 396, 148, -52, 12, 0}, + { 8, -24, 16, 392, 160, -52, 12, 0}, + { 8, -20, 8, 384, 176, -56, 12, 0}, + { 8, -20, 0, 384, 188, -56, 8, 0}, + { 8, -16, -8, 372, 204, -56, 8, 0}, + { 8, -12, -16, 364, 216, -56, 8, 0}, + { 4, -12, -20, 356, 232, -56, 8, 0}, + { 4, -8, -28, 348, 244, -56, 8, 0}, + { 4, -8, -32, 332, 264, -52, 4, 0}, + { 4, -4, -36, 324, 272, -52, 4, 0}, + { 4, 0, -40, 312, 280, -48, 0, 4}, + { 4, 0, -44, 296, 296, -44, 0, 4}, + }, +//==1 + { + { 0, 0, 0, 511, 0, 0, 0, 0 }, + { -1, 3, -12, 511, 14, -4, 1, 0 }, + { -2, 6, -23, 509, 28, -8, 2, 0 }, + { -2, 9, -33, 503, 44, -12, 3, 0 }, + { -3, 11, -41, 496, 61, -16, 4, 0 }, + { -3, 13, -48, 488, 79, -21, 5, -1 }, + { -3, 14, -54, 477, 98, -25, 7, -2 }, + { -4, 16, -59, 465, 118, -30, 8, -2 }, + { -4, 17, -63, 451, 138, -35, 9, -1 }, + { -4, 18, -66, 437, 158, -39, 10, -2 }, + { -4, 18, -68, 421, 180, -44, 11, -2 }, + { -4, 18, -69, 404, 201, -48, 13, -3 }, + { -4, 18, -70, 386, 222, -52, 14, -2 }, + { -4, 18, -70, 368, 244, -56, 15, -3 }, + { -4, 18, -69, 348, 265, -59, 16, -3 }, + { -4, 18, -67, 329, 286, -63, 16, -3 }, + { -3, 17, -65, 307, 307, -65, 17, -3 }, + }, +//>=0.833 + { + { -16, 0, 145, 254, 145, 0, -16, 0 }, + { -16, -2, 140, 253, 151, 3, -17, 0 }, + { -15, -5, 135, 253, 157, 5, -18, 0 }, + { -14, -7, 129, 252, 162, 8, -18, 0 }, + { -13, -9, 123, 252, 167, 11, -19, 0 }, + { -13, -11, 118, 250, 172, 15, -19, 0 }, + { -12, -12, 112, 250, 177, 18, -20, -1 }, + { -11, -14, 107, 247, 183, 21, -20, -1 }, + { -10, -15, 101, 245, 188, 25, -21, -1 }, + { -9, -16, 96, 243, 192, 29, -21, -2 }, + { -8, -18, 90, 242, 197, 33, -22, -2 }, + { -8, -19, 85, 239, 202, 37, -22, -2 }, + { -7, -19, 80, 236, 206, 41, -22, -3 }, + { -7, -20, 75, 233, 210, 46, -22, -3 }, + { -6, -21, 69, 230, 215, 50, -22, -3 }, + { -5, -21, 65, 226, 219, 55, -22, -5 }, + { -5, -21, 60, 222, 222, 60, -21, -5 }, + }, +//>=0.7 + { + { -16, 0, 145, 254, 145, 0, -16, 0 }, + { -16, -2, 140, 253, 151, 3, -17, 0 }, + { -15, -5, 135, 253, 157, 5, -18, 0 }, + { -14, -7, 129, 252, 162, 8, -18, 0 }, + { -13, -9, 123, 252, 167, 11, -19, 0 }, + { -13, -11, 118, 250, 172, 15, -19, 0 }, + { -12, -12, 112, 250, 177, 18, -20, -1 }, + { -11, -14, 107, 247, 183, 21, -20, -1 }, + { -10, -15, 101, 245, 188, 25, -21, -1 }, + { -9, -16, 96, 243, 192, 29, -21, -2 }, + { -8, -18, 90, 242, 197, 33, -22, -2 }, + { -8, -19, 85, 239, 202, 37, -22, -2 }, + { -7, -19, 80, 236, 206, 41, -22, -3 }, + { -7, -20, 75, 233, 210, 46, -22, -3 }, + { -6, -21, 69, 230, 215, 50, -22, -3 }, + { -5, -21, 65, 226, 219, 55, -22, -5 }, + { -5, -21, 60, 222, 222, 60, -21, -5 }, + }, +//>=0.5 + { + { -16, 0, 145, 254, 145, 0, -16, 0 }, + { -16, -2, 140, 253, 151, 3, -17, 0 }, + { -15, -5, 135, 253, 157, 5, -18, 0 }, + { -14, -7, 129, 252, 162, 8, -18, 0 }, + { -13, -9, 123, 252, 167, 11, -19, 0 }, + { -13, -11, 118, 250, 172, 15, -19, 0 }, + { -12, -12, 112, 250, 177, 18, -20, -1 }, + { -11, -14, 107, 247, 183, 21, -20, -1 }, + { -10, -15, 101, 245, 188, 25, -21, -1 }, + { -9, -16, 96, 243, 192, 29, -21, -2 }, + { -8, -18, 90, 242, 197, 33, -22, -2 }, + { -8, -19, 85, 239, 202, 37, -22, -2 }, + { -7, -19, 80, 236, 206, 41, -22, -3 }, + { -7, -20, 75, 233, 210, 46, -22, -3 }, + { -6, -21, 69, 230, 215, 50, -22, -3 }, + { -5, -21, 65, 226, 219, 55, -22, -5 }, + { -5, -21, 60, 222, 222, 60, -21, -5 }, + }, +//>=0.33 + { + { -18, 18, 144, 226, 144, 19, -17, -4 }, + { -17, 16, 139, 226, 148, 21, -17, -4 }, + { -17, 13, 135, 227, 153, 24, -18, -5 }, + { -17, 11, 131, 226, 157, 27, -18, -5 }, + { -17, 9, 126, 225, 161, 30, -17, -5 }, + { -16, 6, 122, 225, 165, 33, -17, -6 }, + { -16, 4, 118, 224, 169, 37, -17, -7 }, + { -16, 2, 113, 224, 173, 40, -17, -7 }, + { -15, 0, 109, 222, 177, 43, -17, -7 }, + { -15, -1, 104, 220, 181, 47, -16, -8 }, + { -14, -3, 100, 218, 185, 51, -16, -9 }, + { -14, -5, 96, 217, 188, 54, -15, -9 }, + { -14, -6, 91, 214, 192, 58, -14, -9 }, + { -13, -7, 87, 212, 195, 62, -14, -10 }, + { -13, -9, 83, 210, 198, 66, -13, -10 }, + { -12, -10, 79, 207, 201, 70, -12, -11 }, + { -12, -11, 74, 205, 205, 74, -11, -12 }, + }, +//>=0.25 + { + { 14, 66, 113, 133, 113, 66, 14, -7 }, + { 12, 65, 112, 133, 114, 68, 15, -7 }, + { 11, 63, 111, 132, 115, 70, 17, -7 }, + { 10, 62, 110, 132, 116, 71, 18, -7 }, + { 8, 60, 108, 132, 118, 73, 20, -7 }, + { 7, 58, 107, 132, 119, 75, 21, -7 }, + { 6, 56, 106, 132, 120, 76, 23, -7 }, + { 5, 55, 105, 131, 121, 78, 24, -7 }, + { 4, 53, 103, 131, 122, 80, 26, -7 }, + { 3, 51, 102, 131, 122, 81, 28, -6 }, + { 2, 50, 101, 130, 123, 83, 29, -6 }, + { 1, 48, 99, 131, 124, 84, 31, -6 }, + { 0, 46, 98, 129, 125, 86, 33, -5 }, + { -1, 45, 97, 128, 126, 88, 34, -5 }, + { -2, 43, 95, 130, 126, 89, 36, -5 }, + { -3, 41, 94, 128, 127, 91, 38, -4 }, + { -3, 39, 92, 128, 128, 92, 39, -3 }, + }, +//others + { + { 39, 69, 93, 102, 93, 69, 39, 8 }, + { 38, 68, 92, 102, 93, 70, 40, 9 }, + { 37, 67, 91, 102, 93, 71, 41, 10 }, + { 36, 66, 91, 101, 94, 71, 42, 11 }, + { 35, 65, 90, 102, 94, 72, 43, 11 }, + { 34, 64, 89, 102, 94, 73, 44, 12 }, + { 33, 63, 88, 101, 95, 74, 45, 13 }, + { 32, 62, 88, 100, 95, 75, 46, 14 }, + { 31, 62, 87, 100, 95, 75, 47, 15 }, + { 30, 61, 86, 99, 96, 76, 48, 16 }, + { 29, 60, 86, 98, 96, 77, 49, 17 }, + { 28, 59, 85, 98, 96, 78, 50, 18 }, + { 27, 58, 84, 99, 97, 78, 50, 19 }, + { 26, 57, 83, 99, 97, 79, 51, 20 }, + { 25, 56, 83, 98, 97, 80, 52, 21 }, + { 24, 55, 82, 97, 98, 81, 53, 22 }, + { 23, 54, 81, 98, 98, 81, 54, 23 }, + } +}; + +static RK_S16 g_zme_tap6_coeff[11][17][8] = { +//>=2.667 + { + { -12, 20, 492, 20, -12, 4, 0, 0}, + { -8, 8, 488, 36, -16, 4, 0, 0}, + { -4, -4, 488, 48, -20, 4, 0, 0}, + { 0, -16, 484, 64, -24, 4, 0, 0}, + { 0, -24, 476, 80, -28, 8, 0, 0}, + { 4, -32, 464, 100, -32, 8, 0, 0}, + { 8, -40, 456, 116, -36, 8, 0, 0}, + { 8, -48, 448, 136, -40, 8, 0, 0}, + { 12, -52, 436, 152, -44, 8, 0, 0}, + { 12, -60, 424, 172, -48, 12, 0, 0}, + { 12, -64, 412, 192, -52, 12, 0, 0}, + { 16, -64, 392, 212, -56, 12, 0, 0}, + { 16, -68, 380, 232, -60, 12, 0, 0}, + { 16, -68, 360, 248, -60, 16, 0, 0}, + { 16, -68, 344, 268, -64, 16, 0, 0}, + { 16, -68, 328, 288, -68, 16, 0, 0}, + { 16, -68, 308, 308, -68, 16, 0, 0}, + }, +//>=2 + { + { -20, 40, 468, 40, -20, 4, 0, 0}, + { -16, 28, 464, 56, -24, 4, 0, 0}, + { -16, 16, 464, 68, -28, 8, 0, 0}, + { -12, 4, 460, 84, -32, 8, 0, 0}, + { -8, -4, 452, 100, -36, 8, 0, 0}, + { -4, -12, 444, 116, -40, 8, 0, 0}, + { -4, -24, 440, 136, -44, 8, 0, 0}, + { 0, -32, 432, 152, -48, 8, 0, 0}, + { 0, -36, 416, 168, -48, 12, 0, 0}, + { 4, -44, 408, 184, -52, 12, 0, 0}, + { 4, -48, 400, 200, -56, 12, 0, 0}, + { 8, -52, 380, 220, -56, 12, 0, 0}, + { 8, -56, 372, 236, -60, 12, 0, 0}, + { 8, -60, 356, 256, -60, 12, 0, 0}, + { 12, -60, 340, 268, -60, 12, 0, 0}, + { 12, -60, 324, 288, -64, 12, 0, 0}, + { 12, -64, 308, 308, -64, 12, 0, 0}, + }, +//>=1.5 + { + { -28, 60, 440, 60, -28, 8, 0, 0}, + { -28, 48, 440, 76, -32, 8, 0, 0}, + { -24, 36, 440, 88, -36, 8, 0, 0}, + { -20, 28, 432, 104, -40, 8, 0, 0}, + { -16, 16, 428, 116, -40, 8, 0, 0}, + { -16, 4, 428, 132, -44, 8, 0, 0}, + { -12, -4, 420, 148, -48, 8, 0, 0}, + { -8, -12, 408, 164, -48, 8, 0, 0}, + { -8, -20, 404, 180, -52, 8, 0, 0}, + { -4, -24, 388, 196, -52, 8, 0, 0}, + { -4, -32, 384, 212, -56, 8, 0, 0}, + { 0, -36, 372, 224, -56, 8, 0, 0}, + { 0, -40, 360, 240, -56, 8, 0, 0}, + { 4, -44, 344, 256, -56, 8, 0, 0}, + { 4, -48, 332, 272, -56, 8, 0, 0}, + { 4, -52, 316, 292, -56, 8, 0, 0}, + { 8, -52, 300, 300, -52, 8, 0, 0}, + }, +//>1 + { + { -36, 80, 420, 80, -36, 4, 0, 0}, + { -32, 68, 412, 92, -36, 8, 0, 0}, + { -28, 56, 412, 104, -40, 8, 0, 0}, + { -28, 44, 412, 116, -40, 8, 0, 0}, + { -24, 36, 404, 132, -44, 8, 0, 0}, + { -24, 24, 404, 144, -44, 8, 0, 0}, + { -20, 16, 396, 160, -48, 8, 0, 0}, + { -16, 8, 388, 172, -48, 8, 0, 0}, + { -16, 0, 380, 188, -48, 8, 0, 0}, + { -12, -8, 376, 200, -48, 4, 0, 0}, + { -12, -12, 364, 216, -48, 4, 0, 0}, + { -8, -20, 356, 228, -48, 4, 0, 0}, + { -8, -24, 344, 244, -48, 4, 0, 0}, + { -4, -32, 332, 260, -48, 4, 0, 0}, + { -4, -36, 320, 272, -44, 4, 0, 0}, + { 0, -40, 308, 288, -44, 0, 0, 0}, + { 0, -40, 296, 296, -40, 0, 0, 0}, + }, +//==1 + { + { 0, 0, 511, 0, 0, 0, 0, 0 }, + { 3, -12, 511, 13, -3, 0, 0, 0 }, + { 6, -22, 507, 28, -7, 0, 0, 0 }, + { 8, -32, 502, 44, -11, 1, 0, 0 }, + { 10, -40, 495, 61, -15, 1, 0, 0 }, + { 11, -47, 486, 79, -19, 2, 0, 0 }, + { 12, -53, 476, 98, -24, 3, 0, 0 }, + { 13, -58, 464, 117, -28, 4, 0, 0 }, + { 14, -62, 451, 137, -33, 5, 0, 0 }, + { 15, -65, 437, 157, -38, 6, 0, 0 }, + { 15, -67, 420, 179, -42, 7, 0, 0 }, + { 15, -68, 404, 200, -46, 7, 0, 0 }, + { 14, -68, 386, 221, -50, 9, 0, 0 }, + { 14, -68, 367, 243, -54, 10, 0, 0 }, + { 14, -67, 348, 264, -58, 11, 0, 0 }, + { 13, -66, 328, 286, -61, 12, 0, 0 }, + { 13, -63, 306, 306, -63, 13, 0, 0 }, + }, +//>=0.833 + { + { -31, 104, 362, 104, -31, 4, 0, 0 }, + { -30, 94, 362, 114, -32, 4, 0, 0 }, + { -29, 84, 361, 125, -32, 3, 0, 0 }, + { -28, 75, 359, 136, -33, 3, 0, 0 }, + { -27, 66, 356, 147, -33, 3, 0, 0 }, + { -25, 57, 353, 158, -33, 2, 0, 0 }, + { -24, 49, 349, 169, -33, 2, 0, 0 }, + { -22, 41, 344, 180, -32, 1, 0, 0 }, + { -20, 33, 339, 191, -31, 0, 0, 0 }, + { -19, 26, 333, 203, -30, -1, 0, 0 }, + { -17, 19, 327, 214, -29, -2, 0, 0 }, + { -16, 13, 320, 225, -27, -3, 0, 0 }, + { -14, 7, 312, 236, -25, -4, 0, 0 }, + { -13, 1, 305, 246, -22, -5, 0, 0 }, + { -11, -4, 295, 257, -19, -6, 0, 0 }, + { -10, -8, 286, 267, -16, -7, 0, 0 }, + { -9, -12, 277, 277, -12, -9, 0, 0 }, + }, +//>=0.7 + { + { -31, 104, 362, 104, -31, 4, 0, 0 }, + { -30, 94, 362, 114, -32, 4, 0, 0 }, + { -29, 84, 361, 125, -32, 3, 0, 0 }, + { -28, 75, 359, 136, -33, 3, 0, 0 }, + { -27, 66, 356, 147, -33, 3, 0, 0 }, + { -25, 57, 353, 158, -33, 2, 0, 0 }, + { -24, 49, 349, 169, -33, 2, 0, 0 }, + { -22, 41, 344, 180, -32, 1, 0, 0 }, + { -20, 33, 339, 191, -31, 0, 0, 0 }, + { -19, 26, 333, 203, -30, -1, 0, 0 }, + { -17, 19, 327, 214, -29, -2, 0, 0 }, + { -16, 13, 320, 225, -27, -3, 0, 0 }, + { -14, 7, 312, 236, -25, -4, 0, 0 }, + { -13, 1, 305, 246, -22, -5, 0, 0 }, + { -11, -4, 295, 257, -19, -6, 0, 0 }, + { -10, -8, 286, 267, -16, -7, 0, 0 }, + { -9, -12, 277, 277, -12, -9, 0, 0 }, + }, +//>=0.5 + { + { -20, 130, 297, 130, -20, -5, 0, 0 }, + { -21, 122, 298, 138, -19, -6, 0, 0 }, + { -22, 115, 297, 146, -17, -7, 0, 0 }, + { -22, 108, 296, 153, -16, -7, 0, 0 }, + { -23, 101, 295, 161, -14, -8, 0, 0 }, + { -23, 93, 294, 169, -12, -9, 0, 0 }, + { -24, 87, 292, 177, -10, -10, 0, 0 }, + { -24, 80, 289, 185, -7, -11, 0, 0 }, + { -24, 73, 286, 193, -4, -12, 0, 0 }, + { -23, 66, 283, 200, -1, -13, 0, 0 }, + { -23, 60, 279, 208, 2, -14, 0, 0 }, + { -23, 54, 276, 215, 5, -15, 0, 0 }, + { -22, 48, 271, 222, 9, -16, 0, 0 }, + { -21, 42, 266, 229, 13, -17, 0, 0 }, + { -21, 37, 261, 236, 17, -18, 0, 0 }, + { -21, 32, 255, 242, 22, -18, 0, 0 }, + { -20, 27, 249, 249, 27, -20, 0, 0 }, + }, +//>=0.33 + { + { 16, 136, 217, 136, 16, -9, 0, 0 }, + { 13, 132, 217, 141, 18, -9, 0, 0 }, + { 11, 128, 217, 145, 21, -10, 0, 0 }, + { 9, 124, 216, 149, 24, -10, 0, 0 }, + { 7, 119, 216, 153, 27, -10, 0, 0 }, + { 5, 115, 216, 157, 30, -11, 0, 0 }, + { 3, 111, 215, 161, 33, -11, 0, 0 }, + { 1, 107, 214, 165, 36, -11, 0, 0 }, + { 0, 102, 213, 169, 39, -11, 0, 0 }, + { -2, 98, 211, 173, 43, -11, 0, 0 }, + { -3, 94, 209, 177, 46, -11, 0, 0 }, + { -4, 90, 207, 180, 50, -11, 0, 0 }, + { -5, 85, 206, 184, 53, -11, 0, 0 }, + { -6, 81, 203, 187, 57, -10, 0, 0 }, + { -7, 77, 201, 190, 61, -10, 0, 0 }, + { -8, 73, 198, 193, 65, -9, 0, 0 }, + { -9, 69, 196, 196, 69, -9, 0, 0 }, + }, +//>=0.25 + { + { 66, 115, 138, 115, 66, 12, 0, 0 }, + { 64, 114, 136, 116, 68, 14, 0, 0 }, + { 63, 113, 134, 117, 70, 15, 0, 0 }, + { 61, 111, 135, 118, 71, 16, 0, 0 }, + { 59, 110, 133, 119, 73, 18, 0, 0 }, + { 57, 108, 134, 120, 74, 19, 0, 0 }, + { 55, 107, 133, 121, 76, 20, 0, 0 }, + { 53, 105, 133, 121, 78, 22, 0, 0 }, + { 51, 104, 133, 122, 79, 23, 0, 0 }, + { 49, 102, 132, 123, 81, 25, 0, 0 }, + { 47, 101, 132, 124, 82, 26, 0, 0 }, + { 45, 99, 131, 125, 84, 28, 0, 0 }, + { 44, 98, 130, 125, 85, 30, 0, 0 }, + { 42, 96, 130, 126, 87, 31, 0, 0 }, + { 40, 95, 128, 127, 89, 33, 0, 0 }, + { 38, 93, 129, 127, 90, 35, 0, 0 }, + { 36, 92, 128, 128, 92, 36, 0, 0 }, + }, +//others + { + { 80, 105, 116, 105, 80, 26, 0, 0 }, + { 79, 104, 115, 105, 81, 28, 0, 0 }, + { 77, 103, 116, 106, 81, 29, 0, 0 }, + { 76, 102, 115, 106, 82, 31, 0, 0 }, + { 74, 101, 115, 106, 83, 33, 0, 0 }, + { 73, 100, 114, 106, 84, 35, 0, 0 }, + { 71, 99, 114, 107, 84, 37, 0, 0 }, + { 70, 98, 113, 107, 85, 39, 0, 0 }, + { 68, 98, 113, 107, 86, 40, 0, 0 }, + { 67, 97, 112, 108, 86, 42, 0, 0 }, + { 65, 96, 112, 108, 87, 44, 0, 0 }, + { 63, 95, 112, 108, 88, 46, 0, 0 }, + { 62, 94, 112, 108, 88, 48, 0, 0 }, + { 60, 93, 111, 109, 89, 50, 0, 0 }, + { 58, 93, 111, 109, 90, 51, 0, 0 }, + { 57, 92, 110, 110, 90, 53, 0, 0 }, + { 55, 91, 110, 110, 91, 55, 0, 0 }, + } +}; + +static MPP_RET calc_scl_factor(struct zme_params* src_params, scl_info *p_scl_info, RK_U8 bypass_en) +{ + RK_U16 act_width = p_scl_info->act_width; + RK_U16 dsp_width = p_scl_info->dsp_width; + + RK_U16 act_height = p_scl_info->act_height; + RK_U16 dsp_height = p_scl_info->dsp_height; + + RK_U8 xsd_en = 0; + RK_U8 xsu_en = 0; + RK_U8 xscl_mode = p_scl_info->xscl_mode; + RK_U16 xscl_factor; + RK_U8 xscl_offset = 0; + + RK_U8 ysd_en = 0; + RK_U8 ysu_en = 0; + RK_U8 yscl_mode = p_scl_info->yscl_mode; + RK_U16 yscl_factor; + RK_U8 yscl_offset = 0; + + RK_U8 xavg_en = 0; + RK_U8 xgt_en = 0; + RK_U8 xgt_mode = 0; + + RK_U8 yavg_en = 0; + RK_U8 ygt_en = 0; + RK_U8 ygt_mode = 0; + + RK_U32 f_xscl_factor_t; + RK_U32 f_yscl_factor_t; + RK_U32 f_xscl_factor_t1; + RK_U32 f_yscl_factor_t1; + + if (act_width >= dsp_width * 14) { + act_width = act_width / 4; + xgt_en = 1; + xgt_mode = 3; + } else if (act_width >= dsp_width * 7) { + act_width = act_width / 2; + xgt_en = 1; + xgt_mode = 1; + } + + if (act_width > dsp_width) { + xsd_en = 1; + xsu_en = 0; + xscl_factor = GET_SCALE_FACTOR_DN(act_width, dsp_width); + } else if (act_width < dsp_width) { + xsd_en = 0; + xsu_en = 1; + xscl_factor = GET_SCALE_FACTOR_UP(act_width, dsp_width); + } else { + xsd_en = 0; + xsu_en = 0; + xscl_factor = 1 << 12; + } + + if (yscl_mode <= SCL_BIL) { + if (act_height > dsp_height * 4) { + ygt_en = 1; + ygt_mode = 1; + act_height = act_height / 4; + } else if (act_height > dsp_height * 2) { + ygt_en = 1; + ygt_mode = 0; + act_height = act_height / 2; + } else { + ygt_en = 0; + ygt_mode = 0; + } + } + + if (yscl_mode == SCL_MPH) { + if (act_height >= dsp_height * 6) { + ygt_en = 1; + ygt_mode = 3; + } + } + + if (act_height > dsp_height) { + ysd_en = 1; + ysu_en = 0; + yscl_factor = GET_SCALE_FACTOR_DN(act_height, dsp_height); + } else if (act_height < dsp_height) { + ysd_en = 0; + ysu_en = 1; + yscl_factor = GET_SCALE_FACTOR_UP(act_height, dsp_height); + } else { + ysd_en = 0; + ysu_en = 0; + yscl_factor = 1 << 12; + } + + if (xsu_en == 1) { + f_xscl_factor_t = (1 << 16) * act_width / dsp_width; + f_xscl_factor_t1 = 1000 * (1 << 16) / f_xscl_factor_t; + } else { + f_xscl_factor_t = (1 << 12) * act_width / dsp_width; + f_xscl_factor_t1 = 1000 * (1 << 12) / f_xscl_factor_t; + } + + if (ysu_en == 1) { + f_yscl_factor_t = (1 << 16) * act_height / dsp_height; + f_yscl_factor_t1 = 1000 * (1 << 16) / f_yscl_factor_t; + } else { + f_yscl_factor_t = (1 << 12) * act_height / dsp_height; + f_yscl_factor_t1 = 1000 * (1 << 12) / f_yscl_factor_t; + } + + if (f_xscl_factor_t1 >= vdpp_scale_threshold[0]) + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[0]; + else if (f_xscl_factor_t1 >= vdpp_scale_threshold[1]) + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[1]; + else if (f_xscl_factor_t1 >= vdpp_scale_threshold[2]) + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[2]; + else if (f_xscl_factor_t1 > vdpp_scale_threshold[3]) + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[3]; + else if (f_xscl_factor_t1 == vdpp_scale_threshold[3]) + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[4]; + else if (f_xscl_factor_t1 >= vdpp_scale_threshold[4]) + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[5]; + else if (f_xscl_factor_t1 >= vdpp_scale_threshold[5]) + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[6]; + else if (f_xscl_factor_t1 >= vdpp_scale_threshold[6]) + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[7]; + else if (f_xscl_factor_t1 >= vdpp_scale_threshold[7]) + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[8]; + else if (f_xscl_factor_t1 >= vdpp_scale_threshold[8]) + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[9]; + else + p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[10]; + + if (f_yscl_factor_t1 >= vdpp_scale_threshold[0]) + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[0]; + else if (f_yscl_factor_t1 >= vdpp_scale_threshold[1]) + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[1]; + else if (f_yscl_factor_t1 >= vdpp_scale_threshold[2]) + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[2]; + else if (f_yscl_factor_t1 > vdpp_scale_threshold[3]) + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[3]; + else if (f_yscl_factor_t1 == vdpp_scale_threshold[3]) + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[4]; + else if (f_yscl_factor_t1 >= vdpp_scale_threshold[4]) + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[5]; + else if (f_yscl_factor_t1 >= vdpp_scale_threshold[5]) + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[6]; + else if (f_yscl_factor_t1 >= vdpp_scale_threshold[6]) + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[7]; + else if (f_yscl_factor_t1 >= vdpp_scale_threshold[7]) + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[8]; + else if (f_yscl_factor_t1 >= vdpp_scale_threshold[8]) + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[9]; + else + p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[10]; + + p_scl_info->xsd_en = xsd_en; + p_scl_info->xsu_en = xsu_en; + p_scl_info->xscl_mode = xscl_mode; + p_scl_info->xscl_factor = xscl_factor; + p_scl_info->xscl_offset = xscl_offset; + + p_scl_info->ysd_en = ysd_en; + p_scl_info->ysu_en = ysu_en; + p_scl_info->yscl_mode = yscl_mode; + p_scl_info->yscl_factor = yscl_factor; + p_scl_info->yscl_offset = yscl_offset; + + p_scl_info->xavg_en = xavg_en; + p_scl_info->xgt_en = xgt_en; + p_scl_info->xgt_mode = xgt_mode; + + p_scl_info->yavg_en = yavg_en; + p_scl_info->ygt_en = ygt_en; + p_scl_info->ygt_mode = ygt_mode; + + if (bypass_en) { + p_scl_info->xsd_bypass = !xsd_en; + p_scl_info->xsu_bypass = !xsu_en; + p_scl_info->ys_bypass = !(ysd_en || ysu_en); + } else { + p_scl_info->xsd_bypass = 0; + p_scl_info->xsu_bypass = 0; + p_scl_info->ys_bypass = 0; + } + return MPP_OK; +} + +void set_dmsr_to_vdpp_reg(struct dmsr_params* p_dmsr_param, struct dmsr_reg* dmsr) +{ + /* 0x0080(reg0) */ + dmsr->reg0.sw_dmsr_edge_low_thre_0 = p_dmsr_param->dmsr_edge_th_low_arr[0]; + dmsr->reg0.sw_dmsr_edge_high_thre_0 = p_dmsr_param->dmsr_edge_th_high_arr[0]; + + /* 0x0084(reg1) */ + dmsr->reg1.sw_dmsr_edge_low_thre_1 = p_dmsr_param->dmsr_edge_th_low_arr[1]; + dmsr->reg1.sw_dmsr_edge_high_thre_1 = p_dmsr_param->dmsr_edge_th_high_arr[1]; + + /* 0x0088(reg2) */ + dmsr->reg2.sw_dmsr_edge_low_thre_2 = p_dmsr_param->dmsr_edge_th_low_arr[2]; + dmsr->reg2.sw_dmsr_edge_high_thre_2 = p_dmsr_param->dmsr_edge_th_high_arr[2]; + + /* 0x008C(reg3) */ + dmsr->reg3.sw_dmsr_edge_low_thre_3 = p_dmsr_param->dmsr_edge_th_low_arr[3]; + dmsr->reg3.sw_dmsr_edge_high_thre_3 = p_dmsr_param->dmsr_edge_th_high_arr[3]; + + /* 0x0090(reg4) */ + dmsr->reg4.sw_dmsr_edge_low_thre_4 = p_dmsr_param->dmsr_edge_th_low_arr[4]; + dmsr->reg4.sw_dmsr_edge_high_thre_4 = p_dmsr_param->dmsr_edge_th_high_arr[4]; + + /* 0x0094(reg5) */ + dmsr->reg5.sw_dmsr_edge_low_thre_5 = p_dmsr_param->dmsr_edge_th_low_arr[5]; + dmsr->reg5.sw_dmsr_edge_high_thre_5 = p_dmsr_param->dmsr_edge_th_high_arr[5]; + + /* 0x0098(reg6) */ + dmsr->reg6.sw_dmsr_edge_low_thre_6 = p_dmsr_param->dmsr_edge_th_low_arr[6]; + dmsr->reg6.sw_dmsr_edge_high_thre_6 = p_dmsr_param->dmsr_edge_th_high_arr[6]; + { + RK_U16 adj_mapping_k[7]; + RK_U16 tmp_diff; + RK_U16 i; + RK_U16 contrast2conf_mapping_k; + RK_U32 tmp_diff_y, tmp_diff_x; + + for (i = 0; i < 7; i++) { + tmp_diff = p_dmsr_param->dmsr_edge_th_high_arr[i] - p_dmsr_param->dmsr_edge_th_low_arr[i]; + adj_mapping_k[i] = (65535 / MPP_MAX(1, tmp_diff)); + } + tmp_diff_y = p_dmsr_param->dmsr_contrast_to_conf_map_y1 - p_dmsr_param->dmsr_contrast_to_conf_map_y0; + tmp_diff_x = MPP_MAX(p_dmsr_param->dmsr_contrast_to_conf_map_x1 - p_dmsr_param->dmsr_contrast_to_conf_map_x0, 1); + + contrast2conf_mapping_k = mpp_clip(256 * tmp_diff_y / tmp_diff_x, 0, 65535); + /* 0x009C(reg7) */ + dmsr->reg7.sw_dmsr_edge_k_0 = adj_mapping_k[0]; + dmsr->reg7.sw_dmsr_edge_k_1 = adj_mapping_k[1]; + + /* 0x00A0(reg8) */ + dmsr->reg8.sw_dmsr_edge_k_2 = adj_mapping_k[2]; + dmsr->reg8.sw_dmsr_edge_k_3 = adj_mapping_k[3]; + + /* 0x00A4(reg9) */ + dmsr->reg9.sw_dmsr_edge_k_4 = adj_mapping_k[4]; + dmsr->reg9.sw_dmsr_edge_k_5 = adj_mapping_k[5]; + + /* 0x00A8(reg10) */ + dmsr->reg10.sw_dmsr_edge_k_6 = adj_mapping_k[6]; + dmsr->reg10.sw_dmsr_dir_contrast_conf_f = contrast2conf_mapping_k; + } + /* 0x00AC(reg11) */ + dmsr->reg11.sw_dmsr_dir_contrast_conf_x0 = p_dmsr_param->dmsr_contrast_to_conf_map_x0; + dmsr->reg11.sw_dmsr_dir_contrast_conf_x1 = p_dmsr_param->dmsr_contrast_to_conf_map_x1; + + /* 0x00B0(reg12) */ + dmsr->reg12.sw_dmsr_dir_contrast_conf_y0 = p_dmsr_param->dmsr_contrast_to_conf_map_y0; + dmsr->reg12.sw_dmsr_dir_contrast_conf_y1 = p_dmsr_param->dmsr_contrast_to_conf_map_y1; + + /* 0x00B4(reg13) */ + dmsr->reg13.sw_dmsr_var_th = p_dmsr_param->dmsr_blk_flat_th; + + /* 0x00B8(reg14) */ + dmsr->reg14.sw_dmsr_diff_coring_th0 = p_dmsr_param->dmsr_diff_core_th0; + dmsr->reg14.sw_dmsr_diff_coring_th1 = p_dmsr_param->dmsr_diff_core_th1; + + /* 0x00BC(reg15) */ + dmsr->reg15.sw_dmsr_diff_coring_wgt0 = p_dmsr_param->dmsr_diff_core_wgt0; + dmsr->reg15.sw_dmsr_diff_coring_wgt1 = p_dmsr_param->dmsr_diff_core_wgt1; + dmsr->reg15.sw_dmsr_diff_coring_wgt2 = p_dmsr_param->dmsr_diff_core_wgt2; + { + RK_U16 diff_coring_y0 = p_dmsr_param->dmsr_diff_core_th0 * p_dmsr_param->dmsr_diff_core_wgt0; + RK_U16 diff_coring_y1 = ((p_dmsr_param->dmsr_diff_core_th1 - p_dmsr_param->dmsr_diff_core_th0) * p_dmsr_param->dmsr_diff_core_wgt1) + diff_coring_y0; + /* 0x00C0(reg16) */ + dmsr->reg16.sw_dmsr_diff_coring_y0 = diff_coring_y0; + dmsr->reg16.sw_dmsr_diff_coring_y1 = diff_coring_y1; + } + /* 0x00C4(reg17) */ + dmsr->reg17.sw_dmsr_wgt_pri_gain_1_odd = p_dmsr_param->dmsr_wgt_pri_gain_odd_1; + dmsr->reg17.sw_dmsr_wgt_pri_gain_1_even = p_dmsr_param->dmsr_wgt_pri_gain_even_1; + dmsr->reg17.sw_dmsr_wgt_pri_gain_2_odd = p_dmsr_param->dmsr_wgt_pri_gain_odd_2; + dmsr->reg17.sw_dmsr_wgt_pri_gain_2_even = p_dmsr_param->dmsr_wgt_pri_gain_even_2; + + /* 0x00C8(reg18) */ + dmsr->reg18.sw_dmsr_wgt_sec_gain_1 = p_dmsr_param->dmsr_wgt_sec_gain; + dmsr->reg18.sw_dmsr_wgt_sec_gain_2 = p_dmsr_param->dmsr_wgt_sec_gain * 2; + + /* 0x00CC(reg19) */ + dmsr->reg19.sw_dmsr_strength_pri = p_dmsr_param->dmsr_str_pri_y; + dmsr->reg19.sw_dmsr_strength_sec = p_dmsr_param->dmsr_str_sec_y; + dmsr->reg19.sw_dmsr_dump = p_dmsr_param->dmsr_dumping_y; +} + +void vdpp_set_default_zme_param(struct zme_params* param) +{ + param->zme_bypass_en = 1; + param->zme_dering_enable = 1; + param->zme_dering_sen_0 = 16; + param->zme_dering_sen_1 = 4; + param->zme_dering_blend_alpha = 16; + param->zme_dering_blend_beta = 13; + param->zme_tap8_coeff = g_zme_tap8_coeff; + param->zme_tap6_coeff = g_zme_tap6_coeff; +} + + +void set_zme_to_vdpp_reg(struct zme_params *zme_params, struct zme_reg *zme) +{ + /* 0x00D0(reg20), debug settings, skip */ + /* 3. set reg::zme */ + /* 3.1 set reg::zme::common */ + enum ZME_FMT zme_format_in = FMT_YCbCr420_888; + scl_info yrgb_scl_info = {0}; + scl_info cbcr_scl_info = {0}; + + yrgb_scl_info.act_width = zme_params->src_width; + yrgb_scl_info.act_height = zme_params->src_height; + yrgb_scl_info.dsp_width = zme_params->dst_width; + yrgb_scl_info.dsp_height = zme_params->dst_height; + yrgb_scl_info.xscl_mode = SCL_MPH; + yrgb_scl_info.yscl_mode = SCL_MPH; + yrgb_scl_info.dering_en = zme_params->zme_dering_enable; + calc_scl_factor(zme_params, &yrgb_scl_info, zme_params->zme_bypass_en); + + if (zme_format_in == FMT_YCbCr420_888) { + cbcr_scl_info.act_width = zme_params->src_width / 2; + cbcr_scl_info.act_height = zme_params->src_height / 2; + } else { + /* only support yuv420 as input */ + } + + if (zme_params->dst_fmt == VDPP_FMT_YUV444) { + if (!zme_params->yuv_out_diff) { + cbcr_scl_info.dsp_width = zme_params->dst_width; + cbcr_scl_info.dsp_height = zme_params->dst_height; + } else { + cbcr_scl_info.dsp_width = zme_params->dst_c_width; + cbcr_scl_info.dsp_height = zme_params->dst_c_height; + } + } else if (zme_params->dst_fmt == VDPP_FMT_YUV420) { + if (!zme_params->yuv_out_diff) { + cbcr_scl_info.dsp_width = zme_params->dst_width / 2; + cbcr_scl_info.dsp_height = zme_params->dst_height / 2; + } else { + cbcr_scl_info.dsp_width = zme_params->dst_c_width / 2; + cbcr_scl_info.dsp_height = zme_params->dst_c_height / 2; + } + } else { + /* not supported */ + } + cbcr_scl_info.xscl_mode = SCL_MPH; + cbcr_scl_info.yscl_mode = SCL_MPH; + cbcr_scl_info.dering_en = zme_params->zme_dering_enable; + calc_scl_factor(zme_params, &cbcr_scl_info, zme_params->zme_bypass_en); + + /* 0x0800(reg0) */ + zme->common.reg0.bypass_en = 0; + zme->common.reg0.align_en = 0; + zme->common.reg0.format_in = FMT_YCbCr420_888; + if (zme_params->dst_fmt == VDPP_FMT_YUV444) + zme->common.reg0.format_out = FMT_YCbCr444_888; + else + zme->common.reg0.format_out = FMT_YCbCr420_888; + zme->common.reg0.auto_gating_en = 1; + + /* 0x0804 ~ 0x0808(reg1 ~ reg2), skip */ + + /* 0x080C(reg3), not used */ + zme->common.reg3.vir_width = zme_params->src_width; + zme->common.reg3.vir_height = zme_params->src_height; + + /* 0x0810(reg4) */ + zme->common.reg4.yrgb_xsd_en = yrgb_scl_info.xsd_en; + zme->common.reg4.yrgb_xsu_en = yrgb_scl_info.xsu_en; + zme->common.reg4.yrgb_scl_mode = yrgb_scl_info.xscl_mode; + zme->common.reg4.yrgb_ysd_en = yrgb_scl_info.ysd_en; + zme->common.reg4.yrgb_ysu_en = yrgb_scl_info.ysu_en; + zme->common.reg4.yrgb_yscl_mode = yrgb_scl_info.yscl_mode; + zme->common.reg4.yrgb_dering_en = yrgb_scl_info.dering_en; + zme->common.reg4.yrgb_gt_en = yrgb_scl_info.ygt_en; + zme->common.reg4.yrgb_gt_mode = yrgb_scl_info.ygt_mode; + zme->common.reg4.yrgb_xgt_en = yrgb_scl_info.xgt_en; + zme->common.reg4.yrgb_xgt_mode = yrgb_scl_info.xgt_mode; + zme->common.reg4.yrgb_xsd_bypass = yrgb_scl_info.xsd_bypass; + zme->common.reg4.yrgb_ys_bypass = yrgb_scl_info.ys_bypass; + zme->common.reg4.yrgb_xsu_bypass = yrgb_scl_info.xsu_bypass; + + /* 0x0814(reg5) */ + zme->common.reg5.yrgb_src_width = yrgb_scl_info.act_width - 1; + zme->common.reg5.yrgb_src_height = yrgb_scl_info.act_height - 1; + + /* 0x0818(reg6) */ + zme->common.reg6.yrgb_dst_width = yrgb_scl_info.dsp_width - 1; + zme->common.reg6.yrgb_dst_height = yrgb_scl_info.dsp_height - 1; + + /* 0x081C(reg7) */ + zme->common.reg7.yrgb_dering_sen0 = zme_params->zme_dering_sen_0; + zme->common.reg7.yrgb_dering_sen1 = zme_params->zme_dering_sen_1; + zme->common.reg7.yrgb_dering_alpha = zme_params->zme_dering_blend_alpha; + zme->common.reg7.yrgb_dering_delta = zme_params->zme_dering_blend_beta; + + /* 0x0820(reg8) */ + zme->common.reg8.yrgb_xscl_factor = yrgb_scl_info.xscl_factor; + zme->common.reg8.yrgb_xscl_offset = yrgb_scl_info.xscl_offset; + + /* 0x0824(reg9) */ + zme->common.reg9.yrgb_yscl_factor = yrgb_scl_info.yscl_factor; + zme->common.reg9.yrgb_yscl_offset = yrgb_scl_info.yscl_offset; + + /* 0x0828 ~ 0x082C(reg10 ~ reg11), skip */ + + /* 0x0830(reg12) */ + zme->common.reg12.cbcr_xsd_en = cbcr_scl_info.xsd_en; + zme->common.reg12.cbcr_xsu_en = cbcr_scl_info.xsu_en; + zme->common.reg12.cbcr_scl_mode = cbcr_scl_info.xscl_mode; + zme->common.reg12.cbcr_ysd_en = cbcr_scl_info.ysd_en; + zme->common.reg12.cbcr_ysu_en = cbcr_scl_info.ysu_en; + zme->common.reg12.cbcr_yscl_mode = cbcr_scl_info.yscl_mode; + zme->common.reg12.cbcr_dering_en = cbcr_scl_info.dering_en; + zme->common.reg12.cbcr_gt_en = cbcr_scl_info.ygt_en; + zme->common.reg12.cbcr_gt_mode = cbcr_scl_info.ygt_mode; + zme->common.reg12.cbcr_xgt_en = cbcr_scl_info.xgt_en; + zme->common.reg12.cbcr_xgt_mode = cbcr_scl_info.xgt_mode; + zme->common.reg12.cbcr_xsd_bypass = cbcr_scl_info.xsd_bypass; + zme->common.reg12.cbcr_ys_bypass = cbcr_scl_info.ys_bypass; + zme->common.reg12.cbcr_xsu_bypass = cbcr_scl_info.xsu_bypass; + + /* 0x0834(reg13) */ + zme->common.reg13.cbcr_src_width = cbcr_scl_info.act_width - 1; + zme->common.reg13.cbcr_src_height = cbcr_scl_info.act_height - 1; + + /* 0x0838(reg14) */ + zme->common.reg14.cbcr_dst_width = cbcr_scl_info.dsp_width - 1; + zme->common.reg14.cbcr_dst_height = cbcr_scl_info.dsp_height - 1; + + /* 0x083C(reg15) */ + zme->common.reg15.cbcr_dering_sen0 = zme_params->zme_dering_sen_0; + zme->common.reg15.cbcr_dering_sen1 = zme_params->zme_dering_sen_1; + zme->common.reg15.cbcr_dering_alpha = zme_params->zme_dering_blend_alpha; + zme->common.reg15.cbcr_dering_delta = zme_params->zme_dering_blend_beta; + + /* 0x0840(reg16) */ + zme->common.reg16.cbcr_xscl_factor = cbcr_scl_info.xscl_factor; + zme->common.reg16.cbcr_xscl_offset = cbcr_scl_info.xscl_offset; + + /* 0x0844(reg17) */ + zme->common.reg17.cbcr_yscl_factor = cbcr_scl_info.yscl_factor; + zme->common.reg17.cbcr_yscl_offset = cbcr_scl_info.yscl_offset; + + /* 3.2 set reg::zme::coef */ + /* 0x0000(reg0) */ + VDPP_SET_ZME_COEF(0, 0, 0); + VDPP_SET_ZME_COEF(0, 0, 1); + + /* 0x0004(reg1) */ + VDPP_SET_ZME_COEF(1, 0, 2); + VDPP_SET_ZME_COEF(1, 0, 3); + + /* 0x0008(reg2) */ + VDPP_SET_ZME_COEF(2, 0, 4); + VDPP_SET_ZME_COEF(2, 0, 5); + + /* 0x000c(reg3) */ + VDPP_SET_ZME_COEF(3, 0, 6); + VDPP_SET_ZME_COEF(3, 0, 7); + + /* 0x0010(reg4) */ + VDPP_SET_ZME_COEF(4, 1, 0); + VDPP_SET_ZME_COEF(4, 1, 1); + + /* 0x0014(reg5) */ + VDPP_SET_ZME_COEF(5, 1, 2); + VDPP_SET_ZME_COEF(5, 1, 3); + + /* 0x0018(reg6) */ + VDPP_SET_ZME_COEF(6, 1, 4); + VDPP_SET_ZME_COEF(6, 1, 5); + + /* 0x001c(reg7) */ + VDPP_SET_ZME_COEF(7, 1, 6); + VDPP_SET_ZME_COEF(7, 1, 7); + + /* 0x0020(reg8) */ + VDPP_SET_ZME_COEF(8, 2, 0); + VDPP_SET_ZME_COEF(8, 2, 1); + + /* 0x0024(reg9) */ + VDPP_SET_ZME_COEF(9, 2, 2); + VDPP_SET_ZME_COEF(9, 2, 3); + + /* 0x0028(reg10) */ + VDPP_SET_ZME_COEF(10, 2, 4); + VDPP_SET_ZME_COEF(10, 2, 5); + + /* 0x002c(reg11) */ + VDPP_SET_ZME_COEF(11, 2, 6); + VDPP_SET_ZME_COEF(11, 2, 7); + + /* 0x0030(reg12) */ + VDPP_SET_ZME_COEF(12, 3, 0); + VDPP_SET_ZME_COEF(12, 3, 1); + + /* 0x0034(reg13) */ + VDPP_SET_ZME_COEF(13, 3, 2); + VDPP_SET_ZME_COEF(13, 3, 3); + + /* 0x0038(reg14) */ + VDPP_SET_ZME_COEF(14, 3, 4); + VDPP_SET_ZME_COEF(14, 3, 5); + + /* 0x003c(reg15) */ + VDPP_SET_ZME_COEF(15, 3, 6); + VDPP_SET_ZME_COEF(15, 3, 7); + + /* 0x0040(reg16) */ + VDPP_SET_ZME_COEF(16, 4, 0); + VDPP_SET_ZME_COEF(16, 4, 1); + + /* 0x0044(reg17) */ + VDPP_SET_ZME_COEF(17, 4, 2); + VDPP_SET_ZME_COEF(17, 4, 3); + + /* 0x0048(reg18) */ + VDPP_SET_ZME_COEF(18, 4, 4); + VDPP_SET_ZME_COEF(18, 4, 5); + + /* 0x004c(reg19) */ + VDPP_SET_ZME_COEF(19, 4, 6); + VDPP_SET_ZME_COEF(19, 4, 7); + + /* 0x0050(reg20) */ + VDPP_SET_ZME_COEF(20, 5, 0); + VDPP_SET_ZME_COEF(20, 5, 1); + + /* 0x0054(reg21) */ + VDPP_SET_ZME_COEF(21, 5, 2); + VDPP_SET_ZME_COEF(21, 5, 3); + + /* 0x0058(reg22) */ + VDPP_SET_ZME_COEF(22, 5, 4); + VDPP_SET_ZME_COEF(22, 5, 5); + + /* 0x005c(reg23) */ + VDPP_SET_ZME_COEF(23, 5, 6); + VDPP_SET_ZME_COEF(23, 5, 7); + + /* 0x0060(reg24) */ + VDPP_SET_ZME_COEF(24, 6, 0); + VDPP_SET_ZME_COEF(24, 6, 1); + + /* 0x0064(reg25) */ + VDPP_SET_ZME_COEF(25, 6, 2); + VDPP_SET_ZME_COEF(25, 6, 3); + + /* 0x0068(reg26) */ + VDPP_SET_ZME_COEF(26, 6, 4); + VDPP_SET_ZME_COEF(26, 6, 5); + + /* 0x006c(reg27) */ + VDPP_SET_ZME_COEF(27, 6, 6); + VDPP_SET_ZME_COEF(27, 6, 7); + + /* 0x0070(reg28) */ + VDPP_SET_ZME_COEF(28, 7, 0); + VDPP_SET_ZME_COEF(28, 7, 1); + + /* 0x0074(reg29) */ + VDPP_SET_ZME_COEF(29, 7, 2); + VDPP_SET_ZME_COEF(29, 7, 3); + + /* 0x0078(reg30) */ + VDPP_SET_ZME_COEF(30, 7, 4); + VDPP_SET_ZME_COEF(30, 7, 5); + + /* 0x007c(reg31) */ + VDPP_SET_ZME_COEF(31, 7, 6); + VDPP_SET_ZME_COEF(31, 7, 7); + + /* 0x0080(reg32) */ + VDPP_SET_ZME_COEF(32, 8, 0); + VDPP_SET_ZME_COEF(32, 8, 1); + + /* 0x0084(reg33) */ + VDPP_SET_ZME_COEF(33, 8, 2); + VDPP_SET_ZME_COEF(33, 8, 3); + + /* 0x0088(reg34) */ + VDPP_SET_ZME_COEF(34, 8, 4); + VDPP_SET_ZME_COEF(34, 8, 5); + + /* 0x008c(reg35) */ + VDPP_SET_ZME_COEF(35, 8, 6); + VDPP_SET_ZME_COEF(35, 8, 7); + + /* 0x0090(reg36) */ + VDPP_SET_ZME_COEF(36, 9, 0); + VDPP_SET_ZME_COEF(36, 9, 1); + + /* 0x0094(reg37) */ + VDPP_SET_ZME_COEF(37, 9, 2); + VDPP_SET_ZME_COEF(37, 9, 3); + + /* 0x0098(reg38) */ + VDPP_SET_ZME_COEF(38, 9, 4); + VDPP_SET_ZME_COEF(38, 9, 5); + + /* 0x009c(reg39) */ + VDPP_SET_ZME_COEF(39, 9, 6); + VDPP_SET_ZME_COEF(39, 9, 7); + + /* 0x00a0(reg40) */ + VDPP_SET_ZME_COEF(40, 10, 0); + VDPP_SET_ZME_COEF(40, 10, 1); + + /* 0x00a4(reg41) */ + VDPP_SET_ZME_COEF(41, 10, 2); + VDPP_SET_ZME_COEF(41, 10, 3); + + /* 0x00a8(reg42) */ + VDPP_SET_ZME_COEF(42, 10, 4); + VDPP_SET_ZME_COEF(42, 10, 5); + + /* 0x00ac(reg43) */ + VDPP_SET_ZME_COEF(43, 10, 6); + VDPP_SET_ZME_COEF(43, 10, 7); + + /* 0x00b0(reg44) */ + VDPP_SET_ZME_COEF(44, 11, 0); + VDPP_SET_ZME_COEF(44, 11, 1); + + /* 0x00b4(reg45) */ + VDPP_SET_ZME_COEF(45, 11, 2); + VDPP_SET_ZME_COEF(45, 11, 3); + + /* 0x00b8(reg46) */ + VDPP_SET_ZME_COEF(46, 11, 4); + VDPP_SET_ZME_COEF(46, 11, 5); + + /* 0x00bc(reg47) */ + VDPP_SET_ZME_COEF(47, 11, 6); + VDPP_SET_ZME_COEF(47, 11, 7); + + /* 0x00c0(reg48) */ + VDPP_SET_ZME_COEF(48, 12, 0); + VDPP_SET_ZME_COEF(48, 12, 1); + + /* 0x00c4(reg49) */ + VDPP_SET_ZME_COEF(49, 12, 2); + VDPP_SET_ZME_COEF(49, 12, 3); + + /* 0x00c8(reg50) */ + VDPP_SET_ZME_COEF(50, 12, 4); + VDPP_SET_ZME_COEF(50, 12, 5); + + /* 0x00cc(reg51) */ + VDPP_SET_ZME_COEF(51, 12, 6); + VDPP_SET_ZME_COEF(51, 12, 7); + + /* 0x00d0(reg52) */ + VDPP_SET_ZME_COEF(52, 13, 0); + VDPP_SET_ZME_COEF(52, 13, 1); + + /* 0x00d4(reg53) */ + VDPP_SET_ZME_COEF(53, 13, 2); + VDPP_SET_ZME_COEF(53, 13, 3); + + /* 0x00d8(reg54) */ + VDPP_SET_ZME_COEF(54, 13, 4); + VDPP_SET_ZME_COEF(54, 13, 5); + + /* 0x00dc(reg55) */ + VDPP_SET_ZME_COEF(55, 13, 6); + VDPP_SET_ZME_COEF(55, 13, 7); + + /* 0x00e0(reg56) */ + VDPP_SET_ZME_COEF(56, 14, 0); + VDPP_SET_ZME_COEF(56, 14, 1); + + /* 0x00e4(reg57) */ + VDPP_SET_ZME_COEF(57, 14, 2); + VDPP_SET_ZME_COEF(57, 14, 3); + + /* 0x00e8(reg58) */ + VDPP_SET_ZME_COEF(58, 14, 4); + VDPP_SET_ZME_COEF(58, 14, 5); + + /* 0x00ec(reg59) */ + VDPP_SET_ZME_COEF(59, 14, 6); + VDPP_SET_ZME_COEF(59, 14, 7); + + /* 0x00f0(reg60) */ + VDPP_SET_ZME_COEF(60, 15, 0); + VDPP_SET_ZME_COEF(60, 15, 1); + + /* 0x00f4(reg61) */ + VDPP_SET_ZME_COEF(61, 15, 2); + VDPP_SET_ZME_COEF(61, 15, 3); + + /* 0x00f8(reg62) */ + VDPP_SET_ZME_COEF(62, 15, 4); + VDPP_SET_ZME_COEF(62, 15, 5); + + /* 0x00fc(reg63) */ + VDPP_SET_ZME_COEF(63, 15, 6); + VDPP_SET_ZME_COEF(63, 15, 7); + + /* 0x0100(reg64) */ + VDPP_SET_ZME_COEF(64, 16, 0); + VDPP_SET_ZME_COEF(64, 16, 1); + + /* 0x0104(reg65) */ + VDPP_SET_ZME_COEF(65, 16, 2); + VDPP_SET_ZME_COEF(65, 16, 3); + + /* 0x0108(reg66) */ + VDPP_SET_ZME_COEF(66, 16, 4); + VDPP_SET_ZME_COEF(66, 16, 5); + + /* 0x010c(reg67) */ + VDPP_SET_ZME_COEF(67, 16, 6); + VDPP_SET_ZME_COEF(67, 16, 7); + +} diff --git a/mpp/vproc/vdpp/vdpp_common.h b/mpp/vproc/vdpp/vdpp_common.h new file mode 100644 index 00000000..b5295d3f --- /dev/null +++ b/mpp/vproc/vdpp/vdpp_common.h @@ -0,0 +1,1769 @@ +/* SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#ifndef __VDPP_COMMON_H__ +#define __VDPP_COMMON_H__ + +#include + +#include "rk_type.h" +#include "mpp_err.h" +#include "mpp_common.h" +#include "vdpp_api.h" + +/* marco define */ +#define VDPP_TILE_W_MAX (120) +#define VDPP_TILE_H_MAX (480) + +#define SCALE_FACTOR_DN_FIXPOINT_SHIFT (12) +#define SCALE_FACTOR_UP_FIXPOINT_SHIFT (16) +#define GET_SCALE_FACTOR_DN(src,dst) ((((src) - 1) << SCALE_FACTOR_DN_FIXPOINT_SHIFT) / ((dst) - 1)) +#define GET_SCALE_FACTOR_UP(src,dst) ((((src) - 1) << SCALE_FACTOR_UP_FIXPOINT_SHIFT) / ((dst) - 1)) + +enum ZME_FMT { + FMT_YCbCr420_888 = 4, + FMT_YCbCr444_888 = 6, +}; + +enum { + SCL_NEI = 0, + SCL_BIL = 1, + SCL_BIC = 2, + SCL_MPH = 3, +}; + +struct dmsr_params { + bool dmsr_enable; + RK_U32 dmsr_str_pri_y; + RK_U32 dmsr_str_sec_y; + RK_U32 dmsr_dumping_y; + RK_U32 dmsr_wgt_pri_gain_even_1; + RK_U32 dmsr_wgt_pri_gain_even_2; + RK_U32 dmsr_wgt_pri_gain_odd_1; + RK_U32 dmsr_wgt_pri_gain_odd_2; + RK_U32 dmsr_wgt_sec_gain; + RK_U32 dmsr_blk_flat_th; + RK_U32 dmsr_contrast_to_conf_map_x0; + RK_U32 dmsr_contrast_to_conf_map_x1; + RK_U32 dmsr_contrast_to_conf_map_y0; + RK_U32 dmsr_contrast_to_conf_map_y1; + RK_U32 dmsr_diff_core_th0; + RK_U32 dmsr_diff_core_th1; + RK_U32 dmsr_diff_core_wgt0; + RK_U32 dmsr_diff_core_wgt1; + RK_U32 dmsr_diff_core_wgt2; + RK_U32 dmsr_edge_th_low_arr[7]; + RK_U32 dmsr_edge_th_high_arr[7]; +}; + +struct dmsr_reg { + + struct { + RK_U32 sw_dmsr_edge_low_thre_0 : 16; + RK_U32 sw_dmsr_edge_high_thre_0 : 16; + } reg0; /* 0x0080 */ + + struct { + RK_U32 sw_dmsr_edge_low_thre_1 : 16; + RK_U32 sw_dmsr_edge_high_thre_1 : 16; + } reg1; /* 0x0084 */ + + struct { + RK_U32 sw_dmsr_edge_low_thre_2 : 16; + RK_U32 sw_dmsr_edge_high_thre_2 : 16; + } reg2; /* 0x0088 */ + + struct { + RK_U32 sw_dmsr_edge_low_thre_3 : 16; + RK_U32 sw_dmsr_edge_high_thre_3 : 16; + } reg3; /* 0x008C */ + + struct { + RK_U32 sw_dmsr_edge_low_thre_4 : 16; + RK_U32 sw_dmsr_edge_high_thre_4 : 16; + } reg4; /* 0x0090 */ + + struct { + RK_U32 sw_dmsr_edge_low_thre_5 : 16; + RK_U32 sw_dmsr_edge_high_thre_5 : 16; + } reg5; /* 0x0094 */ + + struct { + RK_U32 sw_dmsr_edge_low_thre_6 : 16; + RK_U32 sw_dmsr_edge_high_thre_6 : 16; + } reg6; /* 0x0098 */ + + struct { + RK_U32 sw_dmsr_edge_k_0 : 16; + RK_U32 sw_dmsr_edge_k_1 : 16; + } reg7; /* 0x009C */ + + struct { + RK_U32 sw_dmsr_edge_k_2 : 16; + RK_U32 sw_dmsr_edge_k_3 : 16; + } reg8; /* 0x00A0 */ + + struct { + RK_U32 sw_dmsr_edge_k_4 : 16; + RK_U32 sw_dmsr_edge_k_5 : 16; + } reg9; /* 0x00A4 */ + + struct { + RK_U32 sw_dmsr_edge_k_6 : 16; + RK_U32 sw_dmsr_dir_contrast_conf_f : 16; + } reg10; /* 0x00A8 */ + + struct { + RK_U32 sw_dmsr_dir_contrast_conf_x0 : 16; + RK_U32 sw_dmsr_dir_contrast_conf_x1 : 16; + } reg11; /* 0x00AC */ + + struct { + RK_U32 sw_dmsr_dir_contrast_conf_y0 : 16; + RK_U32 sw_dmsr_dir_contrast_conf_y1 : 16; + } reg12; /* 0x00B0 */ + + struct { + RK_U32 sw_dmsr_var_th : 16; + } reg13; /* 0x00B4 */ + + struct { + RK_U32 sw_dmsr_diff_coring_th0 : 8; + RK_U32 sw_dmsr_diff_coring_th1 : 8; + } reg14; /* 0x00B8 */ + + struct { + RK_U32 sw_dmsr_diff_coring_wgt0 : 6; + RK_U32 sw_reserved_1 : 2; + RK_U32 sw_dmsr_diff_coring_wgt1 : 6; + RK_U32 sw_reserved_2 : 2; + RK_U32 sw_dmsr_diff_coring_wgt2 : 6; + } reg15; /* 0x00BC */ + + struct { + RK_U32 sw_dmsr_diff_coring_y0 : 14; + RK_U32 sw_reserved_1 : 2; + RK_U32 sw_dmsr_diff_coring_y1 : 14; + RK_U32 sw_reserved_2 : 2; + } reg16; /* 0x00C0 */ + + struct { + RK_U32 sw_dmsr_wgt_pri_gain_1_odd : 6; + RK_U32 sw_reserved_1 : 2; + RK_U32 sw_dmsr_wgt_pri_gain_1_even : 6; + RK_U32 sw_reserved_2 : 2; + RK_U32 sw_dmsr_wgt_pri_gain_2_odd : 6; + RK_U32 sw_reserved_3 : 2; + RK_U32 sw_dmsr_wgt_pri_gain_2_even : 6; + } reg17; /* 0x00C4 */ + + struct { + RK_U32 sw_dmsr_wgt_sec_gain_1 : 6; + RK_U32 sw_reserved_1 : 2; + RK_U32 sw_dmsr_wgt_sec_gain_2 : 6; + } reg18; /* 0x00C8 */ + + struct { + RK_U32 sw_dmsr_strength_pri : 5; + RK_U32 sw_reserved_1 : 3; + RK_U32 sw_dmsr_strength_sec : 5; + RK_U32 sw_reserved_2 : 3; + RK_U32 sw_dmsr_dump : 4; + } reg19; /* 0x00CC */ + + struct { + RK_U32 sw_dmsr_obv_point_h : 12; + RK_U32 sw_dmsr_obv_point_v : 12; + RK_U32 sw_dmsr_obv_enable : 1; + RK_U32 sw_dmsr_obv_mode : 1; + } reg20; /* 0x00D0 */ + + RK_U32 reg_dmsr_21_23[3]; +}; /* offset: 0x1080 */ + + +typedef struct { + RK_U16 act_width; + RK_U16 dsp_width; + + RK_U16 act_height; + RK_U16 dsp_height; + + RK_U8 dering_en; + + RK_U8 xsd_en; + RK_U8 xsu_en; + RK_U8 xsd_bypass; + RK_U8 xsu_bypass; + RK_U8 xscl_mode; + RK_U16 xscl_factor; + RK_U8 xscl_offset; + + RK_U8 ysd_en; + RK_U8 ysu_en; + RK_U8 ys_bypass; + RK_U8 yscl_mode; + RK_U16 yscl_factor; + RK_U8 yscl_offset; + + RK_U8 xavg_en; + RK_U8 xgt_en; + RK_U8 xgt_mode; + + RK_U8 yavg_en; + RK_U8 ygt_en; + RK_U8 ygt_mode; + + RK_S16 (*xscl_zme_coe)[8]; + RK_S16 (*yscl_zme_coe)[8]; +} scl_info; + +typedef struct FdTransInfo_t { + RK_U32 reg_idx; + RK_U32 offset; +} RegOffsetInfo; + +struct vdpp_addr { + RK_U32 y; + RK_U32 cbcr; + RK_U32 cbcr_offset; +}; + +struct zme_params { + RK_U32 zme_bypass_en; + RK_U32 zme_dering_enable; + RK_U32 zme_dering_sen_0; + RK_U32 zme_dering_sen_1; + RK_U32 zme_dering_blend_alpha; + RK_U32 zme_dering_blend_beta; + RK_S16 (*zme_tap8_coeff)[17][8]; + RK_S16 (*zme_tap6_coeff)[17][8]; + + /* for scl_info */ + RK_U32 src_width; + RK_U32 src_height; + RK_U32 dst_width; + RK_U32 dst_height; + RK_U32 dst_fmt; + /* 3576 feature */ + RK_U32 yuv_out_diff; + RK_U32 dst_c_width; + RK_U32 dst_c_height; +}; + + +struct zme_reg { + struct { + struct { + RK_U32 yrgb_hor_coe0_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe0_1 : 10; + } reg0; /* 0x0000 */ + struct { + RK_U32 yrgb_hor_coe0_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe0_3 : 10; + } reg1; /* 0x0004 */ + struct { + RK_U32 yrgb_hor_coe0_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe0_5 : 10; + } reg2; /* 0x0008 */ + struct { + RK_U32 yrgb_hor_coe0_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe0_7 : 10; + } reg3; /* 0x000c */ + struct { + RK_U32 yrgb_hor_coe1_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe1_1 : 10; + } reg4; /* 0x0010 */ + struct { + RK_U32 yrgb_hor_coe1_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe1_3 : 10; + } reg5; /* 0x0014 */ + struct { + RK_U32 yrgb_hor_coe1_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe1_5 : 10; + } reg6; /* 0x0018 */ + struct { + RK_U32 yrgb_hor_coe1_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe1_7 : 10; + } reg7; /* 0x001c */ + struct { + RK_U32 yrgb_hor_coe2_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe2_1 : 10; + } reg8; /* 0x0020 */ + struct { + RK_U32 yrgb_hor_coe2_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe2_3 : 10; + } reg9; /* 0x0024 */ + struct { + RK_U32 yrgb_hor_coe2_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe2_5 : 10; + } reg10; /* 0x0028 */ + struct { + RK_U32 yrgb_hor_coe2_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe2_7 : 10; + } reg11; /* 0x002c */ + struct { + RK_U32 yrgb_hor_coe3_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe3_1 : 10; + } reg12; /* 0x0030 */ + struct { + RK_U32 yrgb_hor_coe3_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe3_3 : 10; + } reg13; /* 0x0034 */ + struct { + RK_U32 yrgb_hor_coe3_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe3_5 : 10; + } reg14; /* 0x0038 */ + struct { + RK_U32 yrgb_hor_coe3_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe3_7 : 10; + } reg15; /* 0x003c */ + struct { + RK_U32 yrgb_hor_coe4_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe4_1 : 10; + } reg16; /* 0x0040 */ + struct { + RK_U32 yrgb_hor_coe4_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe4_3 : 10; + } reg17; /* 0x0044 */ + struct { + RK_U32 yrgb_hor_coe4_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe4_5 : 10; + } reg18; /* 0x0048 */ + struct { + RK_U32 yrgb_hor_coe4_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe4_7 : 10; + } reg19; /* 0x004c */ + struct { + RK_U32 yrgb_hor_coe5_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe5_1 : 10; + } reg20; /* 0x0050 */ + struct { + RK_U32 yrgb_hor_coe5_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe5_3 : 10; + } reg21; /* 0x0054 */ + struct { + RK_U32 yrgb_hor_coe5_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe5_5 : 10; + } reg22; /* 0x0058 */ + struct { + RK_U32 yrgb_hor_coe5_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe5_7 : 10; + } reg23; /* 0x005c */ + struct { + RK_U32 yrgb_hor_coe6_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe6_1 : 10; + } reg24; /* 0x0060 */ + struct { + RK_U32 yrgb_hor_coe6_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe6_3 : 10; + } reg25; /* 0x0064 */ + struct { + RK_U32 yrgb_hor_coe6_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe6_5 : 10; + } reg26; /* 0x0068 */ + struct { + RK_U32 yrgb_hor_coe6_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe6_7 : 10; + } reg27; /* 0x006c */ + struct { + RK_U32 yrgb_hor_coe7_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe7_1 : 10; + } reg28; /* 0x0070 */ + struct { + RK_U32 yrgb_hor_coe7_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe7_3 : 10; + } reg29; /* 0x0074 */ + struct { + RK_U32 yrgb_hor_coe7_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe7_5 : 10; + } reg30; /* 0x0078 */ + struct { + RK_U32 yrgb_hor_coe7_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe7_7 : 10; + } reg31; /* 0x007c */ + struct { + RK_U32 yrgb_hor_coe8_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe8_1 : 10; + } reg32; /* 0x0080 */ + struct { + RK_U32 yrgb_hor_coe8_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe8_3 : 10; + } reg33; /* 0x0084 */ + struct { + RK_U32 yrgb_hor_coe8_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe8_5 : 10; + } reg34; /* 0x0088 */ + struct { + RK_U32 yrgb_hor_coe8_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe8_7 : 10; + } reg35; /* 0x008c */ + struct { + RK_U32 yrgb_hor_coe9_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe9_1 : 10; + } reg36; /* 0x0090 */ + struct { + RK_U32 yrgb_hor_coe9_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe9_3 : 10; + } reg37; /* 0x0094 */ + struct { + RK_U32 yrgb_hor_coe9_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe9_5 : 10; + } reg38; /* 0x0098 */ + struct { + RK_U32 yrgb_hor_coe9_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe9_7 : 10; + } reg39; /* 0x009c */ + struct { + RK_U32 yrgb_hor_coe10_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe10_1 : 10; + } reg40; /* 0x00a0 */ + struct { + RK_U32 yrgb_hor_coe10_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe10_3 : 10; + } reg41; /* 0x00a4 */ + struct { + RK_U32 yrgb_hor_coe10_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe10_5 : 10; + } reg42; /* 0x00a8 */ + struct { + RK_U32 yrgb_hor_coe10_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe10_7 : 10; + } reg43; /* 0x00ac */ + struct { + RK_U32 yrgb_hor_coe11_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe11_1 : 10; + } reg44; /* 0x00b0 */ + struct { + RK_U32 yrgb_hor_coe11_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe11_3 : 10; + } reg45; /* 0x00b4 */ + struct { + RK_U32 yrgb_hor_coe11_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe11_5 : 10; + } reg46; /* 0x00b8 */ + struct { + RK_U32 yrgb_hor_coe11_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe11_7 : 10; + } reg47; /* 0x00bc */ + struct { + RK_U32 yrgb_hor_coe12_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe12_1 : 10; + } reg48; /* 0x00c0 */ + struct { + RK_U32 yrgb_hor_coe12_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe12_3 : 10; + } reg49; /* 0x00c4 */ + struct { + RK_U32 yrgb_hor_coe12_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe12_5 : 10; + } reg50; /* 0x00c8 */ + struct { + RK_U32 yrgb_hor_coe12_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe12_7 : 10; + } reg51; /* 0x00cc */ + struct { + RK_U32 yrgb_hor_coe13_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe13_1 : 10; + } reg52; /* 0x00d0 */ + struct { + RK_U32 yrgb_hor_coe13_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe13_3 : 10; + } reg53; /* 0x00d4 */ + struct { + RK_U32 yrgb_hor_coe13_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe13_5 : 10; + } reg54; /* 0x00d8 */ + struct { + RK_U32 yrgb_hor_coe13_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe13_7 : 10; + } reg55; /* 0x00dc */ + struct { + RK_U32 yrgb_hor_coe14_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe14_1 : 10; + } reg56; /* 0x00e0 */ + struct { + RK_U32 yrgb_hor_coe14_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe14_3 : 10; + } reg57; /* 0x00e4 */ + struct { + RK_U32 yrgb_hor_coe14_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe14_5 : 10; + } reg58; /* 0x00e8 */ + struct { + RK_U32 yrgb_hor_coe14_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe14_7 : 10; + } reg59; /* 0x00ec */ + struct { + RK_U32 yrgb_hor_coe15_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe15_1 : 10; + } reg60; /* 0x00f0 */ + struct { + RK_U32 yrgb_hor_coe15_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe15_3 : 10; + } reg61; /* 0x00f4 */ + struct { + RK_U32 yrgb_hor_coe15_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe15_5 : 10; + } reg62; /* 0x00f8 */ + struct { + RK_U32 yrgb_hor_coe15_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe15_7 : 10; + } reg63; /* 0x00fc */ + struct { + RK_U32 yrgb_hor_coe16_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe16_1 : 10; + } reg64; /* 0x0100 */ + struct { + RK_U32 yrgb_hor_coe16_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe16_3 : 10; + } reg65; /* 0x0104 */ + struct { + RK_U32 yrgb_hor_coe16_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe16_5 : 10; + } reg66; /* 0x0108 */ + struct { + RK_U32 yrgb_hor_coe16_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_hor_coe16_7 : 10; + } reg67; /* 0x010c */ + + } yrgb_hor_coe; + + struct { + struct { + RK_U32 yrgb_ver_coe0_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe0_1 : 10; + } reg0; /* 0x0200 */ + struct { + RK_U32 yrgb_ver_coe0_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe0_3 : 10; + } reg1; /* 0x0204 */ + struct { + RK_U32 yrgb_ver_coe0_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe0_5 : 10; + } reg2; /* 0x0208 */ + struct { + RK_U32 yrgb_ver_coe0_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe0_7 : 10; + } reg3; /* 0x020c */ + struct { + RK_U32 yrgb_ver_coe1_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe1_1 : 10; + } reg4; /* 0x0210 */ + struct { + RK_U32 yrgb_ver_coe1_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe1_3 : 10; + } reg5; /* 0x0214 */ + struct { + RK_U32 yrgb_ver_coe1_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe1_5 : 10; + } reg6; /* 0x0218 */ + struct { + RK_U32 yrgb_ver_coe1_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe1_7 : 10; + } reg7; /* 0x021c */ + struct { + RK_U32 yrgb_ver_coe2_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe2_1 : 10; + } reg8; /* 0x0220 */ + struct { + RK_U32 yrgb_ver_coe2_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe2_3 : 10; + } reg9; /* 0x0224 */ + struct { + RK_U32 yrgb_ver_coe2_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe2_5 : 10; + } reg10; /* 0x0228 */ + struct { + RK_U32 yrgb_ver_coe2_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe2_7 : 10; + } reg11; /* 0x022c */ + struct { + RK_U32 yrgb_ver_coe3_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe3_1 : 10; + } reg12; /* 0x0230 */ + struct { + RK_U32 yrgb_ver_coe3_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe3_3 : 10; + } reg13; /* 0x0234 */ + struct { + RK_U32 yrgb_ver_coe3_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe3_5 : 10; + } reg14; /* 0x0238 */ + struct { + RK_U32 yrgb_ver_coe3_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe3_7 : 10; + } reg15; /* 0x023c */ + struct { + RK_U32 yrgb_ver_coe4_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe4_1 : 10; + } reg16; /* 0x0240 */ + struct { + RK_U32 yrgb_ver_coe4_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe4_3 : 10; + } reg17; /* 0x0244 */ + struct { + RK_U32 yrgb_ver_coe4_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe4_5 : 10; + } reg18; /* 0x0248 */ + struct { + RK_U32 yrgb_ver_coe4_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe4_7 : 10; + } reg19; /* 0x024c */ + struct { + RK_U32 yrgb_ver_coe5_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe5_1 : 10; + } reg20; /* 0x0250 */ + struct { + RK_U32 yrgb_ver_coe5_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe5_3 : 10; + } reg21; /* 0x0254 */ + struct { + RK_U32 yrgb_ver_coe5_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe5_5 : 10; + } reg22; /* 0x0258 */ + struct { + RK_U32 yrgb_ver_coe5_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe5_7 : 10; + } reg23; /* 0x025c */ + struct { + RK_U32 yrgb_ver_coe6_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe6_1 : 10; + } reg24; /* 0x0260 */ + struct { + RK_U32 yrgb_ver_coe6_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe6_3 : 10; + } reg25; /* 0x0264 */ + struct { + RK_U32 yrgb_ver_coe6_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe6_5 : 10; + } reg26; /* 0x0268 */ + struct { + RK_U32 yrgb_ver_coe6_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe6_7 : 10; + } reg27; /* 0x026c */ + struct { + RK_U32 yrgb_ver_coe7_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe7_1 : 10; + } reg28; /* 0x0270 */ + struct { + RK_U32 yrgb_ver_coe7_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe7_3 : 10; + } reg29; /* 0x0274 */ + struct { + RK_U32 yrgb_ver_coe7_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe7_5 : 10; + } reg30; /* 0x0278 */ + struct { + RK_U32 yrgb_ver_coe7_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe7_7 : 10; + } reg31; /* 0x027c */ + struct { + RK_U32 yrgb_ver_coe8_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe8_1 : 10; + } reg32; /* 0x0280 */ + struct { + RK_U32 yrgb_ver_coe8_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe8_3 : 10; + } reg33; /* 0x0284 */ + struct { + RK_U32 yrgb_ver_coe8_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe8_5 : 10; + } reg34; /* 0x0288 */ + struct { + RK_U32 yrgb_ver_coe8_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe8_7 : 10; + } reg35; /* 0x028c */ + struct { + RK_U32 yrgb_ver_coe9_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe9_1 : 10; + } reg36; /* 0x0290 */ + struct { + RK_U32 yrgb_ver_coe9_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe9_3 : 10; + } reg37; /* 0x0294 */ + struct { + RK_U32 yrgb_ver_coe9_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe9_5 : 10; + } reg38; /* 0x0298 */ + struct { + RK_U32 yrgb_ver_coe9_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe9_7 : 10; + } reg39; /* 0x029c */ + struct { + RK_U32 yrgb_ver_coe10_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe10_1 : 10; + } reg40; /* 0x02a0 */ + struct { + RK_U32 yrgb_ver_coe10_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe10_3 : 10; + } reg41; /* 0x02a4 */ + struct { + RK_U32 yrgb_ver_coe10_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe10_5 : 10; + } reg42; /* 0x02a8 */ + struct { + RK_U32 yrgb_ver_coe10_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe10_7 : 10; + } reg43; /* 0x02ac */ + struct { + RK_U32 yrgb_ver_coe11_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe11_1 : 10; + } reg44; /* 0x02b0 */ + struct { + RK_U32 yrgb_ver_coe11_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe11_3 : 10; + } reg45; /* 0x02b4 */ + struct { + RK_U32 yrgb_ver_coe11_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe11_5 : 10; + } reg46; /* 0x02b8 */ + struct { + RK_U32 yrgb_ver_coe11_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe11_7 : 10; + } reg47; /* 0x02bc */ + struct { + RK_U32 yrgb_ver_coe12_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe12_1 : 10; + } reg48; /* 0x02c0 */ + struct { + RK_U32 yrgb_ver_coe12_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe12_3 : 10; + } reg49; /* 0x02c4 */ + struct { + RK_U32 yrgb_ver_coe12_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe12_5 : 10; + } reg50; /* 0x02c8 */ + struct { + RK_U32 yrgb_ver_coe12_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe12_7 : 10; + } reg51; /* 0x02cc */ + struct { + RK_U32 yrgb_ver_coe13_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe13_1 : 10; + } reg52; /* 0x02d0 */ + struct { + RK_U32 yrgb_ver_coe13_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe13_3 : 10; + } reg53; /* 0x02d4 */ + struct { + RK_U32 yrgb_ver_coe13_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe13_5 : 10; + } reg54; /* 0x02d8 */ + struct { + RK_U32 yrgb_ver_coe13_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe13_7 : 10; + } reg55; /* 0x02dc */ + struct { + RK_U32 yrgb_ver_coe14_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe14_1 : 10; + } reg56; /* 0x02e0 */ + struct { + RK_U32 yrgb_ver_coe14_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe14_3 : 10; + } reg57; /* 0x02e4 */ + struct { + RK_U32 yrgb_ver_coe14_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe14_5 : 10; + } reg58; /* 0x02e8 */ + struct { + RK_U32 yrgb_ver_coe14_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe14_7 : 10; + } reg59; /* 0x02ec */ + struct { + RK_U32 yrgb_ver_coe15_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe15_1 : 10; + } reg60; /* 0x02f0 */ + struct { + RK_U32 yrgb_ver_coe15_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe15_3 : 10; + } reg61; /* 0x02f4 */ + struct { + RK_U32 yrgb_ver_coe15_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe15_5 : 10; + } reg62; /* 0x02f8 */ + struct { + RK_U32 yrgb_ver_coe15_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe15_7 : 10; + } reg63; /* 0x02fc */ + struct { + RK_U32 yrgb_ver_coe16_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe16_1 : 10; + } reg64; /* 0x0300 */ + struct { + RK_U32 yrgb_ver_coe16_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe16_3 : 10; + } reg65; /* 0x0304 */ + struct { + RK_U32 yrgb_ver_coe16_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe16_5 : 10; + } reg66; /* 0x0308 */ + struct { + RK_U32 yrgb_ver_coe16_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 yrgb_ver_coe16_7 : 10; + } reg67; /* 0x030c */ + + } yrgb_ver_coe; + + struct { + struct { + RK_U32 cbcr_hor_coe0_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe0_1 : 10; + } reg0; /* 0x0400 */ + struct { + RK_U32 cbcr_hor_coe0_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe0_3 : 10; + } reg1; /* 0x0404 */ + struct { + RK_U32 cbcr_hor_coe0_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe0_5 : 10; + } reg2; /* 0x0408 */ + struct { + RK_U32 cbcr_hor_coe0_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe0_7 : 10; + } reg3; /* 0x040c */ + struct { + RK_U32 cbcr_hor_coe1_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe1_1 : 10; + } reg4; /* 0x0410 */ + struct { + RK_U32 cbcr_hor_coe1_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe1_3 : 10; + } reg5; /* 0x0414 */ + struct { + RK_U32 cbcr_hor_coe1_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe1_5 : 10; + } reg6; /* 0x0418 */ + struct { + RK_U32 cbcr_hor_coe1_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe1_7 : 10; + } reg7; /* 0x041c */ + struct { + RK_U32 cbcr_hor_coe2_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe2_1 : 10; + } reg8; /* 0x0420 */ + struct { + RK_U32 cbcr_hor_coe2_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe2_3 : 10; + } reg9; /* 0x0424 */ + struct { + RK_U32 cbcr_hor_coe2_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe2_5 : 10; + } reg10; /* 0x0428 */ + struct { + RK_U32 cbcr_hor_coe2_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe2_7 : 10; + } reg11; /* 0x042c */ + struct { + RK_U32 cbcr_hor_coe3_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe3_1 : 10; + } reg12; /* 0x0430 */ + struct { + RK_U32 cbcr_hor_coe3_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe3_3 : 10; + } reg13; /* 0x0434 */ + struct { + RK_U32 cbcr_hor_coe3_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe3_5 : 10; + } reg14; /* 0x0438 */ + struct { + RK_U32 cbcr_hor_coe3_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe3_7 : 10; + } reg15; /* 0x043c */ + struct { + RK_U32 cbcr_hor_coe4_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe4_1 : 10; + } reg16; /* 0x0440 */ + struct { + RK_U32 cbcr_hor_coe4_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe4_3 : 10; + } reg17; /* 0x0444 */ + struct { + RK_U32 cbcr_hor_coe4_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe4_5 : 10; + } reg18; /* 0x0448 */ + struct { + RK_U32 cbcr_hor_coe4_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe4_7 : 10; + } reg19; /* 0x044c */ + struct { + RK_U32 cbcr_hor_coe5_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe5_1 : 10; + } reg20; /* 0x0450 */ + struct { + RK_U32 cbcr_hor_coe5_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe5_3 : 10; + } reg21; /* 0x0454 */ + struct { + RK_U32 cbcr_hor_coe5_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe5_5 : 10; + } reg22; /* 0x0458 */ + struct { + RK_U32 cbcr_hor_coe5_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe5_7 : 10; + } reg23; /* 0x045c */ + struct { + RK_U32 cbcr_hor_coe6_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe6_1 : 10; + } reg24; /* 0x0460 */ + struct { + RK_U32 cbcr_hor_coe6_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe6_3 : 10; + } reg25; /* 0x0464 */ + struct { + RK_U32 cbcr_hor_coe6_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe6_5 : 10; + } reg26; /* 0x0468 */ + struct { + RK_U32 cbcr_hor_coe6_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe6_7 : 10; + } reg27; /* 0x046c */ + struct { + RK_U32 cbcr_hor_coe7_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe7_1 : 10; + } reg28; /* 0x0470 */ + struct { + RK_U32 cbcr_hor_coe7_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe7_3 : 10; + } reg29; /* 0x0474 */ + struct { + RK_U32 cbcr_hor_coe7_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe7_5 : 10; + } reg30; /* 0x0478 */ + struct { + RK_U32 cbcr_hor_coe7_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe7_7 : 10; + } reg31; /* 0x047c */ + struct { + RK_U32 cbcr_hor_coe8_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe8_1 : 10; + } reg32; /* 0x0480 */ + struct { + RK_U32 cbcr_hor_coe8_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe8_3 : 10; + } reg33; /* 0x0484 */ + struct { + RK_U32 cbcr_hor_coe8_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe8_5 : 10; + } reg34; /* 0x0488 */ + struct { + RK_U32 cbcr_hor_coe8_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe8_7 : 10; + } reg35; /* 0x048c */ + struct { + RK_U32 cbcr_hor_coe9_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe9_1 : 10; + } reg36; /* 0x0490 */ + struct { + RK_U32 cbcr_hor_coe9_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe9_3 : 10; + } reg37; /* 0x0494 */ + struct { + RK_U32 cbcr_hor_coe9_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe9_5 : 10; + } reg38; /* 0x0498 */ + struct { + RK_U32 cbcr_hor_coe9_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe9_7 : 10; + } reg39; /* 0x049c */ + struct { + RK_U32 cbcr_hor_coe10_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe10_1 : 10; + } reg40; /* 0x04a0 */ + struct { + RK_U32 cbcr_hor_coe10_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe10_3 : 10; + } reg41; /* 0x04a4 */ + struct { + RK_U32 cbcr_hor_coe10_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe10_5 : 10; + } reg42; /* 0x04a8 */ + struct { + RK_U32 cbcr_hor_coe10_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe10_7 : 10; + } reg43; /* 0x04ac */ + struct { + RK_U32 cbcr_hor_coe11_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe11_1 : 10; + } reg44; /* 0x04b0 */ + struct { + RK_U32 cbcr_hor_coe11_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe11_3 : 10; + } reg45; /* 0x04b4 */ + struct { + RK_U32 cbcr_hor_coe11_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe11_5 : 10; + } reg46; /* 0x04b8 */ + struct { + RK_U32 cbcr_hor_coe11_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe11_7 : 10; + } reg47; /* 0x04bc */ + struct { + RK_U32 cbcr_hor_coe12_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe12_1 : 10; + } reg48; /* 0x04c0 */ + struct { + RK_U32 cbcr_hor_coe12_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe12_3 : 10; + } reg49; /* 0x04c4 */ + struct { + RK_U32 cbcr_hor_coe12_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe12_5 : 10; + } reg50; /* 0x04c8 */ + struct { + RK_U32 cbcr_hor_coe12_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe12_7 : 10; + } reg51; /* 0x04cc */ + struct { + RK_U32 cbcr_hor_coe13_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe13_1 : 10; + } reg52; /* 0x04d0 */ + struct { + RK_U32 cbcr_hor_coe13_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe13_3 : 10; + } reg53; /* 0x04d4 */ + struct { + RK_U32 cbcr_hor_coe13_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe13_5 : 10; + } reg54; /* 0x04d8 */ + struct { + RK_U32 cbcr_hor_coe13_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe13_7 : 10; + } reg55; /* 0x04dc */ + struct { + RK_U32 cbcr_hor_coe14_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe14_1 : 10; + } reg56; /* 0x04e0 */ + struct { + RK_U32 cbcr_hor_coe14_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe14_3 : 10; + } reg57; /* 0x04e4 */ + struct { + RK_U32 cbcr_hor_coe14_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe14_5 : 10; + } reg58; /* 0x04e8 */ + struct { + RK_U32 cbcr_hor_coe14_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe14_7 : 10; + } reg59; /* 0x04ec */ + struct { + RK_U32 cbcr_hor_coe15_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe15_1 : 10; + } reg60; /* 0x04f0 */ + struct { + RK_U32 cbcr_hor_coe15_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe15_3 : 10; + } reg61; /* 0x04f4 */ + struct { + RK_U32 cbcr_hor_coe15_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe15_5 : 10; + } reg62; /* 0x04f8 */ + struct { + RK_U32 cbcr_hor_coe15_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe15_7 : 10; + } reg63; /* 0x04fc */ + struct { + RK_U32 cbcr_hor_coe16_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe16_1 : 10; + } reg64; /* 0x0500 */ + struct { + RK_U32 cbcr_hor_coe16_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe16_3 : 10; + } reg65; /* 0x0504 */ + struct { + RK_U32 cbcr_hor_coe16_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe16_5 : 10; + } reg66; /* 0x0508 */ + struct { + RK_U32 cbcr_hor_coe16_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_hor_coe16_7 : 10; + } reg67; /* 0x050c */ + + } cbcr_hor_coe; + + struct { + struct { + RK_U32 cbcr_ver_coe0_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe0_1 : 10; + } reg0; /* 0x0600 */ + struct { + RK_U32 cbcr_ver_coe0_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe0_3 : 10; + } reg1; /* 0x0604 */ + struct { + RK_U32 cbcr_ver_coe0_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe0_5 : 10; + } reg2; /* 0x0608 */ + struct { + RK_U32 cbcr_ver_coe0_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe0_7 : 10; + } reg3; /* 0x060c */ + struct { + RK_U32 cbcr_ver_coe1_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe1_1 : 10; + } reg4; /* 0x0610 */ + struct { + RK_U32 cbcr_ver_coe1_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe1_3 : 10; + } reg5; /* 0x0614 */ + struct { + RK_U32 cbcr_ver_coe1_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe1_5 : 10; + } reg6; /* 0x0618 */ + struct { + RK_U32 cbcr_ver_coe1_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe1_7 : 10; + } reg7; /* 0x061c */ + struct { + RK_U32 cbcr_ver_coe2_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe2_1 : 10; + } reg8; /* 0x0620 */ + struct { + RK_U32 cbcr_ver_coe2_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe2_3 : 10; + } reg9; /* 0x0624 */ + struct { + RK_U32 cbcr_ver_coe2_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe2_5 : 10; + } reg10; /* 0x0628 */ + struct { + RK_U32 cbcr_ver_coe2_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe2_7 : 10; + } reg11; /* 0x062c */ + struct { + RK_U32 cbcr_ver_coe3_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe3_1 : 10; + } reg12; /* 0x0630 */ + struct { + RK_U32 cbcr_ver_coe3_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe3_3 : 10; + } reg13; /* 0x0634 */ + struct { + RK_U32 cbcr_ver_coe3_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe3_5 : 10; + } reg14; /* 0x0638 */ + struct { + RK_U32 cbcr_ver_coe3_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe3_7 : 10; + } reg15; /* 0x063c */ + struct { + RK_U32 cbcr_ver_coe4_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe4_1 : 10; + } reg16; /* 0x0640 */ + struct { + RK_U32 cbcr_ver_coe4_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe4_3 : 10; + } reg17; /* 0x0644 */ + struct { + RK_U32 cbcr_ver_coe4_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe4_5 : 10; + } reg18; /* 0x0648 */ + struct { + RK_U32 cbcr_ver_coe4_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe4_7 : 10; + } reg19; /* 0x064c */ + struct { + RK_U32 cbcr_ver_coe5_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe5_1 : 10; + } reg20; /* 0x0650 */ + struct { + RK_U32 cbcr_ver_coe5_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe5_3 : 10; + } reg21; /* 0x0654 */ + struct { + RK_U32 cbcr_ver_coe5_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe5_5 : 10; + } reg22; /* 0x0658 */ + struct { + RK_U32 cbcr_ver_coe5_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe5_7 : 10; + } reg23; /* 0x065c */ + struct { + RK_U32 cbcr_ver_coe6_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe6_1 : 10; + } reg24; /* 0x0660 */ + struct { + RK_U32 cbcr_ver_coe6_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe6_3 : 10; + } reg25; /* 0x0664 */ + struct { + RK_U32 cbcr_ver_coe6_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe6_5 : 10; + } reg26; /* 0x0668 */ + struct { + RK_U32 cbcr_ver_coe6_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe6_7 : 10; + } reg27; /* 0x066c */ + struct { + RK_U32 cbcr_ver_coe7_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe7_1 : 10; + } reg28; /* 0x0670 */ + struct { + RK_U32 cbcr_ver_coe7_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe7_3 : 10; + } reg29; /* 0x0674 */ + struct { + RK_U32 cbcr_ver_coe7_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe7_5 : 10; + } reg30; /* 0x0678 */ + struct { + RK_U32 cbcr_ver_coe7_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe7_7 : 10; + } reg31; /* 0x067c */ + struct { + RK_U32 cbcr_ver_coe8_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe8_1 : 10; + } reg32; /* 0x0680 */ + struct { + RK_U32 cbcr_ver_coe8_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe8_3 : 10; + } reg33; /* 0x0684 */ + struct { + RK_U32 cbcr_ver_coe8_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe8_5 : 10; + } reg34; /* 0x0688 */ + struct { + RK_U32 cbcr_ver_coe8_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe8_7 : 10; + } reg35; /* 0x068c */ + struct { + RK_U32 cbcr_ver_coe9_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe9_1 : 10; + } reg36; /* 0x0690 */ + struct { + RK_U32 cbcr_ver_coe9_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe9_3 : 10; + } reg37; /* 0x0694 */ + struct { + RK_U32 cbcr_ver_coe9_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe9_5 : 10; + } reg38; /* 0x0698 */ + struct { + RK_U32 cbcr_ver_coe9_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe9_7 : 10; + } reg39; /* 0x069c */ + struct { + RK_U32 cbcr_ver_coe10_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe10_1 : 10; + } reg40; /* 0x06a0 */ + struct { + RK_U32 cbcr_ver_coe10_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe10_3 : 10; + } reg41; /* 0x06a4 */ + struct { + RK_U32 cbcr_ver_coe10_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe10_5 : 10; + } reg42; /* 0x06a8 */ + struct { + RK_U32 cbcr_ver_coe10_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe10_7 : 10; + } reg43; /* 0x06ac */ + struct { + RK_U32 cbcr_ver_coe11_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe11_1 : 10; + } reg44; /* 0x06b0 */ + struct { + RK_U32 cbcr_ver_coe11_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe11_3 : 10; + } reg45; /* 0x06b4 */ + struct { + RK_U32 cbcr_ver_coe11_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe11_5 : 10; + } reg46; /* 0x06b8 */ + struct { + RK_U32 cbcr_ver_coe11_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe11_7 : 10; + } reg47; /* 0x06bc */ + struct { + RK_U32 cbcr_ver_coe12_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe12_1 : 10; + } reg48; /* 0x06c0 */ + struct { + RK_U32 cbcr_ver_coe12_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe12_3 : 10; + } reg49; /* 0x06c4 */ + struct { + RK_U32 cbcr_ver_coe12_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe12_5 : 10; + } reg50; /* 0x06c8 */ + struct { + RK_U32 cbcr_ver_coe12_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe12_7 : 10; + } reg51; /* 0x06cc */ + struct { + RK_U32 cbcr_ver_coe13_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe13_1 : 10; + } reg52; /* 0x06d0 */ + struct { + RK_U32 cbcr_ver_coe13_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe13_3 : 10; + } reg53; /* 0x06d4 */ + struct { + RK_U32 cbcr_ver_coe13_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe13_5 : 10; + } reg54; /* 0x06d8 */ + struct { + RK_U32 cbcr_ver_coe13_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe13_7 : 10; + } reg55; /* 0x06dc */ + struct { + RK_U32 cbcr_ver_coe14_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe14_1 : 10; + } reg56; /* 0x06e0 */ + struct { + RK_U32 cbcr_ver_coe14_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe14_3 : 10; + } reg57; /* 0x06e4 */ + struct { + RK_U32 cbcr_ver_coe14_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe14_5 : 10; + } reg58; /* 0x06e8 */ + struct { + RK_U32 cbcr_ver_coe14_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe14_7 : 10; + } reg59; /* 0x06ec */ + struct { + RK_U32 cbcr_ver_coe15_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe15_1 : 10; + } reg60; /* 0x06f0 */ + struct { + RK_U32 cbcr_ver_coe15_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe15_3 : 10; + } reg61; /* 0x06f4 */ + struct { + RK_U32 cbcr_ver_coe15_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe15_5 : 10; + } reg62; /* 0x06f8 */ + struct { + RK_U32 cbcr_ver_coe15_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe15_7 : 10; + } reg63; /* 0x06fc */ + struct { + RK_U32 cbcr_ver_coe16_0 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe16_1 : 10; + } reg64; /* 0x0700 */ + struct { + RK_U32 cbcr_ver_coe16_2 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe16_3 : 10; + } reg65; /* 0x0704 */ + struct { + RK_U32 cbcr_ver_coe16_4 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe16_5 : 10; + } reg66; /* 0x0708 */ + struct { + RK_U32 cbcr_ver_coe16_6 : 10; + RK_U32 sw_reserved_1 : 6; + RK_U32 cbcr_ver_coe16_7 : 10; + } reg67; /* 0x070c */ + + } cbcr_ver_coe; + + struct { + struct { + RK_U32 bypass_en : 1; + RK_U32 align_en : 1; + RK_U32 reserved_1 : 2; + RK_U32 format_in : 4; + RK_U32 format_out : 4; + RK_U32 reserved_2 : 19; + RK_U32 auto_gating_en : 1; + } reg0; /* 0x0800 */ + + RK_U32 reg1; /* 0x0804 */ + RK_U32 reg2; /* 0x0808 */ + + struct { + RK_U32 vir_width : 16; + RK_U32 vir_height : 16; + } reg3; /* 0x080C */ + + struct { + RK_U32 yrgb_xsd_en : 1; + RK_U32 yrgb_xsu_en : 1; + RK_U32 yrgb_scl_mode : 2; + RK_U32 yrgb_ysd_en : 1; + RK_U32 yrgb_ysu_en : 1; + RK_U32 yrgb_yscl_mode : 2; + RK_U32 yrgb_dering_en : 1; + RK_U32 yrgb_gt_en : 1; + RK_U32 yrgb_gt_mode : 2; + RK_U32 yrgb_xgt_en : 1; + RK_U32 reserved_1 : 1; + RK_U32 yrgb_xgt_mode : 2; + RK_U32 yrgb_xsd_bypass : 1; + RK_U32 yrgb_ys_bypass : 1; + RK_U32 yrgb_xsu_bypass : 1; + } reg4; /* 0x0810 */ + + struct { + RK_U32 yrgb_src_width : 16; + RK_U32 yrgb_src_height : 16; + } reg5; /* 0x0814 */ + + struct { + RK_U32 yrgb_dst_width : 16; + RK_U32 yrgb_dst_height : 16; + } reg6; /* 0x0818 */ + + struct { + RK_U32 yrgb_dering_sen0 : 5; + RK_U32 reserved_1 : 3; + RK_U32 yrgb_dering_sen1 : 5; + RK_U32 reserved_2 : 3; + RK_U32 yrgb_dering_alpha: 5; + RK_U32 reserved_3 : 3; + RK_U32 yrgb_dering_delta: 5; + } reg7; /* 0x081C */ + + struct { + RK_U32 yrgb_xscl_factor : 16; + RK_U32 yrgb_xscl_offset : 16; + } reg8; /* 0x0820 */ + + struct { + RK_U32 yrgb_yscl_factor : 16; + RK_U32 yrgb_yscl_offset : 16; + } reg9; /* 0x0824 */ + + RK_U32 reg10; /* 0x0828 */ + RK_U32 reg11; /* 0x082C */ + + struct { + RK_U32 cbcr_xsd_en : 1; + RK_U32 cbcr_xsu_en : 1; + RK_U32 cbcr_scl_mode : 2; + RK_U32 cbcr_ysd_en : 1; + RK_U32 cbcr_ysu_en : 1; + RK_U32 cbcr_yscl_mode : 2; + RK_U32 cbcr_dering_en : 1; + RK_U32 cbcr_gt_en : 1; + RK_U32 cbcr_gt_mode : 2; + RK_U32 cbcr_xgt_en : 1; + RK_U32 reserved_1 : 1; + RK_U32 cbcr_xgt_mode : 2; + RK_U32 cbcr_xsd_bypass : 1; + RK_U32 cbcr_ys_bypass : 1; + RK_U32 cbcr_xsu_bypass : 1; + } reg12; /* 0x0830 */ + + struct { + RK_U32 cbcr_src_width : 16; + RK_U32 cbcr_src_height : 16; + } reg13; /* 0x0834 */ + + struct { + RK_U32 cbcr_dst_width : 16; + RK_U32 cbcr_dst_height : 16; + } reg14; /* 0x0838 */ + + struct { + RK_U32 cbcr_dering_sen0 : 5; + RK_U32 reserved_1 : 3; + RK_U32 cbcr_dering_sen1 : 5; + RK_U32 reserved_2 : 3; + RK_U32 cbcr_dering_alpha: 5; + RK_U32 reserved_3 : 3; + RK_U32 cbcr_dering_delta: 5; + } reg15; /* 0x083C */ + + struct { + RK_U32 cbcr_xscl_factor : 16; + RK_U32 cbcr_xscl_offset : 16; + } reg16; /* 0x0840 */ + + struct { + RK_U32 cbcr_yscl_factor : 16; + RK_U32 cbcr_yscl_offset : 16; + } reg17; /* 0x0844 */ + + } common; + +}; /* offset: 0x2000 */ + +#ifdef __cplusplus +extern "C" { +#endif + +void set_dmsr_to_vdpp_reg(struct dmsr_params* p_dmsr_param, struct dmsr_reg* dmsr); + +void vdpp_set_default_zme_param(struct zme_params* param); +void set_zme_to_vdpp_reg(struct zme_params *zme_params, struct zme_reg *zme); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/mpp/vproc/vdpp/vdpp_reg.h b/mpp/vproc/vdpp/vdpp_reg.h new file mode 100644 index 00000000..a2d248d8 --- /dev/null +++ b/mpp/vproc/vdpp/vdpp_reg.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: Apache-2.0 OR MIT */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#ifndef __VDPP_REG_H__ +#define __VDPP_REG_H__ + +#include "rk_type.h" + +#define VDPP_REG_OFF_DMSR (0x80) +#define VDPP_REG_OFF_YRGB_HOR_COE (0x2000) +#define VDPP_REG_OFF_YRGB_VER_COE (0x2200) +#define VDPP_REG_OFF_CBCR_HOR_COE (0x2400) +#define VDPP_REG_OFF_CBCR_VER_COE (0x2600) +#define VDPP_REG_OFF_ZME_COMMON (0x2800) + +struct vdpp_reg { + struct { + + struct { + RK_U32 sw_vdpp_frm_en : 1; + } reg0; // 0x0000 + + struct { + RK_U32 sw_vdpp_src_fmt : 2; + RK_U32 sw_reserved_1 : 2; + RK_U32 sw_vdpp_src_yuv_swap : 2; + RK_U32 sw_reserved_2 : 2; + RK_U32 sw_vdpp_dst_fmt : 2; + RK_U32 sw_reserved_3 : 2; + RK_U32 sw_vdpp_dst_yuv_swap : 2; + RK_U32 sw_reserved_4 : 2; + RK_U32 sw_vdpp_debug_data_en: 1; + RK_U32 sw_reserved_5 : 3; + RK_U32 sw_vdpp_rst_protect_dis : 1; + RK_U32 sys_vdpp_sreset_p : 1; + RK_U32 sw_vdpp_init_dis : 1; + RK_U32 sw_reserved_6 : 1; + RK_U32 sw_vdpp_dbmsr_en : 1; + } reg1; // 0x0004 + + struct { + RK_U32 sw_vdpp_working_mode : 2; + } reg2; // 0x0008 + + RK_U32 reg3; // 0x000C + + struct { + RK_U32 sw_vdpp_clk_on : 1; + RK_U32 sw_md_clk_on : 1; + RK_U32 sw_dect_clk_on : 1; + RK_U32 sw_me_clk_on : 1; + RK_U32 sw_mc_clk_on : 1; + RK_U32 sw_eedi_clk_on : 1; + RK_U32 sw_ble_clk_on : 1; + RK_U32 sw_out_clk_on : 1; + RK_U32 sw_ctrl_clk_on : 1; + RK_U32 sw_ram_clk_on : 1; + RK_U32 sw_dma_clk_on : 1; + RK_U32 sw_reg_clk_on : 1; + } reg4; // 0x0010 + + struct { + RK_U32 ro_arst_finish_done : 1; + } reg5; // 0x0014 + + RK_U32 reg6; // 0x0018 + RK_U32 reg7; // 0x001c + + struct { + RK_U32 sw_vdpp_frm_done_en : 1; + RK_U32 sw_vdpp_osd_max_en : 1; + RK_U32 sw_reserved_1 : 2; + RK_U32 sw_vdpp_bus_error_en : 1; + RK_U32 sw_vdpp_timeout_int_en : 1; + RK_U32 sw_vdpp_config_error_en : 1; + } reg8; // 0x0020 + + struct { + RK_U32 sw_vdpp_frm_done_clr : 1; + RK_U32 sw_vdpp_osd_max_clr : 1; + RK_U32 sw_reserved_1 : 2; + RK_U32 sw_vdpp_bus_error_clr: 1; + RK_U32 sw_vdpp_timeout_int_clr : 1; + RK_U32 sw_vdpp_config_error_clr : 1; + } reg9; // 0x0024 + + struct { + RK_U32 ro_frm_done_sts : 1; + RK_U32 ro_osd_max_sts : 1; + RK_U32 sw_reserved_1 : 2; + RK_U32 ro_bus_error_sts : 1; + RK_U32 ro_timeout_sts : 1; + RK_U32 ro_config_error_sts : 1; + } reg10; // 0x0028, read only + + struct { + RK_U32 ro_frm_done_raw : 1; + RK_U32 ro_osd_max_raw : 1; + RK_U32 sw_reserved_1 : 2; + RK_U32 ro_bus_error_raw : 1; + RK_U32 ro_timeout_raw : 1; + RK_U32 ro_config_error_raw : 1; + } reg11; // 0x002C, read only + + struct { + RK_U32 sw_vdpp_src_vir_y_stride : 16; + } reg12; // 0x0030 + + struct { + RK_U32 sw_vdpp_dst_vir_y_stride : 16; + } reg13; // 0x0034 + + struct { + RK_U32 sw_vdpp_src_pic_width : 11; + RK_U32 sw_reserved_1 : 1; + RK_U32 sw_vdpp_src_right_redundant : 4; + RK_U32 sw_vdpp_src_pic_height : 11; + RK_U32 sw_reserved_2 : 1; + RK_U32 sw_vdpp_src_down_redundant : 3; + } reg14; // 0x0038 + + struct { + RK_U32 sw_vdpp_dst_pic_width : 11; + RK_U32 sw_reserved_1 : 1; + RK_U32 sw_vdpp_dst_right_redundant : 4; + RK_U32 sw_vdpp_dst_pic_height : 11; + } reg15; // 0x003C + + RK_U32 reg16; // 0x0040 + RK_U32 reg17; // 0x0044 + RK_U32 reg18; // 0x0048 + RK_U32 reg19; // 0x004C + + struct { + RK_U32 sw_vdpp_timeout_cnt : 31; + RK_U32 sw_vdpp_timeout_en : 1; + } reg20; // 0x0050 + + struct { + RK_U32 svnbuild : 20; + RK_U32 minor : 8; + RK_U32 major : 4; + } reg21; // 0x0054 + + struct { + RK_U32 dbg_frm_cnt : 16; + } reg22; // 0x0058 + + RK_U32 reg23; // 0x005C + + struct { + RK_U32 sw_vdpp_src_addr_y : 32; + } reg24; // 0x0060 + + struct { + RK_U32 sw_vdpp_src_addr_uv : 32; + } reg25; // 0x0064 + + struct { + RK_U32 sw_vdpp_dst_addr_y : 32; + } reg26; // 0x0068 + + struct { + RK_U32 sw_vdpp_dst_addr_uv : 32; + } reg27; // 0x006C + + } common; // offset: 0x1000 + RK_U32 reg_common_28_31[4]; + +}; + +#endif diff --git a/osal/inc/mpp_dev_defs.h b/osal/inc/mpp_dev_defs.h index 5bc43420..04b61eba 100644 --- a/osal/inc/mpp_dev_defs.h +++ b/osal/inc/mpp_dev_defs.h @@ -43,6 +43,7 @@ typedef enum MppClientType_e { VPU_CLIENT_VEPU22 = 24, /* 0x01000000 */ IEP_CLIENT_TYPE = 28, /* 0x10000000 */ + VDPP_CLIENT_TYPE = 29, /* 0x20000000 */ VPU_CLIENT_BUTT, } MppClientType; @@ -68,6 +69,8 @@ typedef enum MppClientType_e { #define HAVE_VEPU22 (1 << VPU_CLIENT_VEPU22) /* 0x01000000 */ /* RK Image Enhance Processor for deinterlacing */ #define HAVE_IEP (1 << IEP_CLIENT_TYPE) /* 0x10000000 */ +/* RK Image Enhance Processor for dispaly */ +#define HAVE_VDPP (1 << VDPP_CLIENT_TYPE) /* 0x20000000 */ /* Platform image process hardware feature */ #define HAVE_IPP (0x00000001)