usaeg:
<exe> <-s|--spec> <|h264|h265|avs2|vp9|av1|jpeg|all> [-q]
-h|--help: help info
-s|--spec: spec, |h264|h265|avs2|vp9|av1|jpeg|all
-sv|--save: save test file
-l|--log: exec mpp demo with log
-d|--debug: dump debug info
Change-Id: I5c69570d0a2834c0114c75ed3f64c734e238d4b6
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Platform：All
Spec:encoder
Error case:
h264e_dpb: find_cpb_frame can not find match frm 0.
Solution:
Since info->st_gop = st_cfg_cnt - 1 cannot accurately represent
the number of st_cfg, st_cfg_cnt is used to replace info->st_gop.
Change-Id: I3a2f494de5dcec0182d0431fb2c1b653cbe3bf84
Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
Platform: RK3576
Spec: av1
Error case:
When the resolution is switched and the width and height
are enlarged, the segid space is insufficient
Solution:
Determine whether the cdf/segid space is sufficient and
recalculate if insufficient
Reported-by: Jinsen Chen <kevin.chen@rock-chips.com> KTC
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I8df6773337e093f0767d18d552895b3ec7601efa
The default misc buffer group do not have the flag. We need to seperate
the default misc group with different flag.
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I14941eedfe9c06ec978a12061ba33e12495aa038
Platform: All
Spec: h265
Error case:
nalu payloads with byte sequence 00 00 00 xx data used to be incorrectly detected as start code.
Solution:
Modify the start code detection logic by replacing
condition src[i+2] < 2 with src[i+2] == 1
Reported by: redmine #545594
Source: kiloview-p3.hevc
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I7e544e127f324df42418765adc5a7a51e082736e
Platform: General
Spec: all
Reported-by: Jinsen Chen <kevin.chen@rock-chips.com>
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Change-Id: Ib5a9ac80f36d9e3211882a74cc1acd4727b4c477
Platform: RK3576
Spec: h265
Error case:
When decoding a video sequence, the interrupt reports
a bitstream error, but the video sequence is actually
normal.
The value of num_negative_pics shall be in the range of
0 to sps_max_dec_pic_buffering_minus1[ sps_max_sub_layers_minus1 ]
For frame5 (starting from 0)
sps_max_dec_pic_buffering_minus1[ sps_max_sub_layers_minus1 ] = 4
num_negative_pics = 5
Solution:
Mask out undefined bits in cabac error detection
Reported-by: redmine #540704
Source: H.265 HEVC_1280x720_Movie Trailer_复仇者联盟.预告片.h265.mp4.mp4
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Change-Id: I9f0b6c744bbc56ad721d45461a18f8124956ffc7
The encoder speed mode is in range of 0 ~ 3.
0 - normal mode with all mode decision path enabled.
1 - fast mode
2 - faster mode
3 - fastest mode
Signed-off-by: toby.zhang <toby.zhang@rock-chips.com>
Change-Id: I0c607adbc1e4cea4025fa8a3816dc3a1ec1f13a1
Signed-off-by: toby.zhang <toby.zhang@rock-chips.com>
Platform: General
Spec: avs2
Error case:
In AVS2, CTU supports both 64 and 32 alignment. The
sys_cfg defaults to 64 alignment. However, if the
parsed CTU size is 32, it may cause additional info
changes.
This is because, initially, when calculating the
stride, there is no external stride configuration,
so it defaults to 64 alignment. After parsing the
video sequence, the stride is configured, and
calculations should then follow the configured
stride.
Solution:
During the parsing process, the stride is not set
and is entirely calculated by sys_cfg.
Reported-by: Liming Xu <rimon.xu@rock-chips.com>
Source: test_avs2_160x90.av1
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Change-Id: I0fed8b86391a03651f22ef859ec2ff1c02647b12
Platform: General
Solution:
To resolve GPU compatibility issues, horizontal pixel
alignment relies on processing in the parser to avoid
incompatibility issues caused by byte alignment intro
-duced by pixel alignment.
Reported-by: Jinsen Chen <kevin.chen@rock-chips.com>
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Change-Id: Id17abf9e39a6b9bc5bd468ff50eadaf45b9d6520
Platform: General
Error case:
1. Image height is 1080
2. Use SLOTS_FRAME_INFO command to set frame information
3. Use SLOT_FRAME command to set info change
4. info change: ver_stride 1080 -> 1088
5. Generates an avoidable info change, re-applies for buffer,
affects fast play
Solution:
For avc, in sys_cfg, align directly according to ctu
Reported-by: Jinsen Chen <kevin.chen@rock-chips.com>
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Change-Id: I87e396ae8ac8ea55d6bd8ad314d52e2b6f796e98
Platform:
RK3399, vp9/h265
RK3562/RK3576/RK3588, vp9
Error case:
The stride result calculated by sys_cfg is not
synchronized with the HAL layer.
Change-Id: I98f4e18fcb9af19850ca7dbd201bded8137e7861
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
update hsd_mode/vsd_mode before blk_size calculation, fix the mismatch
between hsd_mode/vsd_mode registers and blk_size registers.
Change-Id: I49215f99430382ec8f59adad3cd81b9f9ab736d8
Signed-off-by: akira.wang <akira.wang@rock-chips.com>
1. Sync kmpp_obj_func.h and kmpp_obj_helper.h from kernel.
2. Add more kmpp_obj function from kernel.
3. Add KmppFrame module.
4. Fix kmpp_obj_check failure.
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: Ib333370eb36c7b63ef50d3e52cf7fd753c9e5af1
Platform: General
Spec: av1
Reported-by: Herman Chen <herman.chen@rock-chips.com>
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Change-Id: I338545eb1fdb7e726c8c6f81c103061fd0dc9c9d
