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Revert "usb: dwc3: core: Do not perform GCTL_CORE_SOFTRESET during bootup"

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This reverts commit d376ca6716.

It's reported that when using Radxa CM5 with RPI CM4 IO board,
USB2.0 host ports don't work.

By default RK3588 USB DRD DWC3_0 (usb@fc000000) is set in otg mode.
In hardware, RK3588 TYPEC0_USB20_OTG_ID is pulled down to groud
by a 2.2k resistor.

It is needed to perform GCTL_CORE_SOFTRESET during bootup.

Signed-off-by: Stephen Chen <stephen@radxa.com>
(cherry picked from commit ec8a9ad8bf5ddbe8ad7cba3d0deafbcba204092a)
Signed-off-by: Joshua Riek <jjriek@verizon.net>
This commit is contained in:
Stephen Chen 2024-04-22 21:59:23 +08:00 • committed by Mecid Urganci
parent b6205ab4a9
commit 0e40ee39c5
1 changed files with 3 additions and 7 deletions
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10
drivers/usb/dwc3/core.c
View file

@ -196,13 +196,9 @@ static void __dwc3_set_mode(struct work_struct *work)
break;
}
/*
* When current_dr_role is not set, there's no role switching.
* Only perform GCTL.CoreSoftReset when there's DRD role switching.
*/
if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
/* For DRD host or device mode only */
if ((DWC3_IP_IS(DWC3) || DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) {
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg |= DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);