From 0e40ee39c5ea7c20105d57a09ab7b9cdb4e32a43 Mon Sep 17 00:00:00 2001 From: Stephen Chen Date: Mon, 22 Apr 2024 21:59:23 +0800 Subject: [PATCH] Revert "usb: dwc3: core: Do not perform GCTL_CORE_SOFTRESET during bootup" This reverts commit d376ca67168316d5e004268600b8c978e1b87cff. It's reported that when using Radxa CM5 with RPI CM4 IO board, USB2.0 host ports don't work. By default RK3588 USB DRD DWC3_0 (usb@fc000000) is set in otg mode. In hardware, RK3588 TYPEC0_USB20_OTG_ID is pulled down to groud by a 2.2k resistor. It is needed to perform GCTL_CORE_SOFTRESET during bootup. Signed-off-by: Stephen Chen (cherry picked from commit ec8a9ad8bf5ddbe8ad7cba3d0deafbcba204092a) Signed-off-by: Joshua Riek --- drivers/usb/dwc3/core.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 6f2a35b6806b..8c2a02b38f26 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -196,13 +196,9 @@ static void __dwc3_set_mode(struct work_struct *work) break; } - /* - * When current_dr_role is not set, there's no role switching. - * Only perform GCTL.CoreSoftReset when there's DRD role switching. - */ - if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || - DWC3_VER_IS_PRIOR(DWC31, 190A)) && - desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { + /* For DRD host or device mode only */ + if ((DWC3_IP_IS(DWC3) || DWC3_VER_IS_PRIOR(DWC31, 190A)) && + dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) { reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg |= DWC3_GCTL_CORESOFTRESET; dwc3_writel(dwc->regs, DWC3_GCTL, reg);