mirror of
https://github.com/nyanmisaka/mpp.git
synced 2026-01-24 03:30:40 +01:00
2b35cee0ce
1. Move mpp_log.h to inc for external user. 2. Add mpp_debug.h for mpp internal logging. 3. Fix some warning. 4. Add log level setup function. 5. Check env log_level value in mpp_get_log_level call. NOTE: 1. mpp internal module should use mpp_debug.h and mpp external user should use mpp_log.h 2. Use mpp_get_log_level to update mpp_log_level when the env changed. Change-Id: I90a55a02a72db177533013280dfe111ca3479229 Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
425 lines
11 KiB
C
425 lines
11 KiB
C
/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_AVSD_REG_H__
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#define __HAL_AVSD_REG_H__
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#include "mpp_debug.h"
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#include "mpp_device.h"
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#include "parser_api.h"
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#include "hal_avsd_api.h"
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#include "avsd_syntax.h"
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#define AVSD_HAL_DBG_ERROR (0x00000001)
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#define AVSD_HAL_DBG_ASSERT (0x00000002)
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#define AVSD_HAL_DBG_WARNNING (0x00000004)
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#define AVSD_HAL_DBG_TRACE (0x00000008)
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#define AVSD_HAL_DBG_OFFSET (0x00010000)
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extern RK_U32 avsd_hal_debug;
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#define AVSD_HAL_DBG(level, fmt, ...)\
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do {\
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if (level & avsd_hal_debug)\
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{ mpp_log(fmt, ## __VA_ARGS__); }\
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} while (0)
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#define AVSD_HAL_TRACE(fmt, ...)\
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do {\
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if (AVSD_HAL_DBG_TRACE & avsd_hal_debug)\
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{ mpp_log_f(fmt, ## __VA_ARGS__); }\
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} while (0)
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#define INP_CHECK(ret, val, ...)\
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do{\
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if ((val)) { \
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ret = MPP_ERR_INIT; \
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AVSD_HAL_DBG(AVSD_HAL_DBG_WARNNING, "input empty(%d).\n", __LINE__); \
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goto __RETURN; \
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}\
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} while (0)
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#define FUN_CHECK(val)\
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do{\
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if ((val) < 0) {\
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AVSD_HAL_DBG(AVSD_HAL_DBG_WARNNING, "Function error(%d).\n", __LINE__); \
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goto __FAILED; \
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}\
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} while (0)
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//!< memory malloc check
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#define MEM_CHECK(ret, val, ...)\
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do{\
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if (!(val)) {\
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ret = MPP_ERR_MALLOC; \
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mpp_err_f("malloc buffer error(%d).\n", __LINE__); \
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goto __FAILED; \
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}\
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} while (0)
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#define FIELDPICTURE 0
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#define FRAMEPICTURE 1
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enum {
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IFRAME = 0,
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PFRAME = 1,
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BFRAME = 2
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};
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typedef struct avsd_hal_picture_t {
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RK_U32 valid;
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RK_U32 pic_type;
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RK_U32 pic_code_type;
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RK_U32 picture_distance;
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RK_S32 slot_idx;
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} AvsdHalPic_t;
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typedef struct avsd_hal_ctx_t {
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MppBufSlots frame_slots;
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MppBufSlots packet_slots;
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MppBufferGroup buf_group;
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MppCbCtx *dec_cb;
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MppDev dev;
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AvsdSyntax_t syn;
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RK_U32 *p_regs;
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MppBuffer mv_buf;
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AvsdHalPic_t pic[3];
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//!< add for control
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RK_U32 first_field;
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RK_U32 prev_pic_structure;
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RK_U32 prev_pic_code_type;
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RK_S32 future2prev_past_dist;
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RK_S32 work0;
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RK_S32 work1;
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RK_S32 work_out;
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RK_U32 data_offset;
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RK_U32 frame_no;
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} AvsdHalCtx_t;
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#define AVSD_REGISTERS 60
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typedef struct {
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RK_U32 sw00;
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struct {
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RK_U32 dec_e : 1;
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RK_U32 reserve0 : 3;
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RK_U32 dec_irq_dis : 1;
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RK_U32 dec_abort_e : 1;
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RK_U32 reserve1 : 2;
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RK_U32 dec_irq : 1;
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RK_U32 reserve2 : 2;
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RK_U32 dec_abort_int : 1;
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RK_U32 dec_rdy_int : 1;
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RK_U32 dec_bus_int : 1;
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RK_U32 dec_buffer_int : 1;
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RK_U32 dec_aso_int : 1;
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RK_U32 dec_error_int : 1;
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RK_U32 dec_slice_int : 1;
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RK_U32 dec_timeout : 1;
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RK_U32 reserve3 : 5;
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RK_U32 dec_pic_inf : 1;
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RK_U32 reserve4 : 7;
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} sw01;
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union {
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struct {
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RK_U32 dec_max_burst : 5;
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RK_U32 dec_scmd_dis : 1;
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RK_U32 dec_adv_pre_dis : 1;
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RK_U32 tiled_mode_lsb : 1;
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RK_U32 dec_out_endian : 1;
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RK_U32 dec_in_endian : 1;
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RK_U32 dec_clk_gate_e : 1;
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RK_U32 dec_latency : 6;
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RK_U32 dec_out_tiled_e : 1;
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RK_U32 dec_2chan_dis : 1;
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RK_U32 dec_outswap32_e : 1;
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RK_U32 dec_inswap32_e : 1;
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RK_U32 dec_strendian_e : 1;
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RK_U32 dec_strswap32_e : 1;
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RK_U32 dec_timeout_e : 1;
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RK_U32 dec_axi_rd_id : 8;
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};
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struct {
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RK_U32 reserve0 : 5;
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RK_U32 priority_mode : 3;
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RK_U32 reserve1 : 9;
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RK_U32 tiled_mode_msb : 1;
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RK_U32 dec_data_disc_e : 1;
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RK_U32 reserve2 : 13;
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};
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} sw02;
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struct {
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RK_U32 dec_axi_wr_id : 8;
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RK_U32 dec_ahb_hlock_e : 1;
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RK_U32 picord_count_e : 1;
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RK_U32 seq_mbaff_e : 1;
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RK_U32 reftopfirst_e : 1;
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RK_U32 write_mvs_e : 1;
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RK_U32 pic_fixed_quant : 1;
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RK_U32 filtering_dis : 1;
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RK_U32 dec_out_dis : 1;
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RK_U32 ref_topfield_e : 1;
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RK_U32 sorenson_e : 1;
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RK_U32 fwd_interlace_e : 1;
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RK_U32 pic_topfiled_e : 1;
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RK_U32 pic_inter_e : 1;
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RK_U32 pic_b_e : 1;
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RK_U32 pic_fieldmode_e : 1;
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RK_U32 pic_interlace_e : 1;
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RK_U32 pjpeg_e : 1;
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RK_U32 divx3_e : 1;
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RK_U32 skip_mode : 1;
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RK_U32 rlc_mode_e : 1;
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RK_U32 dec_mode : 4;
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} sw03;
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struct {
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RK_U32 pic_refer_flag : 1;
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RK_U32 reverse0 : 10;
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RK_U32 pic_mb_height_p : 8;
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RK_U32 mb_width_off : 4;
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RK_U32 pic_mb_width : 9;
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} sw04;
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union {
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struct {
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RK_U32 fieldpic_flag_e : 1;
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RK_S32 reserve0 : 31;
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};
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struct {
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RK_U32 beta_offset : 5;
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RK_U32 alpha_offset : 5;
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RK_U32 reserve1 : 16;
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RK_U32 strm_start_bit : 6;
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};
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} sw05;
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struct {
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RK_U32 stream_len : 24;
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RK_U32 stream_len_ext : 1;
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RK_U32 init_qp : 6;
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RK_U32 start_code_e : 1;
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} sw06;
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struct {
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RK_U32 reserve0 : 25;
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RK_U32 avs_h264_h_ext : 1;
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RK_U32 reserve1 : 6;
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} sw07;
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RK_U32 sw08;
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RK_U32 sw09;
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RK_U32 sw10;
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RK_U32 sw11;
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struct {
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RK_U32 rlc_vlc_base : 32;
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} sw12;
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union {
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struct {
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RK_U32 dec_out_base : 32;
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};
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struct { //!< left move 10bit
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RK_U32 reserve0 : 11;
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RK_U32 dpb_ilace_mode : 1;
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RK_U32 reserve1 : 20;
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};
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} sw13;
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union {
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RK_U32 refer0_base : 32;
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struct { //!< left move 10bit
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RK_U32 reserve0 : 10;
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RK_U32 refer0_topc_e : 1;
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RK_U32 refer0_field_e : 1;
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RK_U32 reserve1 : 20;
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};
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} sw14;
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union {
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struct {
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RK_U32 refer1_base : 32;
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};
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struct { //!< left move 10bit
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RK_U32 reserve0 : 10;
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RK_U32 refer1_topc_e : 1;
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RK_U32 refer1_field_e : 1;
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RK_U32 reserve1 : 20;
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};
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} sw15;
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union {
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struct {
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RK_U32 refer2_base : 32;
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};
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struct { //!< left move 10bit
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RK_U32 reserve0 : 10;
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RK_U32 refer2_topc_e : 1;
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RK_U32 refer2_field_e : 1;
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RK_U32 reserve1 : 20;
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};
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} sw16;
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union {
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struct {
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RK_U32 refer3_base : 32;
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};
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struct { //!< left move 10bit
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RK_U32 reserve0 : 10;
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RK_U32 refer3_topc_e : 1;
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RK_U32 refer3_field_e : 1;
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RK_U32 reserve1 : 20;
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};
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} sw17;
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struct {
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RK_U32 prev_anc_type : 1;
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RK_U32 reverse0 : 31;
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} sw18;
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RK_U32 sw19_27[9];
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struct {
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RK_U32 ref_invd_cur_0 : 16;
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RK_U32 ref_invd_cur_1 : 16;
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} sw28;
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struct {
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RK_U32 ref_invd_cur_2 : 16;
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RK_U32 ref_invd_cur_3 : 16;
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} sw29;
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struct {
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RK_U32 ref_dist_cur_0 : 16;
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RK_U32 ref_dist_cur_1 : 16;
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} sw30;
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struct {
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RK_U32 ref_dist_cur_2 : 16;
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RK_U32 ref_dist_cur_3 : 16;
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} sw31;
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struct {
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RK_U32 ref_invd_col_0 : 16;
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RK_U32 ref_invd_col_1 : 16;
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} sw32;
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struct {
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RK_U32 ref_invd_col_2 : 16;
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RK_U32 ref_invd_col_3 : 16;
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} sw33;
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struct {
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RK_U32 reserve0 : 2;
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RK_U32 pred_bc_tap_1_1 : 10;
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RK_U32 pred_bc_tap_1_0 : 10;
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RK_U32 pred_bc_tap_0_3 : 10;
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} sw34;
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struct {
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RK_U32 reserve0 : 12;
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RK_U32 pred_bc_tap_1_3 : 10;
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RK_U32 pred_bc_tap_1_2 : 10;
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} sw35;
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RK_U32 sw36_40[5];
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struct {
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RK_U32 dir_mv_base : 32;
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} sw41;
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struct {
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RK_U32 ref_delta_cur_3 : 3;
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RK_U32 ref_delta_cur_2 : 3;
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RK_U32 ref_delta_cur_1 : 3;
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RK_U32 ref_delta_cur_0 : 3;
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RK_U32 ref_delta_col_3 : 3;
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RK_U32 ref_delta_col_2 : 3;
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RK_U32 ref_delta_col_1 : 3;
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RK_U32 ref_delta_col_0 : 3;
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RK_U32 weight_qp_1 : 8;
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} sw42;
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struct {
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RK_U32 weight_qp_5 : 8;
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RK_U32 weight_qp_4 : 8;
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RK_U32 weight_qp_3 : 8;
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RK_U32 weight_qp_2 : 8;
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} sw43;
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struct {
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RK_U32 weight_qp_0 : 8;
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RK_U32 qp_delta_cr : 6;
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RK_U32 qp_delta_cb : 6;
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RK_U32 pb_field_enhance_e : 1;
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RK_U32 no_fwd_ref_e : 1;
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RK_U32 avs_aec_e : 1;
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RK_U32 weight_qp_model : 2;
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RK_U32 weight_qp_e : 1;
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RK_U32 dec_avsp_ena : 1;
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RK_U32 reserve0 : 5;
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} sw44;
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struct {
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RK_U32 dir_mv_base2 : 32;
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} sw45;
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RK_U32 sw46;
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RK_U32 sw47;
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struct {
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RK_U32 reserve0 : 14;
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RK_U32 startmb_y : 9;
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RK_U32 startmb_x : 9;
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} sw48;
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struct {
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RK_U32 reserve0 : 2;
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RK_U32 pred_bc_tap_0_2 : 10;
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RK_U32 pred_bc_tap_0_1 : 10;
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RK_U32 pred_bc_tap_0_0 : 10;
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} sw49;
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RK_U32 sw50;
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struct {
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RK_U32 refbu_y_offset : 9;
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RK_U32 reserve0 : 3;
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RK_U32 refbu_fparmod_e : 1;
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RK_U32 refbu_eval_e : 1;
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RK_U32 refbu_picid : 5;
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RK_U32 refbu_thr : 12;
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RK_U32 refbu_e : 1;
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} sw51;
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struct {
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RK_U32 refbu_intra_sum : 16;
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RK_U32 refbu_hit_sum : 16;
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} sw52;
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struct {
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RK_U32 refbu_y_mv_sum : 22;
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RK_U32 reserve0 : 10;
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} sw53;
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RK_U32 sw54;
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struct {
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RK_U32 apf_threshold : 14;
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RK_U32 refbu2_picid : 5;
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RK_U32 refbu2_thr : 12;
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RK_U32 refbu2_buf_e : 1;
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} sw55;
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struct {
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RK_U32 refbu_bot_sum : 16;
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RK_U32 refbu_top_sum : 16;
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};
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RK_U32 sw57;
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struct {
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RK_U32 reserve0 : 31;
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RK_U32 serv_merge_dis : 1;
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} sw58;
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RK_U32 sw59;
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} AvsdRegs_t;
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#ifdef __cplusplus
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extern "C" {
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#endif
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MPP_RET set_defalut_parameters(AvsdHalCtx_t *p_hal);
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MPP_RET set_regs_parameters(AvsdHalCtx_t *p_hal, HalDecTask *task);
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MPP_RET update_parameters(AvsdHalCtx_t *p_hal);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__HAL_AVSD_REG_H__*/
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