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38c370076b
Change-Id: I8819b8ae1224f2166f555a9905d097fa2ff24ea4 Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
254 lines
6.8 KiB
C
254 lines
6.8 KiB
C
/* SPDX-License-Identifier: Apache-2.0 OR MIT */
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __VDPP2_H__
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#define __VDPP2_H__
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#include "vdpp2_reg.h"
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#include "vdpp_common.h"
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/* vdpp log marco */
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#define VDPP2_DBG_TRACE (0x00000001)
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#define VDPP2_DBG_INT (0x00000002)
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#define VDPP2_DBG_CHECK (0x00000004)
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extern RK_U32 vdpp2_debug;
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#define VDPP2_DBG(level, fmt, ...)\
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do {\
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if (level & vdpp2_debug)\
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{ mpp_log(fmt, ## __VA_ARGS__); }\
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} while (0)
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typedef struct ShpParams_t {
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RK_S32 sharp_enable;
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RK_S32 sharp_coloradj_bypass_en;
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RK_S32 lti_h_enable;
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RK_S32 lti_h_radius;
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RK_S32 lti_h_slope;
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RK_S32 lti_h_thresold;
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RK_S32 lti_h_gain;
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RK_S32 lti_h_noise_thr_pos;
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RK_S32 lti_h_noise_thr_neg;
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RK_S32 lti_v_enable;
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RK_S32 lti_v_radius;
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RK_S32 lti_v_slope;
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RK_S32 lti_v_thresold;
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RK_S32 lti_v_gain;
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RK_S32 lti_v_noise_thr_pos;
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RK_S32 lti_v_noise_thr_neg;
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RK_S32 cti_h_enable;
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RK_S32 cti_h_radius;
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RK_S32 cti_h_slope;
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RK_S32 cti_h_thresold;
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RK_S32 cti_h_gain;
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RK_S32 cti_h_noise_thr_pos;
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RK_S32 cti_h_noise_thr_neg;
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RK_S32 peaking_enable;
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RK_S32 peaking_gain;
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RK_S32 peaking_coring_enable;
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RK_S32 peaking_coring_zero[8];
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RK_S32 peaking_coring_thr[8];
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RK_S32 peaking_coring_ratio[8];
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RK_S32 peaking_gain_enable;
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RK_S32 peaking_gain_pos[8];
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RK_S32 peaking_gain_neg[8];
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RK_S32 peaking_limit_ctrl_enable;
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RK_S32 peaking_limit_ctrl_pos0[8];
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RK_S32 peaking_limit_ctrl_pos1[8];
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RK_S32 peaking_limit_ctrl_neg0[8];
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RK_S32 peaking_limit_ctrl_neg1[8];
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RK_S32 peaking_limit_ctrl_ratio[8];
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RK_S32 peaking_limit_ctrl_bnd_pos[8];
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RK_S32 peaking_limit_ctrl_bnd_neg[8];
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RK_S32 peaking_edge_ctrl_enable;
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RK_S32 peaking_edge_ctrl_non_dir_thr;
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RK_S32 peaking_edge_ctrl_dir_cmp_ratio;
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RK_S32 peaking_edge_ctrl_non_dir_wgt_offset;
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RK_S32 peaking_edge_ctrl_non_dir_wgt_ratio;
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RK_S32 peaking_edge_ctrl_dir_cnt_thr;
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RK_S32 peaking_edge_ctrl_dir_cnt_avg;
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RK_S32 peaking_edge_ctrl_dir_cnt_offset;
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RK_S32 peaking_edge_ctrl_diag_dir_thr;
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RK_S32 peaking_edge_ctrl_diag_adj_gain_tab[8];
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RK_S32 peaking_estc_enable;
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RK_S32 peaking_estc_delta_offset_h;
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RK_S32 peaking_estc_alpha_over_h;
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RK_S32 peaking_estc_alpha_under_h;
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RK_S32 peaking_estc_alpha_over_unlimit_h;
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RK_S32 peaking_estc_alpha_under_unlimit_h;
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RK_S32 peaking_estc_delta_offset_v;
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RK_S32 peaking_estc_alpha_over_v;
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RK_S32 peaking_estc_alpha_under_v;
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RK_S32 peaking_estc_alpha_over_unlimit_v;
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RK_S32 peaking_estc_alpha_under_unlimit_v;
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RK_S32 peaking_estc_delta_offset_d0;
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RK_S32 peaking_estc_alpha_over_d0;
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RK_S32 peaking_estc_alpha_under_d0;
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RK_S32 peaking_estc_alpha_over_unlimit_d0;
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RK_S32 peaking_estc_alpha_under_unlimit_d0;
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RK_S32 peaking_estc_delta_offset_d1;
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RK_S32 peaking_estc_alpha_over_d1;
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RK_S32 peaking_estc_alpha_under_d1;
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RK_S32 peaking_estc_alpha_over_unlimit_d1;
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RK_S32 peaking_estc_alpha_under_unlimit_d1;
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RK_S32 peaking_estc_delta_offset_non;
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RK_S32 peaking_estc_alpha_over_non;
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RK_S32 peaking_estc_alpha_under_non;
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RK_S32 peaking_estc_alpha_over_unlimit_non;
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RK_S32 peaking_estc_alpha_under_unlimit_non;
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RK_S32 peaking_filter_cfg_diag_enh_coef;
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RK_S32 peaking_filt_core_H0[6];
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RK_S32 peaking_filt_core_H1[6];
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RK_S32 peaking_filt_core_H2[6];
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RK_S32 peaking_filt_core_H3[6];
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RK_S32 peaking_filt_core_V0[3];
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RK_S32 peaking_filt_core_V1[3];
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RK_S32 peaking_filt_core_V2[3];
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RK_S32 peaking_filt_core_USM[3];
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RK_S32 shootctrl_enable;
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RK_S32 shootctrl_filter_radius;
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RK_S32 shootctrl_delta_offset;
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RK_S32 shootctrl_alpha_over;
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RK_S32 shootctrl_alpha_under;
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RK_S32 shootctrl_alpha_over_unlimit;
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RK_S32 shootctrl_alpha_under_unlimit;
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RK_S32 global_gain_enable;
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RK_S32 global_gain_lum_mode;
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RK_S32 global_gain_lum_grd[6];
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RK_S32 global_gain_lum_val[6];
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RK_S32 global_gain_adp_grd[6];
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RK_S32 global_gain_adp_val[6];
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RK_S32 global_gain_var_grd[6];
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RK_S32 global_gain_var_val[6];
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RK_S32 color_ctrl_enable;
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RK_S32 color_ctrl_p0_scaling_coef;
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RK_S32 color_ctrl_p0_point_u;
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RK_S32 color_ctrl_p0_point_v;
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RK_S32 color_ctrl_p0_roll_tab[16];
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RK_S32 color_ctrl_p1_scaling_coef;
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RK_S32 color_ctrl_p1_point_u;
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RK_S32 color_ctrl_p1_point_v;
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RK_S32 color_ctrl_p1_roll_tab[16];
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RK_S32 color_ctrl_p2_scaling_coef;
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RK_S32 color_ctrl_p2_point_u;
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RK_S32 color_ctrl_p2_point_v;
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RK_S32 color_ctrl_p2_roll_tab[16];
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RK_S32 color_ctrl_p3_scaling_coef;
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RK_S32 color_ctrl_p3_point_u;
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RK_S32 color_ctrl_p3_point_v;
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RK_S32 color_ctrl_p3_roll_tab[16];
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RK_S32 tex_adj_enable;
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RK_S32 tex_adj_y_mode_select;
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RK_S32 tex_adj_mode_select;
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RK_S32 tex_adj_grd[6];
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RK_S32 tex_adj_val[6];
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} ShpParams;
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typedef struct EsParams_t {
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RK_U32 es_bEnabledES;
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RK_U32 es_iAngleDelta;
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RK_U32 es_iAngleDeltaExtra;
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RK_U32 es_iGradNoDirTh;
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RK_U32 es_iGradFlatTh;
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RK_U32 es_iWgtGain;
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RK_U32 es_iWgtDecay;
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RK_U32 es_iLowConfTh;
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RK_U32 es_iLowConfRatio;
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RK_U32 es_iConfCntTh;
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RK_U32 es_iWgtLocalTh;
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RK_U32 es_iK1;
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RK_U32 es_iK2;
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RK_U32 es_iDeltaLimit;
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RK_U32 es_iDiff2conf_lut_x[9];
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RK_U32 es_iDiff2conf_lut_y[9];
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RK_U32 es_bEndpointCheckEnable;
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RK_U32 es_tan_hi_th;
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RK_U32 es_tan_lo_th;
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} EsParams;
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struct vdpp2_params {
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RK_U32 src_fmt;
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RK_U32 src_yuv_swap;
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RK_U32 dst_fmt;
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RK_U32 dst_yuv_swap;
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RK_U32 src_width;
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RK_U32 src_height;
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RK_U32 src_width_vir;
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RK_U32 src_height_vir;
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RK_U32 dst_width;
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RK_U32 dst_height;
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RK_U32 dst_width_vir;
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RK_U32 dst_height_vir;
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RK_U32 yuv_out_diff;
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RK_U32 dst_c_width;
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RK_U32 dst_c_height;
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RK_U32 dst_c_width_vir;
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RK_U32 dst_c_height_vir;
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RK_U32 working_mode; // 2 - VDPP, 3 - DCI HIST
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struct vdpp_addr src; // src frame
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struct vdpp_addr dst; // dst frame
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struct vdpp_addr dst_c; // dst chroma
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RK_S32 hist; // dci hist fd
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struct dmsr_params dmsr_params;
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struct zme_params zme_params;
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/* vdpp2 new feature */
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EsParams es_params;
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ShpParams shp_params;
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RK_U32 hist_cnt_en;
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RK_U32 dci_hsd_mode;
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RK_U32 dci_vsd_mode;
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RK_U32 dci_yrgb_gather_num;
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RK_U32 dci_yrgb_gather_en;
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RK_S32 dci_format;
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RK_S32 dci_alpha_swap;
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RK_S32 dci_rbuv_swap;
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RK_S32 dci_csc_range;
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};
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struct vdpp2_api_ctx {
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RK_S32 fd;
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struct vdpp2_params params;
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struct vdpp2_reg reg;
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struct dmsr_reg dmsr;
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struct zme_reg zme;
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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MPP_RET vdpp2_init(VdppCtx *ictx);
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MPP_RET vdpp2_deinit(VdppCtx ictx);
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MPP_RET vdpp2_control(VdppCtx ictx, VdppCmd cmd, void *iparam);
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RK_S32 vdpp2_check_cap(VdppCtx ictx);
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#ifdef __cplusplus
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}
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#endif
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#endif
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