starred/mpp-nyanmisaka
1
0
Fork 0
mirror of https://github.com/nyanmisaka/mpp.git synced 2026-01-24 02:50:38 +01:00
Code Issues Projects Packages Wiki Activity Actions

refactor[av1d]: Use the common alignment function

Browse source 
Platform: General
Spec: av1

Change-Id: I6d94433d18ef1ed1581330e67c9ef14e29db481b
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
This commit is contained in:
Hongjin Li 2025-12-17 10:44:08 +08:00
parent b48f1326e9
commit f29a4fac4a
3 changed files with 8 additions and 48 deletions
Download patch file Download diff file Expand all files Collapse all files

7
mpp/codec/dec/av1/av1d_parser.c
View file

@ -740,11 +740,6 @@ static MPP_RET update_reference_list(Av1CodecContext *ctx)
return ret;
}
static RK_U32 hor_align_16(RK_U32 val)
{
return MPP_ALIGN(val, 16);
}
static MPP_RET get_current_frame(Av1CodecContext *ctx)
{
AV1Context *s = ctx->priv_data;
@ -786,7 +781,7 @@ static MPP_RET get_current_frame(Av1CodecContext *ctx)
if (MPP_FRAME_FMT_IS_FBC(s->cfg->base.out_fmt)) {
RK_U32 fbc_hdr_stride = MPP_ALIGN(ctx->width, 64);
mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, hor_align_16);
mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, mpp_align_16);
if (s->bit_depth == 10) {
if ((ctx->pix_fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV420SP ||
(ctx->pix_fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV420SP_10BIT)

21
mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c
View file

@ -237,21 +237,6 @@ static MPP_RET dump_reg(RK_U32 *reg_s, RK_U32 count, RK_U32 log_start_idx)
}
#endif
static RK_U32 rkv_ver_align(RK_U32 val)
{
return MPP_ALIGN(val, 8);
}
static RK_U32 rkv_len_align(RK_U32 val)
{
return (2 * MPP_ALIGN(val, 128));
}
static RK_U32 rkv_len_align_422(RK_U32 val)
{
return ((5 * MPP_ALIGN(val, 64)) / 2);
}
static MPP_RET vdpu383_setup_scale_origin_bufs(Av1dHalCtx *p_hal, MppFrame mframe)
{
Vdpu38xAv1dRegCtx *ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx;
@ -373,8 +358,8 @@ MPP_RET vdpu383_av1d_init(void *hal, MppHalCfg *cfg)
FUN_CHECK(hal_av1d_alloc_res(hal));
mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, rkv_ver_align);
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align);
mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, mpp_align_8);
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, mpp_align_wxh2yuv422);
__RETURN:
return MPP_OK;
@ -1664,7 +1649,7 @@ MPP_RET vdpu383_av1d_control(void *hal, MpiCmd cmd_type, void *param)
AV1D_DBG(AV1D_DBG_LOG, "control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight);
if ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV422SP) {
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, mpp_align_wxh2yuv422);
}
if (MPP_FRAME_FMT_IS_FBC(fmt)) {
vdpu383_afbc_align_calc(p_hal->slots, (MppFrame)param, 16);

28
mpp/hal/vpu/av1d/hal_av1d_vdpu.c
View file

@ -108,26 +108,6 @@ typedef struct VdpuAv1dRegCtx_t {
RK_U32 num_tile_cols;
} VdpuAv1dRegCtx;
static RK_U32 rkv_ver_align(RK_U32 val)
{
return MPP_ALIGN(val, 8);
}
static RK_U32 rkv_hor_align(RK_U32 val)
{
return MPP_ALIGN(val, 16);
}
static RK_U32 rkv_len_align(RK_U32 val)
{
return (2 * MPP_ALIGN(val, 128));
}
static RK_U32 rkv_len_align_422(RK_U32 val)
{
return ((5 * MPP_ALIGN(val, 64)) / 2);
}
static MPP_RET hal_av1d_alloc_res(void *hal)
{
MPP_RET ret = MPP_OK;
@ -274,9 +254,9 @@ MPP_RET vdpu_av1d_init(void *hal, MppHalCfg *cfg)
reg_ctx->tile_transpose = 1;
}
mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, rkv_hor_align);
mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, rkv_ver_align);
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align);
mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_16);
mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, mpp_align_8);
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, mpp_align_wxh2yuv422);
(void)cfg;
__RETURN:
@ -2398,7 +2378,7 @@ MPP_RET vdpu_av1d_control(void *hal, MpiCmd cmd_type, void *param)
AV1D_DBG(AV1D_DBG_LOG, "control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight);
if ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV422SP) {
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, mpp_align_wxh2yuv422);
}
break;
}