diff --git a/inc/rk_venc_cmd.h b/inc/rk_venc_cmd.h
index b4000e01..89821ef4 100644
--- a/inc/rk_venc_cmd.h
+++ b/inc/rk_venc_cmd.h
@@ -941,7 +941,9 @@ typedef enum MppEncH265CfgChange_e {
     MPP_ENC_H265_CFG_RC_I_QP_CHANGE             = (1 << 19),
     MPP_ENC_H265_CFG_RC_MAX_QP_STEP_CHANGE      = (1 << 21),
     MPP_ENC_H265_CFG_RC_IP_DELTA_QP_CHANGE      = (1 << 20),
-    MPP_ENC_H265_CFG_TITLE_CHANGE               = (1 << 22),
+    MPP_ENC_H265_CFG_TILE_CHANGE                = (1 << 22),
+    MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE        = (1 << 23),
+    MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE         = (1 << 24),
     MPP_ENC_H265_CFG_CHANGE_ALL                 = (0xFFFFFFFF),
 } MppEncH265CfgChange;
 
@@ -958,7 +960,6 @@ typedef struct MppEncH265SliceCfg_t {
      */
     RK_U32  slice_size;
     RK_U32  slice_out;
-    RK_U32  loop_filter_across_slices_enabled_flag;
 } MppEncH265SliceCfg;
 
 typedef struct MppEncH265CuCfg_t {
@@ -1063,6 +1064,8 @@ typedef struct MppEncH265Cfg_t {
     MppEncH265RefCfg     ref_cfg;
     MppEncH265MergesCfg  merge_cfg;
     RK_S32               auto_tile;
+    RK_U32               lpf_acs_sli_en;
+    RK_U32               lpf_acs_tile_disable;
 
     /* extra info */
     MppEncH265VuiCfg    vui;
diff --git a/mpp/base/mpp_enc_cfg.cpp b/mpp/base/mpp_enc_cfg.cpp
index 7e839dc1..480446dc 100644
--- a/mpp/base/mpp_enc_cfg.cpp
+++ b/mpp/base/mpp_enc_cfg.cpp
@@ -226,7 +226,9 @@ public:
     ENTRY(h265, qp_delta_ip,    S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_IP,            rc, qp_delta_ip) \
     ENTRY(h265, sao_luma_disable,   S32, RK_S32,        MPP_ENC_H265_CFG_SAO_CHANGE,            codec.h265, sao_cfg.slice_sao_luma_disable) \
     ENTRY(h265, sao_chroma_disable, S32, RK_S32,        MPP_ENC_H265_CFG_SAO_CHANGE,            codec.h265, sao_cfg.slice_sao_chroma_disable) \
-    ENTRY(h265, auto_tile,      S32, RK_S32,            MPP_ENC_H265_CFG_TITLE_CHANGE,          codec.h265, auto_tile) \
+    ENTRY(h265, lpf_acs_sli_en, U32, RK_U32,            MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE,   codec.h265, lpf_acs_sli_en) \
+    ENTRY(h265, lpf_acs_tile_disable, U32, RK_U32,      MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE,    codec.h265, lpf_acs_tile_disable) \
+    ENTRY(h265, auto_tile,      S32, RK_S32,            MPP_ENC_H265_CFG_TILE_CHANGE,           codec.h265, auto_tile) \
     /* vp8 config */ \
     ENTRY(vp8,  qp_init,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_INIT,          rc, qp_init) \
     ENTRY(vp8,  qp_min,         S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_min) \
diff --git a/mpp/codec/enc/h265/h265e_api.c b/mpp/codec/enc/h265/h265e_api.c
index d480f8f5..3e82ddad 100644
--- a/mpp/codec/enc/h265/h265e_api.c
+++ b/mpp/codec/enc/h265/h265e_api.c
@@ -480,9 +480,15 @@ static MPP_RET h265e_proc_h265_cfg(MppEncH265Cfg *dst, MppEncH265Cfg *src)
         memcpy(&dst->sao_cfg, &src->sao_cfg, sizeof(src->sao_cfg));
     }
 
-    if (change & MPP_ENC_H265_CFG_TITLE_CHANGE)
+    if (change & MPP_ENC_H265_CFG_TILE_CHANGE)
         dst->auto_tile = src->auto_tile;
 
+    if (change & MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE)
+        dst->lpf_acs_sli_en = src->lpf_acs_sli_en;
+
+    if (change & MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE)
+        dst->lpf_acs_tile_disable = src->lpf_acs_tile_disable;
+
     /*
      * NOTE: use OR here for avoiding overwrite on multiple config
      * When next encoding is trigger the change flag will be clear
diff --git a/mpp/codec/enc/h265/h265e_ps.c b/mpp/codec/enc/h265/h265e_ps.c
index c696bd7d..b6248de0 100644
--- a/mpp/codec/enc/h265/h265e_ps.c
+++ b/mpp/codec/enc/h265/h265e_ps.c
@@ -399,7 +399,7 @@ MPP_RET h265e_set_pps(H265eCtx  *ctx, H265ePps *pps, H265eSps *sps)
     pps->m_outputFlagPresentFlag = 0;
     pps->m_signHideFlag = 0;
     pps->m_picInitQPMinus26 = codec->intra_qp - 26;
-    pps->m_LFCrossSliceBoundaryFlag = codec->slice_cfg.loop_filter_across_slices_enabled_flag;
+    pps->m_LFCrossSliceBoundaryFlag = codec->lpf_acs_sli_en;
     pps->m_deblockingFilterControlPresentFlag = !codec->dblk_cfg.slice_deblocking_filter_disabled_flag;
     if (pps->m_deblockingFilterControlPresentFlag) {
         pps->m_deblockingFilterOverrideEnabledFlag = 0;
@@ -432,7 +432,7 @@ MPP_RET h265e_set_pps(H265eCtx  *ctx, H265ePps *pps, H265eSps *sps)
     pps->m_bTileUniformSpacing = 0;
     pps->m_nNumTileRowsMinus1 = 0;
     pps->m_nNumTileColumnsMinus1 = 0;
-    pps->m_loopFilterAcrossTilesEnabledFlag = 1;
+    pps->m_loopFilterAcrossTilesEnabledFlag = !codec->lpf_acs_tile_disable;
     {
         const char *soc_name = mpp_get_soc_name();
         /* check tile support on rk3566 and rk3568 */
@@ -453,7 +453,7 @@ MPP_RET h265e_set_pps(H265eCtx  *ctx, H265ePps *pps, H265eSps *sps)
         if (pps->m_nNumTileColumnsMinus1) {
             pps->m_tiles_enabled_flag = 1;
             pps->m_bTileUniformSpacing = 1;
-            pps->m_loopFilterAcrossTilesEnabledFlag = 1;
+            pps->m_loopFilterAcrossTilesEnabledFlag = !codec->lpf_acs_tile_disable;;
         }
     }