From aaa4c8e9a8d8a024f192bead2c45615173378e8c Mon Sep 17 00:00:00 2001 From: Chandler Chen Date: Tue, 29 Oct 2024 16:44:45 +0800 Subject: [PATCH] fix[hal_vdpu383]: fix fbc hor_stride mismatch issue Signed-off-by: Chandler Chen Change-Id: I32ba0ace912179d875f2e474a0ef673b9bd74b65 --- mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c | 8 ++++---- mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c | 4 ++-- mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c | 6 +++--- mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c | 6 +++--- mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c | 11 +++++++---- 5 files changed, 19 insertions(+), 16 deletions(-) diff --git a/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c b/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c index 4978cf2a..4b7a3be1 100644 --- a/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c +++ b/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c @@ -2313,11 +2313,11 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task) if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) { RK_U32 fbd_offset; - RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64); - RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 8); + RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); + RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64); regs->ctrl_regs.reg9.fbc_e = 1; - regs->av1d_paras.reg68_hor_virstride = w / 64; + regs->av1d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; fbd_offset = regs->av1d_paras.reg68_hor_virstride * h * 4; regs->av1d_addrs.reg193_fbc_payload_offset = fbd_offset; } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) { @@ -2345,7 +2345,7 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task) ver_virstride = mpp_frame_get_ver_stride(mframe); y_virstride = hor_virstride * ver_virstride; if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) { - hor_virstride = MPP_ALIGN(mpp_frame_get_width(mframe), 64) / 4; + hor_virstride = mpp_frame_get_fbc_hdr_stride(mframe) / 4; } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) { hor_virstride = MPP_ALIGN(hor_virstride * 6, 16); y_virstride += y_virstride / 2; diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c index 30014b17..7738568d 100644 --- a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c +++ b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c @@ -380,11 +380,11 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu383Avs2dRegSet *regs, Ha is_fbc, y_virstride, hor_virstride, ver_virstride); if (is_fbc) { - RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64); + RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); RK_U32 fbd_offset; regs->ctrl_regs.reg9.fbc_e = 1; - regs->avs2d_paras.reg68_hor_virstride = pixel_width / 64; + regs->avs2d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; fbd_offset = regs->avs2d_paras.reg68_hor_virstride * MPP_ALIGN(ver_virstride, 64) * 4; regs->avs2d_addrs.reg193_fbc_payload_offset = fbd_offset; } else if (is_tile) { diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c index 478cf209..56675c4b 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c @@ -437,13 +437,13 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu383H264dRegSet *regs, Hal uv_virstride = hor_virstride * ver_virstride / 2; if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) { - RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64); + RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); RK_U32 fbd_offset; - fbd_offset = pixel_width * MPP_ALIGN(ver_virstride, 64) / 16; + fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; regs->ctrl_regs.reg9.fbc_e = 1; - regs->h264d_paras.reg68_hor_virstride = pixel_width / 64; + regs->h264d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; regs->h264d_addrs.reg193_fbc_payload_offset = fbd_offset; } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) { regs->ctrl_regs.reg9.tile_e = 1; diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c index ee18faaf..a6702c05 100644 --- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c +++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c @@ -985,12 +985,12 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal, HalTaskInfo *syn) virstrid_uv = stride_uv * ver_virstride / 2; } if (MPP_FRAME_FMT_IS_FBC(fmt)) { - RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64); + RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); RK_U32 fbd_offset; hw_regs->ctrl_regs.reg9.fbc_e = 1; - hw_regs->h265d_paras.reg68_hor_virstride = pixel_width / 64; - fbd_offset = pixel_width * MPP_ALIGN(ver_virstride, 64) / 16; + hw_regs->h265d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; + fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; hw_regs->h265d_addrs.reg193_fbc_payload_offset = fbd_offset; } else if (MPP_FRAME_FMT_IS_TILE(fmt)) { hw_regs->ctrl_regs.reg9.tile_e = 1; diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c index b400e59e..2091506a 100644 --- a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c +++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c @@ -13,6 +13,7 @@ #include "mpp_common.h" #include "mpp_buffer_impl.h" #include "mpp_bitput.h" +#include "mpp_compat_impl.h" #include "hal_vp9d_debug.h" #include "hal_vp9d_com.h" @@ -850,16 +851,16 @@ static MPP_RET hal_vp9d_vdpu383_gen_regs(void *hal, HalTaskInfo *task) fbc_en = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe)); if (fbc_en) { - RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64); - RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 8); + RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe); + RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64); RK_U32 fbd_offset; vp9_hw_regs->ctrl_regs.reg9.fbc_e = 1; - vp9_hw_regs->vp9d_paras.reg68_hor_virstride = w / 64; + vp9_hw_regs->vp9d_paras.reg68_hor_virstride = fbc_hdr_stride / 64; fbd_offset = vp9_hw_regs->vp9d_paras.reg68_hor_virstride * h * 4; vp9_hw_regs->vp9d_addrs.reg193_fbc_payload_offset = fbd_offset; /* error stride */ - vp9_hw_regs->vp9d_paras.reg80_error_ref_hor_virstride = w / 64; + vp9_hw_regs->vp9d_paras.reg80_error_ref_hor_virstride = fbc_hdr_stride / 64; } else { sw_y_hor_virstride = (mpp_align_128_odd_plus_64((pic_param->width * bit_depth) >> 3) >> 4); sw_uv_hor_virstride = (mpp_align_128_odd_plus_64((pic_param->width * bit_depth) >> 3) >> 4); @@ -953,6 +954,8 @@ static MPP_RET hal_vp9d_vdpu383_gen_regs(void *hal, HalTaskInfo *task) pic_h[1] = vp9_ver_align(ref_frame_height_y) / 2; if (fbc_en) { y_hor_virstride = uv_hor_virstride = MPP_ALIGN(ref_frame_width_y, 64) / 64; + if (*compat_ext_fbc_hdr_256_odd) + y_hor_virstride = uv_hor_virstride = (MPP_ALIGN(ref_frame_width_y, 256) | 256) / 64; } else { y_hor_virstride = uv_hor_virstride = (mpp_align_128_odd_plus_64((ref_frame_width_y * bit_depth) >> 3) >> 4); }