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fix[vepu541]: Add warning for unsupport nv21/nv42

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VEPU_541 unsupport uv_swap in nv12/nv24.

Change-Id: I768b9a5fc5657a8d8eb58feeb0f09756a6197c3e
Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
This commit is contained in:
Yanjun Liao 2025-05-09 15:22:39 +08:00
parent 1483344ec3
commit 6d3cc5ea5d
2 changed files with 15 additions and 6 deletions
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8
mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
View file

@ -445,10 +445,11 @@ static void setup_vepu541_normal(Vepu541H264eRegSet *regs, RK_U32 is_vepu540)
hal_h264e_dbg_func("leave\n");
}
static MPP_RET setup_vepu541_prep(Vepu541H264eRegSet *regs, MppEncPrepCfg *prep,
static MPP_RET setup_vepu541_prep(Vepu541H264eRegSet *regs, HalH264eVepu541Ctx *ctx,
HalEncTask *task)
{
VepuFmtCfg cfg;
MppEncPrepCfg *prep = &ctx->cfg->prep;
MppFrameFormat fmt = prep->format;
MPP_RET ret = vepu541_set_fmt(&cfg, fmt);
RK_U32 hw_fmt = cfg.format;
@ -477,6 +478,9 @@ static MPP_RET setup_vepu541_prep(Vepu541H264eRegSet *regs, MppEncPrepCfg *prep,
regs->reg017.src_range = cfg.src_range;
regs->reg017.out_fmt_cfg = (fmt == MPP_FMT_YUV400) ? 1 : 0;
if (!ctx->frame_cnt && (fmt == MPP_FMT_YUV420SP_VU || fmt == MPP_FMT_YUV422SP_VU))
mpp_logw("Warning: nv21/nv42 fmt not supported, will encode as nv12/nv24.\n");
if (MPP_FRAME_FMT_IS_FBC(fmt)) {
y_stride = mpp_frame_get_fbc_hdr_stride(task->frame);
if (!y_stride)
@ -1602,7 +1606,7 @@ static MPP_RET hal_h264e_vepu541_gen_regs(void *hal, HalEncTask *task)
memset(regs, 0, sizeof(*regs));
setup_vepu541_normal(regs, ctx->is_vepu540);
ret = setup_vepu541_prep(regs, &ctx->cfg->prep, task);
ret = setup_vepu541_prep(regs, ctx, task);
if (ret)
return ret;

13
mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
View file

@ -1060,11 +1060,13 @@ static MPP_RET vepu541_h265_set_rc_regs(H265eV541HalContext *ctx, H265eV541RegSe
return MPP_OK;
}
static MPP_RET vepu541_h265_set_pp_regs(H265eV541RegSet *regs, VepuFmtCfg *fmt,
MppEncPrepCfg *prep_cfg, HalEncTask *task)
static MPP_RET vepu541_h265_set_pp_regs(VepuFmtCfg *fmt, H265eV541HalContext *ctx, HalEncTask *task)
{
RK_S32 stridey = 0;
RK_S32 stridec = 0;
H265eV541RegSet *regs = ctx->regs;
MppEncPrepCfg *prep_cfg = &ctx->cfg->prep;
MppFrameFormat prep_fmt = prep_cfg->format;
regs->dtrns_map.src_bus_edin = fmt->src_endian;
regs->src_fmt.src_cfmt = fmt->format;
@ -1074,7 +1076,10 @@ static MPP_RET vepu541_h265_set_pp_regs(H265eV541RegSet *regs, VepuFmtCfg *fmt,
regs->src_proc.src_mirr = prep_cfg->mirroring > 0;
regs->src_proc.src_rot = prep_cfg->rotation;
if (MPP_FRAME_FMT_IS_FBC(prep_cfg->format)) {
if (!ctx->frame_num && (prep_fmt == MPP_FMT_YUV420SP_VU || prep_fmt == MPP_FMT_YUV422SP_VU))
mpp_logw("Warning: nv21/nv42 fmt not supported, will encode as nv12/nv24.\n");
if (MPP_FRAME_FMT_IS_FBC(prep_fmt)) {
stridey = mpp_frame_get_fbc_hdr_stride(task->frame);
if (!stridey)
stridey = MPP_ALIGN(prep_cfg->hor_stride, 16);
@ -1621,7 +1626,7 @@ MPP_RET hal_h265e_v541_gen_regs(void *hal, HalEncTask *task)
regs->synt_nal.nal_unit_type = syn->sp.temporal_id ? NAL_TSA_R : i_nal_type;
}
vepu54x_h265_set_hw_address(ctx, regs, task);
vepu541_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep, task);
vepu541_h265_set_pp_regs(fmt, ctx, task);
vepu541_h265_set_rc_regs(ctx, regs, task);