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fix[mpp_frame]: Add rk_fbc fmt for 1126b
Change-Id: I357efd122b1bdf3345ca887130d837ebf7cb5afa Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
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2 changed files with 11 additions and 1 deletions
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@ -214,6 +214,14 @@ typedef enum {
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*/
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*/
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#define MPP_FRAME_FBC_AFBC_V2 (0x00200000)
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#define MPP_FRAME_FBC_AFBC_V2 (0x00200000)
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/*
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* RKFBC is for video decoder output and video encoder Input.
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* It has default header stride to be calculated * from width and height:
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* Header stride = MPP_ALIGN(width, 64) / 64 * 16
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* Payload offset is always set to zero.
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*/
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#define MPP_FRAME_FBC_RKFBC (0x00400000)
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#define MPP_FRAME_FMT_LE_MASK (0x01000000)
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#define MPP_FRAME_FMT_LE_MASK (0x01000000)
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#define MPP_FRAME_FMT_IS_YUV(fmt) (((fmt & MPP_FRAME_FMT_COLOR_MASK) == MPP_FRAME_FMT_YUV) && \
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#define MPP_FRAME_FMT_IS_YUV(fmt) (((fmt & MPP_FRAME_FMT_COLOR_MASK) == MPP_FRAME_FMT_YUV) && \
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@ -228,6 +236,7 @@ typedef enum {
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* For MPP_FRAME_FBC_AFBC_V1 the 16byte aligned stride is used.
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* For MPP_FRAME_FBC_AFBC_V1 the 16byte aligned stride is used.
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*/
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*/
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#define MPP_FRAME_FMT_IS_FBC(fmt) (fmt & MPP_FRAME_FBC_MASK)
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#define MPP_FRAME_FMT_IS_FBC(fmt) (fmt & MPP_FRAME_FBC_MASK)
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#define MPP_FRAME_FMT_IS_RKFBC(fmt) (fmt & MPP_FRAME_FBC_RKFBC)
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#define MPP_FRAME_FMT_IS_HDR(fmt) (fmt & MPP_FRAME_HDR_MASK)
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#define MPP_FRAME_FMT_IS_HDR(fmt) (fmt & MPP_FRAME_HDR_MASK)
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@ -246,7 +246,8 @@ RK_U32 mpp_frame_get_fbc_offset(MppFrame frame)
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if (fbc_version == MPP_FRAME_FBC_AFBC_V1) {
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if (fbc_version == MPP_FRAME_FBC_AFBC_V1) {
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fbc_offset = MPP_ALIGN(MPP_ALIGN(p->width, 16) *
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fbc_offset = MPP_ALIGN(MPP_ALIGN(p->width, 16) *
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MPP_ALIGN(p->height, 16) / 16, SZ_4K);
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MPP_ALIGN(p->height, 16) / 16, SZ_4K);
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} else if (fbc_version == MPP_FRAME_FBC_AFBC_V2) {
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} else if (fbc_version == MPP_FRAME_FBC_AFBC_V2 ||
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fbc_version == MPP_FRAME_FBC_RKFBC) {
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fbc_offset = 0;
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fbc_offset = 0;
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}
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}
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p->fbc_offset = fbc_offset;
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p->fbc_offset = fbc_offset;
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