starred/mpp-nyanmisaka
1
0
Fork 0
mirror of https://github.com/nyanmisaka/mpp.git synced 2026-01-24 01:20:40 +01:00
Code Issues Projects Packages Wiki Activity Actions

fix[h264_vdpu384a]: Fix error proc issue

Browse source 
Platform: RV1126B
Spec: h265/h264/avs2/vp9/av1

Change-Id: If82b2595160a739a3c9275382e754d7931ace45b
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
This commit is contained in:
Hongjin Li 2025-04-10 20:06:32 +08:00 • committed by Herman Chen
parent c5190676f4
commit 257ee8ab51
1 changed files with 5 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

5
mpp/hal/rkdec/h264d/hal_h264d_vdpu384a.c
View file

@ -384,6 +384,7 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu384aH264dRegSet *regs, Ha
regs->h264d_paras.reg68_dpb_hor_virstride = fbc_hdr_stride / 64;
regs->h264d_addrs.reg193_dpb_fbc64x4_payload_offset = fbd_offset;
regs->h264d_paras.reg80_error_ref_hor_virstride = regs->h264d_paras.reg68_dpb_hor_virstride;
} else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
regs->ctrl_regs.reg9.dpb_data_sel = 1;
regs->ctrl_regs.reg9.dpb_output_dis = 1;
@ -391,6 +392,7 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu384aH264dRegSet *regs, Ha
regs->h264d_paras.reg77_pp_m_hor_stride = hor_virstride * 6 / 16;
regs->h264d_paras.reg79_pp_m_y_virstride = (y_virstride + uv_virstride) / 16;
regs->h264d_paras.reg80_error_ref_hor_virstride = regs->h264d_paras.reg77_pp_m_hor_stride;
} else {
regs->ctrl_regs.reg9.dpb_data_sel = 1;
regs->ctrl_regs.reg9.dpb_output_dis = 1;
@ -399,7 +401,10 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu384aH264dRegSet *regs, Ha
regs->h264d_paras.reg77_pp_m_hor_stride = hor_virstride / 16;
regs->h264d_paras.reg78_pp_m_uv_hor_stride = hor_virstride / 16;
regs->h264d_paras.reg79_pp_m_y_virstride = y_virstride / 16;
regs->h264d_paras.reg80_error_ref_hor_virstride = regs->h264d_paras.reg77_pp_m_hor_stride;
}
regs->h264d_paras.reg81_error_ref_raster_uv_hor_virstride = regs->h264d_paras.reg78_pp_m_uv_hor_stride;
regs->h264d_paras.reg82_error_ref_virstride = regs->h264d_paras.reg79_pp_m_y_virstride;
}
//!< set current
{