refactor[hal_h265d]: Collect ctx into common

Platform: General
Spec: h265

Change-Id: If0ec8c6c8e80f407cb2c00df0e486b17dfdd1866
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
This commit is contained in:
Hongjin Li 2025-12-16 17:42:47 +08:00 committed by Herman Chen
parent 6e9223830f
commit 1048a30a5e
6 changed files with 23 additions and 23 deletions

View file

@ -9,8 +9,8 @@
#include "mpp_device.h"
#include "mpp_hal.h"
#include "hal_bufs.h"
#include "vdpu_com.h"
#define MAX_GEN_REG 3
/* before vdpu383 10 buf */
#define H265D_RCB_BUF_COUNT 11
@ -51,10 +51,10 @@ typedef struct HalH265dCtx_t {
RK_S32 height;
RK_S32 rcb_buf_size;
H265dRcbInfo rcb_info[H265D_RCB_BUF_COUNT];
MppBuffer rcb_buf[MAX_GEN_REG];
MppBuffer rcb_buf[VDPU_FAST_REG_SET_CNT];
void* hw_regs;
H265dRegBuf g_buf[MAX_GEN_REG];
H265dRegBuf g_buf[VDPU_FAST_REG_SET_CNT];
RK_U32 fast_mode;
MppCbCtx *dec_cb;
RK_U32 fast_mode_err_found;
@ -76,14 +76,14 @@ typedef struct HalH265dCtx_t {
RK_U8 ctu_size;
RK_U8 num_row_tiles;
RK_U8 bit_depth;
RK_U8 error_index[MAX_GEN_REG];
RK_U8 error_index[VDPU_FAST_REG_SET_CNT];
/* for vdpu34x */
MppBuffer bufs;
RK_S32 bufs_fd;
RK_U32 offset_cabac;
RK_U32 offset_spspps[MAX_GEN_REG];
RK_U32 offset_rps[MAX_GEN_REG];
RK_U32 offset_sclst[MAX_GEN_REG];
RK_U32 offset_spspps[VDPU_FAST_REG_SET_CNT];
RK_U32 offset_rps[VDPU_FAST_REG_SET_CNT];
RK_U32 offset_sclst[VDPU_FAST_REG_SET_CNT];
RK_U32 spspps_offset;
RK_U32 rps_offset;
RK_U32 sclst_offset;

View file

@ -44,7 +44,7 @@ static MPP_RET hal_h265d_alloc_res(void *hal)
RK_S32 ret = 0;
HalH265dCtx *reg_ctx = (HalH265dCtx *)hal;
if (reg_ctx->fast_mode) {
for (i = 0; i < MAX_GEN_REG; i++) {
for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
reg_ctx->g_buf[i].hw_regs =
mpp_calloc_size(void, sizeof(H265d_REGS_t));
ret = mpp_buffer_get(reg_ctx->group,
@ -100,7 +100,7 @@ static MPP_RET hal_h265d_release_res(void *hal)
HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal;
RK_S32 i = 0;
if (reg_ctx->fast_mode) {
for (i = 0; i < MAX_GEN_REG; i++) {
for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
if (reg_ctx->g_buf[i].scaling_list_data) {
ret = mpp_buffer_put(reg_ctx->g_buf[i].scaling_list_data);
if (ret) {
@ -750,7 +750,7 @@ MPP_RET hal_h265d_rkv_gen_regs(void *hal, HalTaskInfo *syn)
void *rps_ptr = NULL;
if (reg_ctx ->fast_mode) {
for (i = 0; i < MAX_GEN_REG; i++) {
for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
if (!reg_ctx->g_buf[i].use_flag) {
syn->dec.reg_index = i;
reg_ctx->rps_data = reg_ctx->g_buf[i].rps_data;
@ -762,7 +762,7 @@ MPP_RET hal_h265d_rkv_gen_regs(void *hal, HalTaskInfo *syn)
break;
}
}
if (i == MAX_GEN_REG) {
if (i == VDPU_FAST_REG_SET_CNT) {
mpp_err("hevc rps buf all used");
return MPP_ERR_NOMEM;
}

View file

@ -130,7 +130,7 @@ static MPP_RET hal_h265d_vdpu34x_init(void *hal, MppHalCfg *cfg)
{
RK_U32 i = 0;
RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1;
RK_U32 max_cnt = reg_ctx->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;
//!< malloc buffers
ret = mpp_buffer_get(reg_ctx->group, &reg_ctx->bufs, ALL_BUFFER_SIZE(max_cnt));
@ -868,7 +868,7 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
}
if (reg_ctx ->fast_mode) {
for (i = 0; i < MAX_GEN_REG; i++) {
for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
if (!reg_ctx->g_buf[i].use_flag) {
syn->dec.reg_index = i;
@ -881,7 +881,7 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
break;
}
}
if (i == MAX_GEN_REG) {
if (i == VDPU_FAST_REG_SET_CNT) {
mpp_err("hevc rps buf all used");
return MPP_ERR_NOMEM;
}

View file

@ -128,7 +128,7 @@ static MPP_RET hal_h265d_vdpu382_init(void *hal, MppHalCfg *cfg)
{
RK_U32 i = 0;
RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1;
RK_U32 max_cnt = reg_ctx->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;
//!< malloc buffers
ret = mpp_buffer_get(reg_ctx->group, &reg_ctx->bufs, ALL_BUFFER_SIZE(max_cnt));
@ -674,7 +674,7 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal, HalTaskInfo *syn)
}
if (reg_ctx ->fast_mode) {
for (i = 0; i < MAX_GEN_REG; i++) {
for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
if (!reg_ctx->g_buf[i].use_flag) {
syn->dec.reg_index = i;
@ -687,7 +687,7 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal, HalTaskInfo *syn)
break;
}
}
if (i == MAX_GEN_REG) {
if (i == VDPU_FAST_REG_SET_CNT) {
mpp_err("hevc rps buf all used");
return MPP_ERR_NOMEM;
}

View file

@ -140,7 +140,7 @@ static MPP_RET hal_h265d_vdpu383_init(void *hal, MppHalCfg *cfg)
{
RK_U32 i = 0;
RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1;
RK_U32 max_cnt = reg_ctx->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;
//!< malloc buffers
ret = mpp_buffer_get(reg_ctx->group, &reg_ctx->bufs, ALL_BUFFER_SIZE(max_cnt));
@ -884,7 +884,7 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal, HalTaskInfo *syn)
void *rps_ptr = NULL;
if (reg_ctx ->fast_mode) {
for (i = 0; i < MAX_GEN_REG; i++) {
for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
if (!reg_ctx->g_buf[i].use_flag) {
syn->dec.reg_index = i;
@ -897,7 +897,7 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal, HalTaskInfo *syn)
break;
}
}
if (i == MAX_GEN_REG) {
if (i == VDPU_FAST_REG_SET_CNT) {
mpp_err("hevc rps buf all used");
return MPP_ERR_NOMEM;
}

View file

@ -118,7 +118,7 @@ static MPP_RET hal_h265d_vdpu384a_init(void *hal, MppHalCfg *cfg)
{
RK_U32 i = 0;
RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1;
RK_U32 max_cnt = reg_ctx->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;
//!< malloc buffers
ret = mpp_buffer_get(reg_ctx->group, &reg_ctx->bufs, ALL_BUFFER_SIZE(max_cnt));
@ -804,7 +804,7 @@ static MPP_RET hal_h265d_vdpu384a_gen_regs(void *hal, HalTaskInfo *syn)
HalBuf *origin_buf = NULL;
if (reg_ctx ->fast_mode) {
for (i = 0; i < MAX_GEN_REG; i++) {
for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
if (!reg_ctx->g_buf[i].use_flag) {
syn->dec.reg_index = i;
@ -816,7 +816,7 @@ static MPP_RET hal_h265d_vdpu384a_gen_regs(void *hal, HalTaskInfo *syn)
break;
}
}
if (i == MAX_GEN_REG) {
if (i == VDPU_FAST_REG_SET_CNT) {
mpp_err("hevc rps buf all used");
return MPP_ERR_NOMEM;
}