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refactor[hal_h265d]: Collect ctx into common
Platform: General Spec: h265 Change-Id: If0ec8c6c8e80f407cb2c00df0e486b17dfdd1866 Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
This commit is contained in:
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6e9223830f
commit
1048a30a5e
6 changed files with 23 additions and 23 deletions
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@ -9,8 +9,8 @@
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#include "mpp_device.h"
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#include "mpp_hal.h"
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#include "hal_bufs.h"
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#include "vdpu_com.h"
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#define MAX_GEN_REG 3
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/* before vdpu383 10 buf */
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#define H265D_RCB_BUF_COUNT 11
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@ -51,10 +51,10 @@ typedef struct HalH265dCtx_t {
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RK_S32 height;
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RK_S32 rcb_buf_size;
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H265dRcbInfo rcb_info[H265D_RCB_BUF_COUNT];
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MppBuffer rcb_buf[MAX_GEN_REG];
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MppBuffer rcb_buf[VDPU_FAST_REG_SET_CNT];
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void* hw_regs;
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H265dRegBuf g_buf[MAX_GEN_REG];
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H265dRegBuf g_buf[VDPU_FAST_REG_SET_CNT];
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RK_U32 fast_mode;
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MppCbCtx *dec_cb;
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RK_U32 fast_mode_err_found;
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@ -76,14 +76,14 @@ typedef struct HalH265dCtx_t {
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RK_U8 ctu_size;
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RK_U8 num_row_tiles;
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RK_U8 bit_depth;
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RK_U8 error_index[MAX_GEN_REG];
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RK_U8 error_index[VDPU_FAST_REG_SET_CNT];
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/* for vdpu34x */
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MppBuffer bufs;
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RK_S32 bufs_fd;
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RK_U32 offset_cabac;
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RK_U32 offset_spspps[MAX_GEN_REG];
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RK_U32 offset_rps[MAX_GEN_REG];
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RK_U32 offset_sclst[MAX_GEN_REG];
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RK_U32 offset_spspps[VDPU_FAST_REG_SET_CNT];
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RK_U32 offset_rps[VDPU_FAST_REG_SET_CNT];
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RK_U32 offset_sclst[VDPU_FAST_REG_SET_CNT];
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RK_U32 spspps_offset;
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RK_U32 rps_offset;
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RK_U32 sclst_offset;
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@ -44,7 +44,7 @@ static MPP_RET hal_h265d_alloc_res(void *hal)
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RK_S32 ret = 0;
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HalH265dCtx *reg_ctx = (HalH265dCtx *)hal;
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if (reg_ctx->fast_mode) {
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for (i = 0; i < MAX_GEN_REG; i++) {
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for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
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reg_ctx->g_buf[i].hw_regs =
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mpp_calloc_size(void, sizeof(H265d_REGS_t));
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ret = mpp_buffer_get(reg_ctx->group,
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@ -100,7 +100,7 @@ static MPP_RET hal_h265d_release_res(void *hal)
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HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal;
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RK_S32 i = 0;
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if (reg_ctx->fast_mode) {
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for (i = 0; i < MAX_GEN_REG; i++) {
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for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
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if (reg_ctx->g_buf[i].scaling_list_data) {
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ret = mpp_buffer_put(reg_ctx->g_buf[i].scaling_list_data);
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if (ret) {
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@ -750,7 +750,7 @@ MPP_RET hal_h265d_rkv_gen_regs(void *hal, HalTaskInfo *syn)
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void *rps_ptr = NULL;
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if (reg_ctx ->fast_mode) {
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for (i = 0; i < MAX_GEN_REG; i++) {
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for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
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if (!reg_ctx->g_buf[i].use_flag) {
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syn->dec.reg_index = i;
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reg_ctx->rps_data = reg_ctx->g_buf[i].rps_data;
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@ -762,7 +762,7 @@ MPP_RET hal_h265d_rkv_gen_regs(void *hal, HalTaskInfo *syn)
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break;
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}
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}
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if (i == MAX_GEN_REG) {
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if (i == VDPU_FAST_REG_SET_CNT) {
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mpp_err("hevc rps buf all used");
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return MPP_ERR_NOMEM;
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}
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@ -130,7 +130,7 @@ static MPP_RET hal_h265d_vdpu34x_init(void *hal, MppHalCfg *cfg)
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{
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RK_U32 i = 0;
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RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1;
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RK_U32 max_cnt = reg_ctx->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;
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//!< malloc buffers
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ret = mpp_buffer_get(reg_ctx->group, ®_ctx->bufs, ALL_BUFFER_SIZE(max_cnt));
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@ -868,7 +868,7 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
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}
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if (reg_ctx ->fast_mode) {
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for (i = 0; i < MAX_GEN_REG; i++) {
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for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
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if (!reg_ctx->g_buf[i].use_flag) {
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syn->dec.reg_index = i;
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@ -881,7 +881,7 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
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break;
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}
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}
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if (i == MAX_GEN_REG) {
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if (i == VDPU_FAST_REG_SET_CNT) {
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mpp_err("hevc rps buf all used");
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return MPP_ERR_NOMEM;
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}
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@ -128,7 +128,7 @@ static MPP_RET hal_h265d_vdpu382_init(void *hal, MppHalCfg *cfg)
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{
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RK_U32 i = 0;
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RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1;
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RK_U32 max_cnt = reg_ctx->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;
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//!< malloc buffers
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ret = mpp_buffer_get(reg_ctx->group, ®_ctx->bufs, ALL_BUFFER_SIZE(max_cnt));
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@ -674,7 +674,7 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal, HalTaskInfo *syn)
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}
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if (reg_ctx ->fast_mode) {
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for (i = 0; i < MAX_GEN_REG; i++) {
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for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
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if (!reg_ctx->g_buf[i].use_flag) {
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syn->dec.reg_index = i;
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@ -687,7 +687,7 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal, HalTaskInfo *syn)
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break;
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}
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}
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if (i == MAX_GEN_REG) {
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if (i == VDPU_FAST_REG_SET_CNT) {
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mpp_err("hevc rps buf all used");
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return MPP_ERR_NOMEM;
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}
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@ -140,7 +140,7 @@ static MPP_RET hal_h265d_vdpu383_init(void *hal, MppHalCfg *cfg)
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{
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RK_U32 i = 0;
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RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1;
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RK_U32 max_cnt = reg_ctx->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;
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//!< malloc buffers
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ret = mpp_buffer_get(reg_ctx->group, ®_ctx->bufs, ALL_BUFFER_SIZE(max_cnt));
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@ -884,7 +884,7 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal, HalTaskInfo *syn)
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void *rps_ptr = NULL;
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if (reg_ctx ->fast_mode) {
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for (i = 0; i < MAX_GEN_REG; i++) {
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for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
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if (!reg_ctx->g_buf[i].use_flag) {
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syn->dec.reg_index = i;
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@ -897,7 +897,7 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal, HalTaskInfo *syn)
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break;
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}
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}
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if (i == MAX_GEN_REG) {
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if (i == VDPU_FAST_REG_SET_CNT) {
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mpp_err("hevc rps buf all used");
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return MPP_ERR_NOMEM;
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}
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@ -118,7 +118,7 @@ static MPP_RET hal_h265d_vdpu384a_init(void *hal, MppHalCfg *cfg)
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{
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RK_U32 i = 0;
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RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1;
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RK_U32 max_cnt = reg_ctx->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;
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//!< malloc buffers
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ret = mpp_buffer_get(reg_ctx->group, ®_ctx->bufs, ALL_BUFFER_SIZE(max_cnt));
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@ -804,7 +804,7 @@ static MPP_RET hal_h265d_vdpu384a_gen_regs(void *hal, HalTaskInfo *syn)
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HalBuf *origin_buf = NULL;
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if (reg_ctx ->fast_mode) {
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for (i = 0; i < MAX_GEN_REG; i++) {
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for (i = 0; i < VDPU_FAST_REG_SET_CNT; i++) {
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if (!reg_ctx->g_buf[i].use_flag) {
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syn->dec.reg_index = i;
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@ -816,7 +816,7 @@ static MPP_RET hal_h265d_vdpu384a_gen_regs(void *hal, HalTaskInfo *syn)
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break;
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}
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}
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if (i == MAX_GEN_REG) {
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if (i == VDPU_FAST_REG_SET_CNT) {
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mpp_err("hevc rps buf all used");
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return MPP_ERR_NOMEM;
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}
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