diff --git a/mpp/hal/rkdec/av1d/hal_av1d_com.c b/mpp/hal/rkdec/av1d/hal_av1d_com.c index 363ef995..3f1f152e 100644 --- a/mpp/hal/rkdec/av1d/hal_av1d_com.c +++ b/mpp/hal/rkdec/av1d/hal_av1d_com.c @@ -5,7 +5,11 @@ #define MODULE_TAG "hal_av1d_com" +#include "mpp_bitput.h" + +#include "hal_av1d_ctx.h" #include "hal_av1d_com.h" +#include "vdpu38x_com.h" const RK_U32 g_av1d_default_prob[7400] = { 0x000052ce, 0x90000000, 0x000003e2, 0x3b000000, 0x0013e5db, 0x00000000, 0x00000000, 0x20000000, @@ -934,3 +938,669 @@ const RK_U32 g_av1d_default_prob[7400] = { 0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000, 0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000, }; + +static void hal_av1d_release_res(void *hal) +{ + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + Vdpu38xAv1dRegCtx *reg_ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx; + RK_U32 max_cnt = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; + RK_U32 i = 0; + + for (i = 0; i < max_cnt; i++) + MPP_FREE(reg_ctx->reg_buf[i].regs); + + BUF_PUT(reg_ctx->cdf_rd_def_base); + BUF_PUT(reg_ctx->bufs); + for (i = 0; i < max_cnt; i++) + BUF_PUT(reg_ctx->rcb_bufs[i]); + vdpu38x_rcb_calc_deinit(reg_ctx->rcb_ctx); + + BUF_PUT(reg_ctx->filter_mem); + + if (reg_ctx->cdf_segid_bufs) { + hal_bufs_deinit(reg_ctx->cdf_segid_bufs); + reg_ctx->cdf_segid_bufs = NULL; + } + if (reg_ctx->colmv_bufs) { + hal_bufs_deinit(reg_ctx->colmv_bufs); + reg_ctx->colmv_bufs = NULL; + } + if (reg_ctx->origin_bufs) { + hal_bufs_deinit(reg_ctx->origin_bufs); + reg_ctx->origin_bufs = NULL; + } + + MPP_FREE(p_hal->reg_ctx); +} + +MPP_RET vdpu38x_av1d_deinit(void *hal) +{ + hal_av1d_release_res(hal); + + return MPP_OK; +} + +MPP_RET vdpu38x_av1d_reset(void *hal) +{ + (void)hal; + + return MPP_OK; +} + +MPP_RET vdpu38x_av1d_flush(void *hal) +{ + (void)hal; + + return MPP_OK; +} + +MPP_RET vdpu38x_av1d_control(void *hal, MpiCmd cmd_type, void *param) +{ + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + MPP_RET ret = MPP_ERR_UNKNOW; + + INP_CHECK(ret, NULL == p_hal); + + switch ((MpiCmd)cmd_type) { + case MPP_DEC_SET_FRAME_INFO : { + MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param); + RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param); + RK_U32 imgheight = mpp_frame_get_height((MppFrame)param); + + AV1D_DBG(AV1D_DBG_LOG, "control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight); + if ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV422SP) { + mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, mpp_align_wxh2yuv422); + } + if (MPP_FRAME_FMT_IS_FBC(fmt)) { + vdpu38x_afbc_align_calc(p_hal->slots, (MppFrame)param, 16); + } else if (imgwidth > 1920 || imgheight > 1088) { + mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64); + } + break; + } + case MPP_DEC_GET_THUMBNAIL_FRAME_INFO: { + vdpu38x_update_thumbnail_frame_info((MppFrame)param); + } break; + case MPP_DEC_SET_OUTPUT_FORMAT : { + } break; + default : { + } break; + } + +__RETURN: + return ret = MPP_OK; +} + +static RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b) +{ + if (!dxva->order_hint_bits) return 0; + const RK_S32 bits = dxva->order_hint_bits - 1; + + RK_S32 diff = a - b; + RK_S32 m = 1 << bits; + diff = (diff & (m - 1)) - (diff & m); + return diff; +} + +static RK_U32 mpp_clip_uintp2(RK_S32 a, RK_S32 p) +{ + if (a & ~((1 << p) - 1)) + return -a >> 31 & ((1 << p) - 1); + else + return a; +} + +MPP_RET vdpu38x_av1d_uncomp_hdr(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva, + RK_U64 *data, RK_U32 len) +{ + RockchipSocType soc_type; + BitputCtx_t bp; + RK_S32 i, j; + (void) p_hal; + + soc_type = mpp_get_soc_type(); + + mpp_set_bitput_ctx(&bp, data, len); + + /* sequence header */ + mpp_put_bits(&bp, dxva->coding.current_operating_point, 12); + mpp_put_bits(&bp, dxva->coding.use_128x128_superblock, 1); + mpp_put_bits(&bp, dxva->coding.filter_intra, 1); + mpp_put_bits(&bp, dxva->coding.intra_edge_filter, 1); + mpp_put_bits(&bp, dxva->coding.interintra_compound, 1); + mpp_put_bits(&bp, dxva->coding.masked_compound, 1); + mpp_put_bits(&bp, dxva->coding.dual_filter, 1); + mpp_put_bits(&bp, dxva->enable_order_hint, 1); + mpp_put_bits(&bp, dxva->coding.jnt_comp, 1); + mpp_put_bits(&bp, dxva->coding.enable_ref_frame_mvs, 1); + { + RK_S32 order_hint_bits_minus_1 = dxva->order_hint_bits ? (dxva->order_hint_bits - 1) : 0; + + mpp_put_bits(&bp, order_hint_bits_minus_1, 3); + } + { + RK_U32 skip_loop_filter = 0; // TODO: control by user + RK_U32 enable_cdef = !skip_loop_filter && !dxva->coded_lossless; + RK_U32 enable_cdef_y = dxva->cdef.y_strengths[0].primary || dxva->cdef.y_strengths[0].secondary; + RK_U32 enable_cdef_uv = dxva->cdef.uv_strengths[0].primary || dxva->cdef.uv_strengths[0].secondary; + + enable_cdef = enable_cdef && (dxva->cdef.bits || enable_cdef_y || enable_cdef_uv); + mpp_put_bits(&bp, enable_cdef, 1); + } + mpp_put_bits(&bp, (dxva->bitdepth > 8) ? (dxva->bitdepth - 8) : 0, 3); + { + RK_U32 yuv_format = 0; + + if (dxva->format.mono_chrome) + yuv_format = 0; // 400 + else if (dxva->format.subsampling_y == 1 && dxva->format.subsampling_y == 1) + yuv_format = 1; // 420 + else if (dxva->format.subsampling_x == 1) + yuv_format = 2; // 422 + else + yuv_format = 3; // 444 + + mpp_put_bits(&bp, yuv_format, 2); + } + + mpp_put_bits(&bp, dxva->film_grain.matrix_coefficients, 8); + mpp_put_bits(&bp, dxva->coding.film_grain_en, 1); + + /* frame uncompresss header */ + { + RK_U32 frame_is_intra = dxva->format.frame_type == KEY_FRAME || + dxva->format.frame_type == INTRA_ONLY_FRAME; + + mpp_put_bits(&bp, frame_is_intra, 1); + mpp_put_bits(&bp, dxva->coding.disable_cdf_update, 1); + mpp_put_bits(&bp, dxva->coding.screen_content_tools, 1); + mpp_put_bits(&bp, dxva->coding.integer_mv || frame_is_intra, 1); + mpp_put_bits(&bp, dxva->order_hint, 8); + if (soc_type == ROCKCHIP_SOC_RK3538 || soc_type == ROCKCHIP_SOC_RK3572) + mpp_put_bits(&bp, dxva->primary_ref_frame == AV1_PRIMARY_REF_NONE, 1); + mpp_put_bits(&bp, dxva->width, 16); + mpp_put_bits(&bp, dxva->height, 16); + mpp_put_bits(&bp, dxva->coding.superres, 1); + mpp_put_bits(&bp, dxva->superres_denom, 5); + mpp_put_bits(&bp, dxva->upscaled_width, 16); + mpp_put_bits(&bp, dxva->coding.high_precision_mv, 1); + mpp_put_bits(&bp, dxva->coding.intrabc, 1); + } + + for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++) + mpp_put_bits(&bp, dxva->ref_frame_valued ? dxva->ref_frame_idx[i] : (RK_U32) - 1, 3); + + mpp_put_bits(&bp, dxva->interp_filter, 3); + mpp_put_bits(&bp, dxva->coding.switchable_motion_mode, 1); + mpp_put_bits(&bp, dxva->coding.use_ref_frame_mvs, 1); + + { + RK_U32 mapped_idx = 0; + + for (i = 0; i < NUM_REF_FRAMES; i++) { + mpp_put_bits(&bp, dxva->frame_refs[i].order_hint, 8); + } + for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++) { + mapped_idx = dxva->ref_frame_idx[i]; + mpp_put_bits(&bp, dxva->ref_order_hint[mapped_idx], 8); + } + } + + for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i) { + if (!dxva->order_hint_bits) { + dxva->ref_frame_sign_bias[i] = 0; + } else { + if (dxva->frame_refs[i].Index >= 0) { + RK_S32 ref_frame_offset = dxva->frame_refs[dxva->ref_frame_idx[i]].order_hint; + RK_S32 rel_off = GetRelativeDist(dxva, ref_frame_offset, dxva->order_hint); + + dxva->ref_frame_sign_bias[i] = (rel_off <= 0) ? 0 : 1; + } + } + mpp_put_bits(&bp, dxva->ref_frame_sign_bias[i], 1); + } + + mpp_put_bits(&bp, dxva->coding.disable_frame_end_update_cdf, 1); + + /* quantization params */ + mpp_put_bits(&bp, dxva->quantization.base_qindex, 8); + mpp_put_bits(&bp, dxva->quantization.y_dc_delta_q, 7); + mpp_put_bits(&bp, dxva->quantization.u_dc_delta_q, 7); + mpp_put_bits(&bp, dxva->quantization.u_ac_delta_q, 7); + mpp_put_bits(&bp, dxva->quantization.v_dc_delta_q, 7); + mpp_put_bits(&bp, dxva->quantization.v_ac_delta_q, 7); + mpp_put_bits(&bp, dxva->quantization.using_qmatrix, 1); + + /* segmentation params */ + mpp_put_bits(&bp, dxva->segmentation.enabled, 1); + mpp_put_bits(&bp, dxva->segmentation.update_map, 1); + mpp_put_bits(&bp, dxva->segmentation.temporal_update, 1); + + { + RK_U32 mi_rows = MPP_ALIGN(dxva->width, 8) >> MI_SIZE_LOG2; + RK_U32 mi_cols = MPP_ALIGN(dxva->height, 8) >> MI_SIZE_LOG2; + /* index 0: AV1_REF_FRAME_LAST - AV1_REF_FRAME_LAST */ + RK_U32 prev_mi_rows = MPP_ALIGN(dxva->frame_refs[0].width, 8) >> MI_SIZE_LOG2; + RK_U32 prev_mi_cols = MPP_ALIGN(dxva->frame_refs[0].height, 8) >> MI_SIZE_LOG2; + RK_U32 use_prev_segmentation_ids = dxva->segmentation.enabled && dxva->primary_ref_frame && + (mi_rows == prev_mi_rows) && + (mi_cols == prev_mi_cols); + + mpp_put_bits(&bp, use_prev_segmentation_ids, 1); + } + + /* Segmentation data update */ + for (i = 0; i < MAX_SEGMENTS; i++) + mpp_put_bits(&bp, dxva->segmentation.feature_mask[i], 8); + + for (i = 0; i < MAX_SEGMENTS; i++) { + mpp_put_bits(&bp, dxva->segmentation.feature_data[i][0], 9); + mpp_put_bits(&bp, dxva->segmentation.feature_data[i][1], 7); + mpp_put_bits(&bp, dxva->segmentation.feature_data[i][2], 7); + mpp_put_bits(&bp, dxva->segmentation.feature_data[i][3], 7); + mpp_put_bits(&bp, dxva->segmentation.feature_data[i][4], 7); + mpp_put_bits(&bp, dxva->segmentation.feature_data[i][5], 3); + } + mpp_put_bits(&bp, dxva->segmentation.last_active, 3); + mpp_put_bits(&bp, dxva->segmentation.preskip, 1); + mpp_put_bits(&bp, dxva->quantization.delta_q_present, 1); + if (dxva->quantization.delta_q_present) + mpp_put_bits(&bp, dxva->quantization.delta_q_res, 2); + else + mpp_put_bits(&bp, 1 << dxva->quantization.delta_q_res, 2); + + /* delta lf params */ + mpp_put_bits(&bp, dxva->loop_filter.delta_lf_present, 1); + mpp_put_bits(&bp, 1 << dxva->loop_filter.delta_lf_res, 2); + mpp_put_bits(&bp, dxva->loop_filter.delta_lf_multi, 1); + mpp_put_bits(&bp, dxva->coded_lossless, 1); + for (i = 0; i < MAX_SEGMENTS; ++i) { + RK_S32 qindex, lossless; + + if (dxva->segmentation.feature_mask[i] & 0x1) { + qindex = (dxva->quantization.base_qindex + dxva->segmentation.feature_data[i][SEG_LVL_ALT_Q]); + } else { + qindex = dxva->quantization.base_qindex; + } + qindex = mpp_clip_uintp2(qindex, 8); + lossless = qindex == 0 && dxva->quantization.y_dc_delta_q == 0 && + dxva->quantization.u_dc_delta_q == 0 && + dxva->quantization.v_dc_delta_q == 0 && + dxva->quantization.u_ac_delta_q == 0 && + dxva->quantization.v_ac_delta_q == 0; + + mpp_put_bits(&bp, lossless, 1); + } + mpp_put_bits(&bp, dxva->all_lossless, 1); + + /* segmentation dequant */ + mpp_put_bits(&bp, dxva->quantization.qm_y, 4); + mpp_put_bits(&bp, dxva->quantization.qm_u, 4); + mpp_put_bits(&bp, dxva->quantization.qm_v, 4); + mpp_put_bits(&bp, dxva->loop_filter.filter_level[0], 6); + mpp_put_bits(&bp, dxva->loop_filter.filter_level[1], 6); + mpp_put_bits(&bp, dxva->loop_filter.filter_level_u, 6); + mpp_put_bits(&bp, dxva->loop_filter.filter_level_v, 6); + mpp_put_bits(&bp, dxva->loop_filter.sharpness_level, 3); + mpp_put_bits(&bp, dxva->loop_filter.mode_ref_delta_enabled, 1); + + for (i = 0; i < NUM_REF_FRAMES; i++) + mpp_put_bits(&bp, dxva->loop_filter.ref_deltas[i], 7); + + for (i = 0; i < MAX_MODE_LF_DELTAS; i++) + mpp_put_bits(&bp, dxva->loop_filter.mode_deltas[i], 7); + + /* cdef params */ + mpp_put_bits(&bp, dxva->cdef.damping + 3, 3); + mpp_put_bits(&bp, dxva->cdef.bits, 2); + + for (i = 0; i < 8; i++) + mpp_put_bits(&bp, dxva->cdef.y_strengths[i].primary, 4); + + for (i = 0; i < 8; i++) + mpp_put_bits(&bp, dxva->cdef.uv_strengths[i].primary, 4); + + for (i = 0; i < 8; i++) + mpp_put_bits(&bp, dxva->cdef.y_strengths[i].secondary, 2); + + for (i = 0; i < 8; i++) + mpp_put_bits(&bp, dxva->cdef.uv_strengths[i].secondary, 2); + + { + RK_U32 uses_lr = 0; + + for (i = 0; i < (dxva->format.mono_chrome ? 1 : 3); i++) + uses_lr |= (dxva->loop_filter.frame_restoration_type[i] != AV1_RESTORE_NONE) ? 1 : 0; + mpp_put_bits(&bp, uses_lr, 1); + } + for (i = 0; i < 3; ++i) + mpp_put_bits(&bp, dxva->loop_filter.frame_restoration_type[i], 2); + for (i = 0; i < 2; ++i) // 0:32x32, 1:64x64, 2:128x128, 3:256x256 + mpp_put_bits(&bp, dxva->loop_filter.log2_restoration_unit_size[i], 2); + + mpp_put_bits(&bp, dxva->coding.tx_mode, 2); + mpp_put_bits(&bp, dxva->coding.reference_mode, 1); + mpp_put_bits(&bp, dxva->skip_ref0, 3); + mpp_put_bits(&bp, dxva->skip_ref1, 3); + mpp_put_bits(&bp, dxva->coding.skip_mode, 1); + mpp_put_bits(&bp, dxva->coding.warped_motion, 1); + mpp_put_bits(&bp, dxva->coding.reduced_tx_set, 1); + + /* gm_type and gm_params */ + for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i) + mpp_put_bits(&bp, dxva->frame_refs[i].wmtype, 2); + + for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i) + for (j = 0; j < 6; j++) + mpp_put_bits(&bp, dxva->frame_refs[i].wmmat_val[j], 17); + + /* film_grain_params */ + { + mpp_put_bits(&bp, dxva->film_grain.apply_grain, 1); + mpp_put_bits(&bp, dxva->film_grain.grain_seed, 16); + mpp_put_bits(&bp, dxva->film_grain.update_grain, 1); + mpp_put_bits(&bp, dxva->film_grain.num_y_points, 4); + + for (i = 0; i < 14; i++) + mpp_put_bits(&bp, dxva->film_grain.scaling_points_y[i][0], 8); + + for (i = 0; i < 14; i++) + mpp_put_bits(&bp, dxva->film_grain.scaling_points_y[i][1], 8); + + mpp_put_bits(&bp, dxva->film_grain.chroma_scaling_from_luma, 1); + mpp_put_bits(&bp, dxva->film_grain.num_cb_points, 4); + + for (i = 0; i < 10; ++i) + mpp_put_bits(&bp, dxva->film_grain.scaling_points_cb[i][0], 8); + + for (i = 0; i < 10; ++i) + mpp_put_bits(&bp, dxva->film_grain.scaling_points_cb[i][1], 8); + + mpp_put_bits(&bp, dxva->film_grain.num_cr_points, 4); + for (i = 0; i < 10; ++i) + mpp_put_bits(&bp, dxva->film_grain.scaling_points_cr[i][0], 8); + + for (i = 0; i < 10; ++i) + mpp_put_bits(&bp, dxva->film_grain.scaling_points_cr[i][1], 8); + + mpp_put_bits(&bp, dxva->film_grain.scaling_shift_minus8, 2); + mpp_put_bits(&bp, dxva->film_grain.ar_coeff_lag, 2); + for (i = 0; i < 24; ++i) + mpp_put_bits(&bp, dxva->film_grain.ar_coeffs_y[i], 8); + + for (i = 0; i < 25; ++i) + mpp_put_bits(&bp, dxva->film_grain.ar_coeffs_cb[i], 8); + + for (i = 0; i < 25; ++i) + mpp_put_bits(&bp, dxva->film_grain.ar_coeffs_cr[i], 8); + + mpp_put_bits(&bp, dxva->film_grain.ar_coeff_shift_minus6, 2); + mpp_put_bits(&bp, dxva->film_grain.grain_scale_shift, 2); + mpp_put_bits(&bp, dxva->film_grain.cb_mult, 8); + mpp_put_bits(&bp, dxva->film_grain.cb_luma_mult, 8); + mpp_put_bits(&bp, dxva->film_grain.cb_offset, 9); + mpp_put_bits(&bp, dxva->film_grain.cr_mult, 8); + mpp_put_bits(&bp, dxva->film_grain.cr_luma_mult, 8); + mpp_put_bits(&bp, dxva->film_grain.cr_offset, 9); + mpp_put_bits(&bp, dxva->film_grain.overlap_flag, 1); + mpp_put_bits(&bp, dxva->film_grain.clip_to_restricted_range, 1); + } + + /* ref frame info */ + for (i = 0; i < NUM_REF_FRAMES; ++i) + mpp_put_bits(&bp, dxva->frame_ref_state[i].upscaled_width, 16); + + for (i = 0; i < NUM_REF_FRAMES; ++i) + mpp_put_bits(&bp, dxva->frame_ref_state[i].frame_height, 16); + + for (i = 0; i < NUM_REF_FRAMES; ++i) + mpp_put_bits(&bp, dxva->frame_ref_state[i].frame_width, 16); + + for (i = 0; i < NUM_REF_FRAMES; ++i) + mpp_put_bits(&bp, dxva->frame_ref_state[i].frame_type, 2); + + for (i = 0; i < NUM_REF_FRAMES; ++i) { + mpp_put_bits(&bp, dxva->frame_refs[i].lst_frame_offset, 8); + mpp_put_bits(&bp, dxva->frame_refs[i].lst2_frame_offset, 8); + mpp_put_bits(&bp, dxva->frame_refs[i].lst3_frame_offset, 8); + mpp_put_bits(&bp, dxva->frame_refs[i].gld_frame_offset, 8); + mpp_put_bits(&bp, dxva->frame_refs[i].bwd_frame_offset, 8); + mpp_put_bits(&bp, dxva->frame_refs[i].alt2_frame_offset, 8); + mpp_put_bits(&bp, dxva->frame_refs[i].alt_frame_offset, 8); + } + + { + RK_U32 mapped_idx = 0; + RK_U32 mapped_frame_width[8] = {0}; + RK_U32 mapped_frame_height[8] = {0}; + + for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++) { + mapped_idx = dxva->ref_frame_idx[i]; + mapped_frame_width[mapped_idx] = dxva->frame_ref_state[mapped_idx].frame_width; + mapped_frame_height[mapped_idx] = dxva->frame_ref_state[mapped_idx].frame_height; + } + for (i = 0; i <= ALLOWED_REFS_PER_FRAME_EX; ++i) { + RK_U32 hor_scale, ver_scale; + + if (dxva->coding.intrabc) { + hor_scale = dxva->width; + ver_scale = dxva->height; + } else { + hor_scale = mapped_frame_width[i]; + ver_scale = mapped_frame_height[i]; + } + hor_scale = ((hor_scale << AV1_REF_SCALE_SHIFT) + dxva->width / 2) / dxva->width; + ver_scale = ((ver_scale << AV1_REF_SCALE_SHIFT) + dxva->height / 2) / dxva->height; + + mpp_put_bits(&bp, hor_scale, 16); + mpp_put_bits(&bp, ver_scale, 16); + } + } + + mpp_put_bits(&bp, (dxva->frame_header_size + 7) >> 3, 10); + /* tile info */ + mpp_put_bits(&bp, dxva->tiles.cols, 7); + mpp_put_bits(&bp, dxva->tiles.rows, 7); + mpp_put_bits(&bp, dxva->tiles.context_update_id, 12); + mpp_put_bits(&bp, dxva->tiles.tile_sz_mag + 1, 3); + mpp_put_bits(&bp, dxva->tiles.cols * dxva->tiles.rows, 13); + mpp_put_bits(&bp, dxva->tile_cols_log2 + dxva->tile_rows_log2, 12); + + for (i = 0; i < 64; i++) + mpp_put_bits(&bp, dxva->tiles.widths[i], 7); + + for (i = 0; i < 64; i++) + mpp_put_bits(&bp, dxva->tiles.heights[i], 10); + + mpp_put_align(&bp, 128, 0); + + return MPP_OK; +} + +MPP_RET vdpu38x_av1d_cdf_setup(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + Vdpu38xAv1dRegCtx *reg_ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx; + size_t segid_size = (MPP_ALIGN(dxva->width, 128) / 128) * \ + (MPP_ALIGN(dxva->height, 128) / 128) * \ + 32 * 16; + size_t size = ALL_CDF_SIZE + segid_size; + MPP_RET ret = MPP_ERR_UNKNOW; + + /* the worst case is the frame is error with whole frame */ + if (reg_ctx->cdf_segid_size < size) { + if (reg_ctx->cdf_segid_bufs) { + hal_bufs_deinit(reg_ctx->cdf_segid_bufs); + reg_ctx->cdf_segid_bufs = NULL; + } + + hal_bufs_init(®_ctx->cdf_segid_bufs); + if (reg_ctx->cdf_segid_bufs == NULL) { + mpp_err_f("cdf bufs init fail"); + goto __RETURN; + } + + reg_ctx->cdf_segid_size = size; + reg_ctx->cdf_segid_count = mpp_buf_slot_get_count(p_hal->slots); + hal_bufs_setup(reg_ctx->cdf_segid_bufs, reg_ctx->cdf_segid_count, 1, &size); + } + +__RETURN: + return ret; +} + +/* + * cdf buf structure: + * + * base_addr0 +--------------------------+ + * 434x128bit | def_non_coeff_cdf | + * base_addr0+433 +--------------------------+ + * + * base_addr1 +--------------------------+ + * 354x128bit | def_coeff_cdf_0 | + * | (base_q_idx <= 20) | + * +--------------------------+ + * 354x128bit | def_coeff_cdf_1 | + * | (20 < base_q_idx <= 60) | + * +--------------------------+ + * 354x128bit | def_coeff_cdf_2 | + * | (60 < base_q_idx <= 120) | + * +--------------------------+ + * 354x128bit | def_coeff_cdf_3 | + * | (base_q_idx > 120) | + * base_addr1+1415 +--------------------------+ + */ +void vdpu38x_av1d_set_cdf_segid(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva, + RK_U32 *coef_rd_base, RK_U32 *coef_wr_base, + RK_U32 *segid_last_base, RK_U32 *segid_cur_base, + RK_U32 *noncoef_rd_base, RK_U32 *noncoef_wr_base) +{ + Vdpu38xAv1dRegCtx *reg_ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx; + Vdpu38xRegSet *regs = reg_ctx->regs; + RK_U32 coeff_cdf_idx = 0; + RK_U32 mapped_idx = 0; + HalBuf *cdf_buf = NULL; + MppBuffer buf_tmp = NULL; + RK_U32 i = 0; + + /* use para in decoder */ +#ifdef DUMP_VDPU38X_DATAS + { + char *cur_fname = "cabac_cdf_in.dat"; + + memset(vdpu38x_dump_cur_fname_path, 0, sizeof(vdpu38x_dump_cur_fname_path)); + sprintf(vdpu38x_dump_cur_fname_path, "%s/%s", vdpu38x_dump_cur_dir, cur_fname); + } +#endif + if (dxva->format.frame_type == AV1_FRAME_KEY) + for (i = 0; i < NUM_REF_FRAMES; i++) + reg_ctx->ref_info_tbl[i].cdf_valid = 0; + /* def coeff cdf idx */ + coeff_cdf_idx = dxva->quantization.base_qindex <= 20 ? 0 : + dxva->quantization.base_qindex <= 60 ? 1 : + dxva->quantization.base_qindex <= 120 ? 2 : 3; + + if (dxva->format.frame_type == AV1_FRAME_KEY || + dxva->primary_ref_frame == AV1_PRIMARY_REF_NONE) { + *noncoef_rd_base = mpp_buffer_get_fd(reg_ctx->cdf_rd_def_base); + *coef_rd_base = mpp_buffer_get_fd(reg_ctx->cdf_rd_def_base); +#ifdef DUMP_VDPU38X_DATAS + { + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (void *)mpp_buffer_get_ptr(reg_ctx->cdf_rd_def_base), + 8 * NON_COEF_CDF_SIZE, 128, 0, 0); + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->cdf_rd_def_base) + + NON_COEF_CDF_SIZE + COEF_CDF_SIZE * coeff_cdf_idx, + 8 * COEF_CDF_SIZE, 128, 0, 1); + } +#endif + } else { + mapped_idx = dxva->ref_frame_idx[dxva->primary_ref_frame]; + + coeff_cdf_idx = reg_ctx->ref_info_tbl[mapped_idx].coeff_idx; + if (!dxva->coding.disable_frame_end_update_cdf && + reg_ctx->ref_info_tbl[mapped_idx].cdf_valid && + dxva->frame_refs[mapped_idx].Index != (CHAR)0xff && + dxva->frame_refs[mapped_idx].Index != 0x7f) { + cdf_buf = hal_bufs_get_buf(reg_ctx->cdf_segid_bufs, dxva->frame_refs[mapped_idx].Index); + buf_tmp = cdf_buf->buf[0]; + } else { + buf_tmp = reg_ctx->cdf_rd_def_base; + } + *noncoef_rd_base = mpp_buffer_get_fd(buf_tmp); + *coef_rd_base = mpp_buffer_get_fd(buf_tmp); + *segid_last_base = mpp_buffer_get_fd(buf_tmp); +#ifdef DUMP_VDPU38X_DATAS + { + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (void *)mpp_buffer_get_ptr(buf_tmp), + 8 * NON_COEF_CDF_SIZE, 128, 0, 0); + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (RK_U8 *)mpp_buffer_get_ptr(buf_tmp) + + NON_COEF_CDF_SIZE + COEF_CDF_SIZE * coeff_cdf_idx, + 8 * COEF_CDF_SIZE, 128, 0, 1); + } +#endif + } + cdf_buf = hal_bufs_get_buf(reg_ctx->cdf_segid_bufs, dxva->CurrPic.Index7Bits); + *noncoef_wr_base = mpp_buffer_get_fd(cdf_buf->buf[0]); + *coef_wr_base = mpp_buffer_get_fd(cdf_buf->buf[0]); + *segid_cur_base = mpp_buffer_get_fd(cdf_buf->buf[0]); + + /* byte, 434 x 128 bit = 434 x 16 byte */ + mpp_dev_set_reg_offset(p_hal->dev, 178, NON_COEF_CDF_SIZE + COEF_CDF_SIZE * coeff_cdf_idx); + mpp_dev_set_reg_offset(p_hal->dev, 179, NON_COEF_CDF_SIZE); + mpp_dev_set_reg_offset(p_hal->dev, 181, ALL_CDF_SIZE); + mpp_dev_set_reg_offset(p_hal->dev, 182, ALL_CDF_SIZE); + + /* update params sync with "update buffer" */ + for (i = 0; i < NUM_REF_FRAMES; i++) { + if (dxva->refresh_frame_flags & (1 << i)) { + if (dxva->coding.disable_frame_end_update_cdf) { + if (dxva->show_existing_frame && dxva->format.frame_type == AV1_FRAME_KEY) + reg_ctx->ref_info_tbl[i].coeff_idx + = reg_ctx->ref_info_tbl[dxva->frame_to_show_map_idx].coeff_idx; + else + reg_ctx->ref_info_tbl[i].coeff_idx = coeff_cdf_idx; + } else { + reg_ctx->ref_info_tbl[i].cdf_valid = 1; + reg_ctx->ref_info_tbl[i].coeff_idx = 0; + } + } + } + +#ifdef DUMP_VDPU38X_DATAS + { + char *cur_fname = "cdf_rd_def.dat"; + memset(vdpu38x_dump_cur_fname_path, 0, sizeof(vdpu38x_dump_cur_fname_path)); + sprintf(vdpu38x_dump_cur_fname_path, "%s/%s", vdpu38x_dump_cur_dir, cur_fname); + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (void *)mpp_buffer_get_ptr(reg_ctx->cdf_rd_def_base), + (NON_COEF_CDF_SIZE + COEF_CDF_SIZE * 4) * 8, 128, 0, 0); + } +#endif + +} + +MPP_RET vdpu38x_av1d_colmv_setup(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + Vdpu38xAv1dRegCtx *reg_ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx; + size_t mv_size; + MPP_RET ret = MPP_ERR_UNKNOW; + + /* the worst case is the frame is error with whole frame */ + mv_size = MPP_ALIGN(dxva->width, 64) / 64 * MPP_ALIGN(dxva->height, 64) / 64 * 1024; + if (reg_ctx->colmv_bufs == NULL || reg_ctx->colmv_size < mv_size) { + if (reg_ctx->colmv_bufs) { + hal_bufs_deinit(reg_ctx->colmv_bufs); + reg_ctx->colmv_bufs = NULL; + } + + hal_bufs_init(®_ctx->colmv_bufs); + if (reg_ctx->colmv_bufs == NULL) { + mpp_err_f("colmv bufs init fail"); + goto __RETURN; + } + reg_ctx->colmv_size = mv_size; + reg_ctx->colmv_count = mpp_buf_slot_get_count(p_hal->slots); + hal_bufs_setup(reg_ctx->colmv_bufs, reg_ctx->colmv_count, 1, &mv_size); + } + +__RETURN: + return ret; +} diff --git a/mpp/hal/rkdec/av1d/hal_av1d_com.h b/mpp/hal/rkdec/av1d/hal_av1d_com.h index a580d2c8..2aeb0800 100644 --- a/mpp/hal/rkdec/av1d/hal_av1d_com.h +++ b/mpp/hal/rkdec/av1d/hal_av1d_com.h @@ -6,10 +6,29 @@ #ifndef HAL_AV1D_COM_H #define HAL_AV1D_COM_H -#include "rk_type.h" +#include "rk_mpi_cmd.h" +#include "av1d_syntax.h" +#include "hal_av1d_common.h" #define AV1_PRIMARY_REF_NONE 7 +#define NON_COEF_CDF_SIZE (434 * 16) // byte +#define COEF_CDF_SIZE (354 * 16) // byte +#define ALL_CDF_SIZE (NON_COEF_CDF_SIZE + COEF_CDF_SIZE * 4) + extern const RK_U32 g_av1d_default_prob[7400]; +MPP_RET vdpu38x_av1d_deinit(void *hal); +MPP_RET vdpu38x_av1d_reset(void *hal); +MPP_RET vdpu38x_av1d_flush(void *hal); +MPP_RET vdpu38x_av1d_control(void *hal, MpiCmd cmd_type, void *param); +MPP_RET vdpu38x_av1d_uncomp_hdr(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva, + RK_U64 *data, RK_U32 len); +MPP_RET vdpu38x_av1d_cdf_setup(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva); +void vdpu38x_av1d_set_cdf_segid(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva, + RK_U32 *coef_rd_base, RK_U32 *coef_wr_base, + RK_U32 *segid_last_base, RK_U32 *segid_cur_base, + RK_U32 *noncoef_rd_base, RK_U32 *noncoef_wr_base); +MPP_RET vdpu38x_av1d_colmv_setup(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva); + #endif /* HAL_AV1D_COM_H */ diff --git a/mpp/hal/rkdec/av1d/hal_av1d_ctx.h b/mpp/hal/rkdec/av1d/hal_av1d_ctx.h index 3df25fb5..41475f85 100644 --- a/mpp/hal/rkdec/av1d/hal_av1d_ctx.h +++ b/mpp/hal/rkdec/av1d/hal_av1d_ctx.h @@ -8,6 +8,7 @@ #include "av1d_common.h" #include "vdpu_com.h" +#include "hal_bufs.h" typedef struct Av1dVdpu38xBuf_t { RK_U32 valid; diff --git a/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c b/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c index ecb3e2af..b476dc12 100644 --- a/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c +++ b/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c @@ -18,6 +18,7 @@ #include "hal_av1d_com.h" #include "vdpu383_av1d.h" #include "vdpu383_com.h" +#include "vdpu38x_com.h" #include "av1d_syntax.h" #include "film_grain_noise_table.h" @@ -39,17 +40,10 @@ #define VDPU383_RCB_FILTERD_AV1_UP_TL_COL_LEN (MPP_ALIGN(dxva->width, 64) * 10 * 22) #define VDPU383_UNCMPS_HEADER_OFFSET_BASE (0) - #define VDPU383_INFO_ELEM_SIZE (VDPU383_UNCMPS_HEADER_SIZE) - #define VDPU383_UNCMPS_HEADER_OFFSET(idx) (VDPU383_INFO_ELEM_SIZE * idx + VDPU383_UNCMPS_HEADER_OFFSET_BASE) - #define VDPU383_INFO_BUF_SIZE(cnt) (VDPU383_INFO_ELEM_SIZE * cnt) -#define NON_COEF_CDF_SIZE (434 * 16) // byte -#define COEF_CDF_SIZE (354 * 16) // byte -#define ALL_CDF_SIZE (NON_COEF_CDF_SIZE + COEF_CDF_SIZE * 4) - #define SET_REF_HOR_VIRSTRIDE(regs, ref_index, value)\ do{ \ switch(ref_index){\ @@ -120,150 +114,6 @@ default: break;}\ }while(0) -#define OFFSET_CTRL_REGS (8 * sizeof(RK_U32)) -#define OFFSET_COMMON_ADDR_REGS (128 * sizeof(RK_U32)) -#define OFFSET_RCB_PARAS_REGS (140 * sizeof(RK_U32)) -#define OFFSET_AV1D_PARAS_REGS (64 * sizeof(RK_U32)) -#define OFFSET_AV1D_ADDR_REGS (168 * sizeof(RK_U32)) -#define OFFSET_INTERRUPT_REGS (15 * sizeof(RK_U32)) - -// #define DUMP_AV1D_VDPU383_DATAS - -#ifdef DUMP_AV1D_VDPU383_DATAS -static RK_U32 dump_cur_frame = 0; -static char dump_cur_dir[128]; -static char dump_cur_fname_path[512]; - -static MPP_RET flip_string(char *str) -{ - RK_U32 len = strlen(str); - RK_U32 i, j; - - for (i = 0, j = len - 1; i <= j; i++, j--) { - // swapping characters - char c = str[i]; - str[i] = str[j]; - str[j] = c; - } - return MPP_OK; -} - -static MPP_RET dump_data_to_file(char *fname_path, void *data, RK_U32 data_bit_size, - RK_U32 line_bits, RK_U32 big_end, RK_U32 append) -{ - RK_U8 *buf_p = (RK_U8 *)data; - RK_U8 cur_data; - RK_U32 i; - RK_U32 loop_cnt; - FILE *dump_fp = NULL; - char line_tmp[256]; - RK_U32 str_idx = 0; - - if (append) - dump_fp = fopen(fname_path, "aw+"); - else - dump_fp = fopen(fname_path, "w+"); - if (!dump_fp) { - mpp_err_f("open file: %s error!\n", fname_path); - return MPP_NOK; - } - if (append) - fseek(dump_fp, 0, SEEK_END); - - if ((data_bit_size % 4 != 0) || (line_bits % 8 != 0)) { - mpp_err_f("line bits not align to 4!\n"); - return MPP_NOK; - } - - loop_cnt = data_bit_size / 8; - for (i = 0; i < loop_cnt; i++) { - cur_data = buf_p[i]; - - sprintf(&line_tmp[str_idx++], "%0x", cur_data & 0xf); - if ((i * 8 + 4) % line_bits == 0) { - line_tmp[str_idx++] = '\0'; - str_idx = 0; - if (!big_end) - flip_string(line_tmp); - fprintf(dump_fp, "%s\n", line_tmp); - } - sprintf(&line_tmp[str_idx++], "%0x", (cur_data >> 4) & 0xf); - if ((i * 8 + 8) % line_bits == 0) { - line_tmp[str_idx++] = '\0'; - str_idx = 0; - if (!big_end) - flip_string(line_tmp); - fprintf(dump_fp, "%s\n", line_tmp); - } - } - - // last line - if (data_bit_size % 4) { - cur_data = buf_p[i]; - sprintf(&line_tmp[str_idx++], "%0x", cur_data & 0xf); - if ((i * 8 + 8) % line_bits == 0) { - line_tmp[str_idx++] = '\0'; - str_idx = 0; - if (!big_end) - flip_string(line_tmp); - fprintf(dump_fp, "%s\n", line_tmp); - } - } - if (data_bit_size % line_bits) { - loop_cnt = (line_bits - (data_bit_size % line_bits)) / 4; - for (i = 0; i < loop_cnt; i++) - sprintf(&line_tmp[str_idx++], "%0x", 0); - line_tmp[str_idx++] = '\0'; - str_idx = 0; - if (!big_end) - flip_string(line_tmp); - fprintf(dump_fp, "%s\n", line_tmp); - } - - fflush(dump_fp); - fclose(dump_fp); - - return MPP_OK; -} - -static MPP_RET dump_reg(RK_U32 *reg_s, RK_U32 count, RK_U32 log_start_idx) -{ - RK_U32 loop; - for (loop = 0; loop < count; loop++) { - mpp_log("reg[%03d]: 0%08x", log_start_idx + loop, reg_s[loop]); - } - - return MPP_OK; -} -#endif - -static MPP_RET vdpu383_setup_scale_origin_bufs(Av1dHalCtx *p_hal, MppFrame mframe) -{ - Vdpu38xAv1dRegCtx *ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx; - /* for 8K FrameBuf scale mode */ - size_t origin_buf_size = 0; - - origin_buf_size = mpp_frame_get_buf_size(mframe); - - if (!origin_buf_size) { - mpp_err_f("origin_bufs get buf size failed\n"); - return MPP_NOK; - } - if (ctx->origin_bufs) { - hal_bufs_deinit(ctx->origin_bufs); - ctx->origin_bufs = NULL; - } - hal_bufs_init(&ctx->origin_bufs); - if (!ctx->origin_bufs) { - mpp_err_f("origin_bufs init fail\n"); - return MPP_ERR_NOMEM; - } - hal_bufs_setup(ctx->origin_bufs, 16, 1, &origin_buf_size); - - return MPP_OK; -} - - static MPP_RET hal_av1d_alloc_res(void *hal) { MPP_RET ret = MPP_OK; @@ -307,51 +157,11 @@ __FAILED: return ret; } - -static void hal_av1d_release_res(void *hal) -{ - Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; - Vdpu38xAv1dRegCtx *reg_ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx; - RK_U32 i = 0; - RK_U32 max_cnt = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; - - for (i = 0; i < max_cnt; i++) - MPP_FREE(reg_ctx->reg_buf[i].regs); - - BUF_PUT(reg_ctx->cdf_rd_def_base); - BUF_PUT(reg_ctx->bufs); - for (i = 0; i < max_cnt; i++) - BUF_PUT(reg_ctx->rcb_bufs[i]); - - BUF_PUT(reg_ctx->filter_mem); - - if (reg_ctx->cdf_segid_bufs) { - hal_bufs_deinit(reg_ctx->cdf_segid_bufs); - reg_ctx->cdf_segid_bufs = NULL; - } - if (reg_ctx->colmv_bufs) { - hal_bufs_deinit(reg_ctx->colmv_bufs); - reg_ctx->colmv_bufs = NULL; - } - if (reg_ctx->origin_bufs) { - hal_bufs_deinit(reg_ctx->origin_bufs); - reg_ctx->origin_bufs = NULL; - } - - MPP_FREE(p_hal->reg_ctx); -} - -MPP_RET vdpu383_av1d_deinit(void *hal) -{ - hal_av1d_release_res(hal); - - return MPP_OK; -} - MPP_RET vdpu383_av1d_init(void *hal, MppHalCfg *cfg) { MPP_RET ret = MPP_OK; Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + Vdpu38xAv1dRegCtx *reg_ctx = NULL; INP_CHECK(ret, NULL == p_hal); (void) cfg; @@ -361,398 +171,17 @@ MPP_RET vdpu383_av1d_init(void *hal, MppHalCfg *cfg) mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, mpp_align_8); mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, mpp_align_wxh2yuv422); + reg_ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx; + vdpu38x_rcb_calc_init((Vdpu38xRcbCtx **)®_ctx->rcb_ctx); + __RETURN: return MPP_OK; __FAILED: - vdpu383_av1d_deinit(hal); + vdpu38x_av1d_deinit(hal); return ret; } -#define MAX_FRAME_DISTANCE 31 -#define MAX_ACTIVE_REFS AV1_ACTIVE_REFS_EX - -static RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b) -{ - if (!dxva->order_hint_bits) return 0; - const RK_S32 bits = dxva->order_hint_bits - 1; - - RK_S32 diff = a - b; - RK_S32 m = 1 << bits; - diff = (diff & (m - 1)) - (diff & m); - return diff; -} - -#undef MAX_FRAME_DISTANCE - -static RK_U32 mpp_clip_uintp2(RK_S32 a, RK_S32 p) -{ - if (a & ~((1 << p) - 1)) return -a >> 31 & ((1 << p) - 1); - else return a; -} - -static MPP_RET prepare_uncompress_header(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva, - RK_U64 *data, RK_U32 len) -{ - BitputCtx_t bp; - RK_S32 i, j; - (void) p_hal; - - mpp_set_bitput_ctx(&bp, data, len); - - /* sequence header */ - mpp_put_bits(&bp, dxva->coding.current_operating_point, 12); - mpp_put_bits(&bp, dxva->coding.use_128x128_superblock, 1); - mpp_put_bits(&bp, dxva->coding.filter_intra, 1); - mpp_put_bits(&bp, dxva->coding.intra_edge_filter, 1); - mpp_put_bits(&bp, dxva->coding.interintra_compound, 1); - mpp_put_bits(&bp, dxva->coding.masked_compound, 1); - mpp_put_bits(&bp, dxva->coding.dual_filter, 1); - mpp_put_bits(&bp, dxva->enable_order_hint, 1); - mpp_put_bits(&bp, dxva->coding.jnt_comp, 1); - mpp_put_bits(&bp, dxva->coding.enable_ref_frame_mvs, 1); - { - RK_S32 order_hint_bits_minus_1 = dxva->order_hint_bits ? (dxva->order_hint_bits - 1) : 0; - - mpp_put_bits(&bp, order_hint_bits_minus_1, 3); - } - { - RK_U32 skip_loop_filter = 0; // TODO: control by user - RK_U32 enable_cdef = !skip_loop_filter && !dxva->coded_lossless; - RK_U32 enable_cdef_y = dxva->cdef.y_strengths[0].primary || dxva->cdef.y_strengths[0].secondary; - RK_U32 enable_cdef_uv = dxva->cdef.uv_strengths[0].primary || dxva->cdef.uv_strengths[0].secondary; - - enable_cdef = enable_cdef && (dxva->cdef.bits || enable_cdef_y || enable_cdef_uv); - mpp_put_bits(&bp, enable_cdef, 1); - } - mpp_put_bits(&bp, (dxva->bitdepth > 8) ? (dxva->bitdepth - 8) : 0, 3); - { - RK_U32 yuv_format = 0; - - if (dxva->format.mono_chrome) - yuv_format = 0; // 400 - else if (dxva->format.subsampling_y == 1 && dxva->format.subsampling_y == 1) - yuv_format = 1; // 420 - else if (dxva->format.subsampling_x == 1) - yuv_format = 2; // 422 - else - yuv_format = 3; // 444 - - mpp_put_bits(&bp, yuv_format, 2); - } - - mpp_put_bits(&bp, dxva->film_grain.matrix_coefficients, 8); - mpp_put_bits(&bp, dxva->coding.film_grain_en, 1); - - /* frame uncompresss header */ - { - RK_U32 frame_is_intra = dxva->format.frame_type == KEY_FRAME || - dxva->format.frame_type == INTRA_ONLY_FRAME; - - mpp_put_bits(&bp, frame_is_intra, 1); - mpp_put_bits(&bp, dxva->coding.disable_cdf_update, 1); - mpp_put_bits(&bp, dxva->coding.screen_content_tools, 1); - mpp_put_bits(&bp, dxva->coding.integer_mv || frame_is_intra, 1); - mpp_put_bits(&bp, dxva->order_hint, 8); - mpp_put_bits(&bp, dxva->width, 16); - mpp_put_bits(&bp, dxva->height, 16); - mpp_put_bits(&bp, dxva->coding.superres, 1); - mpp_put_bits(&bp, dxva->superres_denom, 5); - mpp_put_bits(&bp, dxva->upscaled_width, 16); - mpp_put_bits(&bp, dxva->coding.high_precision_mv, 1); - mpp_put_bits(&bp, dxva->coding.intrabc, 1); - } - - for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++) - mpp_put_bits(&bp, dxva->ref_frame_valued ? dxva->ref_frame_idx[i] : (RK_U32) - 1, 3); - - mpp_put_bits(&bp, dxva->interp_filter, 3); - mpp_put_bits(&bp, dxva->coding.switchable_motion_mode, 1); - mpp_put_bits(&bp, dxva->coding.use_ref_frame_mvs, 1); - - { - RK_U32 mapped_idx = 0; - - for (i = 0; i < NUM_REF_FRAMES; i++) { - mpp_put_bits(&bp, dxva->frame_refs[i].order_hint, 8); - } - for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++) { - mapped_idx = dxva->ref_frame_idx[i]; - mpp_put_bits(&bp, dxva->ref_order_hint[mapped_idx], 8); - } - } - - for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i) { - if (!dxva->order_hint_bits) { - dxva->ref_frame_sign_bias[i] = 0; - } else { - if (dxva->frame_refs[i].Index >= 0) { - RK_S32 ref_frame_offset = dxva->frame_refs[dxva->ref_frame_idx[i]].order_hint; - RK_S32 rel_off = GetRelativeDist(dxva, ref_frame_offset, dxva->order_hint); - - dxva->ref_frame_sign_bias[i] = (rel_off <= 0) ? 0 : 1; - } - } - mpp_put_bits(&bp, dxva->ref_frame_sign_bias[i], 1); - } - - mpp_put_bits(&bp, dxva->coding.disable_frame_end_update_cdf, 1); - - /* quantization params */ - mpp_put_bits(&bp, dxva->quantization.base_qindex, 8); - mpp_put_bits(&bp, dxva->quantization.y_dc_delta_q, 7); - mpp_put_bits(&bp, dxva->quantization.u_dc_delta_q, 7); - mpp_put_bits(&bp, dxva->quantization.u_ac_delta_q, 7); - mpp_put_bits(&bp, dxva->quantization.v_dc_delta_q, 7); - mpp_put_bits(&bp, dxva->quantization.v_ac_delta_q, 7); - mpp_put_bits(&bp, dxva->quantization.using_qmatrix, 1); - - /* segmentation params */ - mpp_put_bits(&bp, dxva->segmentation.enabled, 1); - mpp_put_bits(&bp, dxva->segmentation.update_map, 1); - mpp_put_bits(&bp, dxva->segmentation.temporal_update, 1); - - { - RK_U32 mi_rows = MPP_ALIGN(dxva->width, 8) >> MI_SIZE_LOG2; - RK_U32 mi_cols = MPP_ALIGN(dxva->height, 8) >> MI_SIZE_LOG2; - /* index 0: AV1_REF_FRAME_LAST - AV1_REF_FRAME_LAST */ - RK_U32 prev_mi_rows = MPP_ALIGN(dxva->frame_refs[0].width, 8) >> MI_SIZE_LOG2; - RK_U32 prev_mi_cols = MPP_ALIGN(dxva->frame_refs[0].height, 8) >> MI_SIZE_LOG2; - RK_U32 use_prev_segmentation_ids = dxva->segmentation.enabled && dxva->primary_ref_frame && - (mi_rows == prev_mi_rows) && - (mi_cols == prev_mi_cols); - - mpp_put_bits(&bp, use_prev_segmentation_ids, 1); - } - - /* Segmentation data update */ - for (i = 0; i < MAX_SEGMENTS; i++) - mpp_put_bits(&bp, dxva->segmentation.feature_mask[i], 8); - - for (i = 0; i < MAX_SEGMENTS; i++) { - mpp_put_bits(&bp, dxva->segmentation.feature_data[i][0], 9); - mpp_put_bits(&bp, dxva->segmentation.feature_data[i][1], 7); - mpp_put_bits(&bp, dxva->segmentation.feature_data[i][2], 7); - mpp_put_bits(&bp, dxva->segmentation.feature_data[i][3], 7); - mpp_put_bits(&bp, dxva->segmentation.feature_data[i][4], 7); - mpp_put_bits(&bp, dxva->segmentation.feature_data[i][5], 3); - } - mpp_put_bits(&bp, dxva->segmentation.last_active, 3); - mpp_put_bits(&bp, dxva->segmentation.preskip, 1); - mpp_put_bits(&bp, dxva->quantization.delta_q_present, 1); - if (dxva->quantization.delta_q_present) - mpp_put_bits(&bp, dxva->quantization.delta_q_res, 2); - else - mpp_put_bits(&bp, 1 << dxva->quantization.delta_q_res, 2); - - /* delta lf params */ - mpp_put_bits(&bp, dxva->loop_filter.delta_lf_present, 1); - mpp_put_bits(&bp, 1 << dxva->loop_filter.delta_lf_res, 2); - mpp_put_bits(&bp, dxva->loop_filter.delta_lf_multi, 1); - mpp_put_bits(&bp, dxva->coded_lossless, 1); - for (i = 0; i < MAX_SEGMENTS; ++i) { - RK_S32 qindex, lossless; - - if (dxva->segmentation.feature_mask[i] & 0x1) { - qindex = (dxva->quantization.base_qindex + dxva->segmentation.feature_data[i][SEG_LVL_ALT_Q]); - } else { - qindex = dxva->quantization.base_qindex; - } - qindex = mpp_clip_uintp2(qindex, 8); - lossless = qindex == 0 && dxva->quantization.y_dc_delta_q == 0 && - dxva->quantization.u_dc_delta_q == 0 && - dxva->quantization.v_dc_delta_q == 0 && - dxva->quantization.u_ac_delta_q == 0 && - dxva->quantization.v_ac_delta_q == 0; - - mpp_put_bits(&bp, lossless, 1); - } - mpp_put_bits(&bp, dxva->all_lossless, 1); - - /* segmentation dequant */ - mpp_put_bits(&bp, dxva->quantization.qm_y, 4); - mpp_put_bits(&bp, dxva->quantization.qm_u, 4); - mpp_put_bits(&bp, dxva->quantization.qm_v, 4); - mpp_put_bits(&bp, dxva->loop_filter.filter_level[0], 6); - mpp_put_bits(&bp, dxva->loop_filter.filter_level[1], 6); - mpp_put_bits(&bp, dxva->loop_filter.filter_level_u, 6); - mpp_put_bits(&bp, dxva->loop_filter.filter_level_v, 6); - mpp_put_bits(&bp, dxva->loop_filter.sharpness_level, 3); - mpp_put_bits(&bp, dxva->loop_filter.mode_ref_delta_enabled, 1); - - for (i = 0; i < NUM_REF_FRAMES; i++) - mpp_put_bits(&bp, dxva->loop_filter.ref_deltas[i], 7); - - for (i = 0; i < MAX_MODE_LF_DELTAS; i++) - mpp_put_bits(&bp, dxva->loop_filter.mode_deltas[i], 7); - - /* cdef params */ - mpp_put_bits(&bp, dxva->cdef.damping + 3, 3); - mpp_put_bits(&bp, dxva->cdef.bits, 2); - - for (i = 0; i < 8; i++) - mpp_put_bits(&bp, dxva->cdef.y_strengths[i].primary, 4); - - for (i = 0; i < 8; i++) - mpp_put_bits(&bp, dxva->cdef.uv_strengths[i].primary, 4); - - for (i = 0; i < 8; i++) - mpp_put_bits(&bp, dxva->cdef.y_strengths[i].secondary, 2); - - for (i = 0; i < 8; i++) - mpp_put_bits(&bp, dxva->cdef.uv_strengths[i].secondary, 2); - - { - RK_U32 uses_lr = 0; - - for (i = 0; i < (dxva->format.mono_chrome ? 1 : 3); i++) - uses_lr |= (dxva->loop_filter.frame_restoration_type[i] != AV1_RESTORE_NONE) ? 1 : 0; - mpp_put_bits(&bp, uses_lr, 1); - } - for (i = 0; i < 3; ++i) - mpp_put_bits(&bp, dxva->loop_filter.frame_restoration_type[i], 2); - for (i = 0; i < 2; ++i) // 0:32x32, 1:64x64, 2:128x128, 3:256x256 - mpp_put_bits(&bp, dxva->loop_filter.log2_restoration_unit_size[i], 2); - - mpp_put_bits(&bp, dxva->coding.tx_mode, 2); - mpp_put_bits(&bp, dxva->coding.reference_mode, 1); - mpp_put_bits(&bp, dxva->skip_ref0, 3); - mpp_put_bits(&bp, dxva->skip_ref1, 3); - mpp_put_bits(&bp, dxva->coding.skip_mode, 1); - mpp_put_bits(&bp, dxva->coding.warped_motion, 1); - mpp_put_bits(&bp, dxva->coding.reduced_tx_set, 1); - - /* gm_type and gm_params */ - for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i) - mpp_put_bits(&bp, dxva->frame_refs[i].wmtype, 2); - - for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i) - for (j = 0; j < 6; j++) - mpp_put_bits(&bp, dxva->frame_refs[i].wmmat_val[j], 17); - - /* film_grain_params */ - { - mpp_put_bits(&bp, dxva->film_grain.apply_grain, 1); - mpp_put_bits(&bp, dxva->film_grain.grain_seed, 16); - mpp_put_bits(&bp, dxva->film_grain.update_grain, 1); - mpp_put_bits(&bp, dxva->film_grain.num_y_points, 4); - - for (i = 0; i < 14; i++) - mpp_put_bits(&bp, dxva->film_grain.scaling_points_y[i][0], 8); - - for (i = 0; i < 14; i++) - mpp_put_bits(&bp, dxva->film_grain.scaling_points_y[i][1], 8); - - mpp_put_bits(&bp, dxva->film_grain.chroma_scaling_from_luma, 1); - mpp_put_bits(&bp, dxva->film_grain.num_cb_points, 4); - - for (i = 0; i < 10; ++i) - mpp_put_bits(&bp, dxva->film_grain.scaling_points_cb[i][0], 8); - - for (i = 0; i < 10; ++i) - mpp_put_bits(&bp, dxva->film_grain.scaling_points_cb[i][1], 8); - - mpp_put_bits(&bp, dxva->film_grain.num_cr_points, 4); - for (i = 0; i < 10; ++i) - mpp_put_bits(&bp, dxva->film_grain.scaling_points_cr[i][0], 8); - - for (i = 0; i < 10; ++i) - mpp_put_bits(&bp, dxva->film_grain.scaling_points_cr[i][1], 8); - - mpp_put_bits(&bp, dxva->film_grain.scaling_shift_minus8, 2); - mpp_put_bits(&bp, dxva->film_grain.ar_coeff_lag, 2); - for (i = 0; i < 24; ++i) - mpp_put_bits(&bp, dxva->film_grain.ar_coeffs_y[i], 8); - - for (i = 0; i < 25; ++i) - mpp_put_bits(&bp, dxva->film_grain.ar_coeffs_cb[i], 8); - - for (i = 0; i < 25; ++i) - mpp_put_bits(&bp, dxva->film_grain.ar_coeffs_cr[i], 8); - - mpp_put_bits(&bp, dxva->film_grain.ar_coeff_shift_minus6, 2); - mpp_put_bits(&bp, dxva->film_grain.grain_scale_shift, 2); - mpp_put_bits(&bp, dxva->film_grain.cb_mult, 8); - mpp_put_bits(&bp, dxva->film_grain.cb_luma_mult, 8); - mpp_put_bits(&bp, dxva->film_grain.cb_offset, 9); - mpp_put_bits(&bp, dxva->film_grain.cr_mult, 8); - mpp_put_bits(&bp, dxva->film_grain.cr_luma_mult, 8); - mpp_put_bits(&bp, dxva->film_grain.cr_offset, 9); - mpp_put_bits(&bp, dxva->film_grain.overlap_flag, 1); - mpp_put_bits(&bp, dxva->film_grain.clip_to_restricted_range, 1); - } - - /* ref frame info */ - for (i = 0; i < NUM_REF_FRAMES; ++i) - mpp_put_bits(&bp, dxva->frame_ref_state[i].upscaled_width, 16); - - for (i = 0; i < NUM_REF_FRAMES; ++i) - mpp_put_bits(&bp, dxva->frame_ref_state[i].frame_height, 16); - - for (i = 0; i < NUM_REF_FRAMES; ++i) - mpp_put_bits(&bp, dxva->frame_ref_state[i].frame_width, 16); - - for (i = 0; i < NUM_REF_FRAMES; ++i) - mpp_put_bits(&bp, dxva->frame_ref_state[i].frame_type, 2); - - for (i = 0; i < NUM_REF_FRAMES; ++i) { - mpp_put_bits(&bp, dxva->frame_refs[i].lst_frame_offset, 8); - mpp_put_bits(&bp, dxva->frame_refs[i].lst2_frame_offset, 8); - mpp_put_bits(&bp, dxva->frame_refs[i].lst3_frame_offset, 8); - mpp_put_bits(&bp, dxva->frame_refs[i].gld_frame_offset, 8); - mpp_put_bits(&bp, dxva->frame_refs[i].bwd_frame_offset, 8); - mpp_put_bits(&bp, dxva->frame_refs[i].alt2_frame_offset, 8); - mpp_put_bits(&bp, dxva->frame_refs[i].alt_frame_offset, 8); - } - - { - RK_U32 mapped_idx = 0; - RK_U32 mapped_frame_width[8] = {0}; - RK_U32 mapped_frame_height[8] = {0}; - - for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++) { - mapped_idx = dxva->ref_frame_idx[i]; - mapped_frame_width[mapped_idx] = dxva->frame_ref_state[mapped_idx].frame_width; - mapped_frame_height[mapped_idx] = dxva->frame_ref_state[mapped_idx].frame_height; - } - for (i = 0; i <= ALLOWED_REFS_PER_FRAME_EX; ++i) { - RK_U32 hor_scale, ver_scale; - - if (dxva->coding.intrabc) { - hor_scale = dxva->width; - ver_scale = dxva->height; - } else { - hor_scale = mapped_frame_width[i]; - ver_scale = mapped_frame_height[i]; - } - hor_scale = ((hor_scale << AV1_REF_SCALE_SHIFT) + dxva->width / 2) / dxva->width; - ver_scale = ((ver_scale << AV1_REF_SCALE_SHIFT) + dxva->height / 2) / dxva->height; - - mpp_put_bits(&bp, hor_scale, 16); - mpp_put_bits(&bp, ver_scale, 16); - } - } - - mpp_put_bits(&bp, (dxva->frame_header_size + 7) >> 3, 10); - /* tile info */ - mpp_put_bits(&bp, dxva->tiles.cols, 7); - mpp_put_bits(&bp, dxva->tiles.rows, 7); - mpp_put_bits(&bp, dxva->tiles.context_update_id, 12); - mpp_put_bits(&bp, dxva->tiles.tile_sz_mag + 1, 3); - mpp_put_bits(&bp, dxva->tiles.cols * dxva->tiles.rows, 13); - mpp_put_bits(&bp, dxva->tile_cols_log2 + dxva->tile_rows_log2, 12); - - for (i = 0; i < 64; i++) - mpp_put_bits(&bp, dxva->tiles.widths[i], 7); - - for (i = 0; i < 64; i++) - mpp_put_bits(&bp, dxva->tiles.heights[i], 10); - - mpp_put_align(&bp, 128, 0); - - return MPP_OK; -} - static RK_S32 update_size_offset(VdpuRcbInfo *info, RK_U32 reg_idx, RK_S32 offset, RK_S32 len, RK_S32 rcb_buf_idx) { @@ -766,62 +195,6 @@ static RK_S32 update_size_offset(VdpuRcbInfo *info, RK_U32 reg_idx, return buf_size; } -#define VDPU383_SET_BUF_PROTECT_VAL(buf_p, buf_size, val, set_byte_cnt) \ -do { \ - RK_U8 *but_p_tmp = (RK_U8 *)buf_p; \ - memset(&but_p_tmp[0], val, set_byte_cnt); \ - memset(&but_p_tmp[buf_size - set_byte_cnt], val, set_byte_cnt); \ -} while (0) - -#define VDPU383_DUMP_BUF_PROTECT_VAL(buf_p, buf_size, dump_byte_cnt) \ -do { \ - RK_U32 prot_loop; \ - RK_U8 *buf_p_tmp = (RK_U8 *)buf_p; \ - printf("======> protect buffer begin\n"); \ - for (prot_loop = 0; prot_loop < dump_byte_cnt; prot_loop++) { \ - if (prot_loop % 32 == 0 && prot_loop != 0) \ - printf("\n"); \ - printf("0x%02x ", buf_p_tmp[prot_loop]); \ - } \ - printf("\n"); \ - printf("======> protect buffer end\n"); \ - for (prot_loop = 0; prot_loop < dump_byte_cnt; prot_loop++) { \ - if (prot_loop % 32 == 0 && prot_loop != 0) \ - printf("\n"); \ - printf("0x%02x ", buf_p_tmp[buf_size - 1 - prot_loop]); \ - } \ - printf("\n"); \ -} while (0) - -#if 0 -static void rcb_buf_set_edge(Vdpu38xAv1dRegCtx *reg_ctx, MppBuffer buf) -{ - RK_U32 loop; - RK_U8 *buf_p = mpp_buffer_get_ptr(buf); - - for (loop = 0; loop < RCB_BUF_CNT; loop++) { - VDPU383_SET_BUF_PROTECT_VAL(&buf_p[reg_ctx->rcb_buf_info[loop].offset], - reg_ctx->rcb_buf_info[loop].size, 0xaa, 128); - } -} - -static void rcb_buf_dump_edge(Vdpu38xAv1dRegCtx *reg_ctx, MppBuffer buf) -{ - RK_U8 *buf_p = mpp_buffer_get_ptr(buf); - RK_U32 loop; - - for (loop = 0; loop < RCB_BUF_CNT; loop++) { - // reg_ctx->rcb_buf_info[loop].reg; - // reg_ctx->rcb_buf_info[loop].offset; - // reg_ctx->rcb_buf_info[loop].size; - - printf("======> reg idx:%d\n", reg_ctx->rcb_buf_info[loop].reg); - VDPU383_DUMP_BUF_PROTECT_VAL(&buf_p[reg_ctx->rcb_buf_info[loop].offset], - reg_ctx->rcb_buf_info[loop].size, 128); - } -} -#endif - static void av1d_refine_rcb_size(VdpuRcbInfo *rcb_info, RK_S32 width, RK_S32 height, void* data) { @@ -914,9 +287,6 @@ static void vdpu383_av1d_rcb_setup(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) } mpp_buffer_get(p_hal->buf_group, &rcb_buf, reg_ctx->rcb_buf_size); reg_ctx->rcb_bufs[i] = rcb_buf; - - // rcb_buf_set_edge(reg_ctx, rcb_buf); - // rcb_buf_dump_edge(reg_ctx, rcb_buf); } return; @@ -957,192 +327,6 @@ static void vdpu383_av1d_rcb_reg_cfg(Av1dHalCtx *p_hal, MppBuffer buf) mpp_dev_set_reg_offset(p_hal->dev, reg_ctx->rcb_buf_info[i].reg_idx, reg_ctx->rcb_buf_info[i].offset); } -static MPP_RET vdpu383_av1d_colmv_setup(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) -{ - MPP_RET ret = MPP_ERR_UNKNOW; - Vdpu38xAv1dRegCtx *reg_ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx; - size_t mv_size; - - /* the worst case is the frame is error with whole frame */ - mv_size = MPP_ALIGN(dxva->width, 64) / 64 * MPP_ALIGN(dxva->height, 64) / 64 * 1024; - if (reg_ctx->colmv_bufs == NULL || reg_ctx->colmv_size < mv_size) { - if (reg_ctx->colmv_bufs) { - hal_bufs_deinit(reg_ctx->colmv_bufs); - reg_ctx->colmv_bufs = NULL; - } - - hal_bufs_init(®_ctx->colmv_bufs); - if (reg_ctx->colmv_bufs == NULL) { - mpp_err_f("colmv bufs init fail"); - goto __RETURN; - } - reg_ctx->colmv_size = mv_size; - reg_ctx->colmv_count = mpp_buf_slot_get_count(p_hal->slots); - hal_bufs_setup(reg_ctx->colmv_bufs, reg_ctx->colmv_count, 1, &mv_size); - } - -__RETURN: - return ret; -} - -static MPP_RET vdpu383_av1d_cdf_setup(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) -{ - MPP_RET ret = MPP_ERR_UNKNOW; - Vdpu38xAv1dRegCtx *reg_ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx; - size_t size = 0; - size_t segid_size = (MPP_ALIGN(dxva->width, 128) / 128) * \ - (MPP_ALIGN(dxva->height, 128) / 128) * \ - 32 * 16; - size = ALL_CDF_SIZE + segid_size; - - /* the worst case is the frame is error with whole frame */ - if (reg_ctx->cdf_segid_bufs == NULL || reg_ctx->cdf_segid_size < size) { - if (reg_ctx->cdf_segid_bufs) { - hal_bufs_deinit(reg_ctx->cdf_segid_bufs); - reg_ctx->cdf_segid_bufs = NULL; - } - - hal_bufs_init(®_ctx->cdf_segid_bufs); - if (reg_ctx->cdf_segid_bufs == NULL) { - mpp_err_f("cdf bufs init fail"); - goto __RETURN; - } - - reg_ctx->cdf_segid_size = size; - reg_ctx->cdf_segid_count = mpp_buf_slot_get_count(p_hal->slots); - hal_bufs_setup(reg_ctx->cdf_segid_bufs, reg_ctx->cdf_segid_count, 1, &size); - } - -__RETURN: - return ret; -} - -/* - * cdf buf structure: - * - * base_addr0 +--------------------------+ - * 434x128bit | def_non_coeff_cdf | - * base_addr0+433 +--------------------------+ - * - * base_addr1 +--------------------------+ - * 354x128bit | def_coeff_cdf_0 | - * | (base_q_idx <= 20) | - * +--------------------------+ - * 354x128bit | def_coeff_cdf_1 | - * | (20 < base_q_idx <= 60) | - * +--------------------------+ - * 354x128bit | def_coeff_cdf_2 | - * | (60 < base_q_idx <= 120) | - * +--------------------------+ - * 354x128bit | def_coeff_cdf_3 | - * | (base_q_idx > 120) | - * base_addr1+1415 +--------------------------+ - */ - -static void vdpu383_av1d_set_cdf(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) -{ - Vdpu38xAv1dRegCtx *reg_ctx = (Vdpu38xAv1dRegCtx *)p_hal->reg_ctx; - Vdpu383Av1dRegSet *regs = reg_ctx->regs; - RK_U32 coeff_cdf_idx = 0; - RK_U32 mapped_idx = 0; - HalBuf *cdf_buf = NULL; - RK_U32 i = 0; - MppBuffer buf_tmp = NULL; - - /* use para in decoder */ -#ifdef DUMP_AV1D_VDPU383_DATAS - { - char *cur_fname = "cabac_cdf_in.dat"; - memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path)); - sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname); - } -#endif - if (dxva->format.frame_type == AV1_FRAME_KEY) - for (i = 0; i < NUM_REF_FRAMES; i++) - reg_ctx->ref_info_tbl[i].cdf_valid = 0; - /* def coeff cdf idx */ - coeff_cdf_idx = dxva->quantization.base_qindex <= 20 ? 0 : - dxva->quantization.base_qindex <= 60 ? 1 : - dxva->quantization.base_qindex <= 120 ? 2 : 3; - - if (dxva->format.frame_type == AV1_FRAME_KEY || - dxva->primary_ref_frame == AV1_PRIMARY_REF_NONE) { - regs->av1d_addrs.reg184_av1_noncoef_rd_base = mpp_buffer_get_fd(reg_ctx->cdf_rd_def_base); - regs->av1d_addrs.reg178_av1_coef_rd_base = mpp_buffer_get_fd(reg_ctx->cdf_rd_def_base); -#ifdef DUMP_AV1D_VDPU383_DATAS - { - dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(reg_ctx->cdf_rd_def_base), - 8 * NON_COEF_CDF_SIZE, 128, 0, 0); - dump_data_to_file(dump_cur_fname_path, (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->cdf_rd_def_base) - + NON_COEF_CDF_SIZE + COEF_CDF_SIZE * coeff_cdf_idx, - 8 * COEF_CDF_SIZE, 128, 0, 1); - } -#endif - } else { - mapped_idx = dxva->ref_frame_idx[dxva->primary_ref_frame]; - - coeff_cdf_idx = reg_ctx->ref_info_tbl[mapped_idx].coeff_idx; - if (!dxva->coding.disable_frame_end_update_cdf && - reg_ctx->ref_info_tbl[mapped_idx].cdf_valid && - dxva->frame_refs[mapped_idx].Index != (CHAR)0xff && - dxva->frame_refs[mapped_idx].Index != 0x7f) { - cdf_buf = hal_bufs_get_buf(reg_ctx->cdf_segid_bufs, dxva->frame_refs[mapped_idx].Index); - buf_tmp = cdf_buf->buf[0]; - } else { - buf_tmp = reg_ctx->cdf_rd_def_base; - } - regs->av1d_addrs.reg184_av1_noncoef_rd_base = mpp_buffer_get_fd(buf_tmp); - regs->av1d_addrs.reg178_av1_coef_rd_base = mpp_buffer_get_fd(buf_tmp); - regs->av1d_addrs.reg181_av1_rd_segid_base = mpp_buffer_get_fd(buf_tmp); -#ifdef DUMP_AV1D_VDPU383_DATAS - { - dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(buf_tmp), - 8 * NON_COEF_CDF_SIZE, 128, 0, 0); - dump_data_to_file(dump_cur_fname_path, (RK_U8 *)mpp_buffer_get_ptr(buf_tmp) - + NON_COEF_CDF_SIZE + COEF_CDF_SIZE * coeff_cdf_idx, - 8 * COEF_CDF_SIZE, 128, 0, 1); - } -#endif - } - cdf_buf = hal_bufs_get_buf(reg_ctx->cdf_segid_bufs, dxva->CurrPic.Index7Bits); - regs->av1d_addrs.reg185_av1_noncoef_wr_base = mpp_buffer_get_fd(cdf_buf->buf[0]); - regs->av1d_addrs.reg179_av1_coef_wr_base = mpp_buffer_get_fd(cdf_buf->buf[0]); - regs->av1d_addrs.reg182_av1_wr_segid_base = mpp_buffer_get_fd(cdf_buf->buf[0]); - - /* byte, 434 x 128 bit = 434 x 16 byte */ - mpp_dev_set_reg_offset(p_hal->dev, 178, NON_COEF_CDF_SIZE + COEF_CDF_SIZE * coeff_cdf_idx); - mpp_dev_set_reg_offset(p_hal->dev, 179, NON_COEF_CDF_SIZE); - mpp_dev_set_reg_offset(p_hal->dev, 181, ALL_CDF_SIZE); - mpp_dev_set_reg_offset(p_hal->dev, 182, ALL_CDF_SIZE); - - /* update params sync with "update buffer" */ - for (i = 0; i < NUM_REF_FRAMES; i++) { - if (dxva->refresh_frame_flags & (1 << i)) { - if (dxva->coding.disable_frame_end_update_cdf) { - if (dxva->show_existing_frame && dxva->format.frame_type == AV1_FRAME_KEY) - reg_ctx->ref_info_tbl[i].coeff_idx - = reg_ctx->ref_info_tbl[dxva->frame_to_show_map_idx].coeff_idx; - else - reg_ctx->ref_info_tbl[i].coeff_idx = coeff_cdf_idx; - } else { - reg_ctx->ref_info_tbl[i].cdf_valid = 1; - reg_ctx->ref_info_tbl[i].coeff_idx = 0; - } - } - } - -#ifdef DUMP_AV1D_VDPU383_DATAS - { - char *cur_fname = "cdf_rd_def.dat"; - memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path)); - sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname); - dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(reg_ctx->cdf_rd_def_base), - (NON_COEF_CDF_SIZE + COEF_CDF_SIZE * 4) * 8, 128, 0, 0); - } -#endif - -} - MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task) { MPP_RET ret = MPP_ERR_UNKNOW; @@ -1168,7 +352,7 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task) mpp_buf_slot_get_prop(p_hal->slots, dxva->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe); if (mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY && MPP_MAX(dxva->width, dxva->height) > 4096 && ctx->origin_bufs == NULL) { - vdpu383_setup_scale_origin_bufs(p_hal, mframe); + vdpu38x_setup_scale_origin_bufs(mframe, &ctx->origin_bufs); } if (p_hal->fast_mode) { @@ -1186,15 +370,15 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task) memset(regs, 0, sizeof(*regs)); p_hal->strm_len = (RK_S32)mpp_packet_get_length(task->dec.input_packet); -#ifdef DUMP_AV1D_VDPU383_DATAS +#ifdef DUMP_VDPU38X_DATAS { - memset(dump_cur_dir, 0, sizeof(dump_cur_dir)); - sprintf(dump_cur_dir, "av1/Frame%04d", dump_cur_frame); - if (access(dump_cur_dir, 0)) { - if (mkdir(dump_cur_dir)) - mpp_err_f("error: mkdir %s\n", dump_cur_dir); + memset(vdpu38x_dump_cur_dir, 0, sizeof(vdpu38x_dump_cur_dir)); + sprintf(vdpu38x_dump_cur_dir, "av1/Frame%04d", vdpu38x_dump_cur_frm); + if (access(vdpu38x_dump_cur_dir, 0)) { + if (mkdir(vdpu38x_dump_cur_dir)) + mpp_err_f("error: mkdir %s\n", vdpu38x_dump_cur_dir); } - dump_cur_frame++; + vdpu38x_dump_cur_frm++; } #endif @@ -1246,18 +430,18 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task) MppBuffer mbuffer = NULL; /* uncompress header data */ - prepare_uncompress_header(p_hal, dxva, (RK_U64 *)ctx->header_data, VDPU383_UNCMPS_HEADER_SIZE / 8); + vdpu38x_av1d_uncomp_hdr(p_hal, dxva, (RK_U64 *)ctx->header_data, VDPU383_UNCMPS_HEADER_SIZE / 8); memcpy((char *)ctx->bufs_ptr, (void *)ctx->header_data, VDPU383_UNCMPS_HEADER_SIZE); regs->av1d_paras.reg67_global_len = VDPU383_UNCMPS_HEADER_SIZE / 16; // 128 bit as unit regs->common_addr.reg131_gbl_base = ctx->bufs_fd; // mpp_dev_set_reg_offset(p_hal->dev, 131, ctx->offset_uncomps); -#ifdef DUMP_AV1D_VDPU383_DATAS +#ifdef DUMP_VDPU38X_DATAS { char *cur_fname = "global_cfg.dat"; - memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path)); - sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname); - dump_data_to_file(dump_cur_fname_path, ctx->bufs_ptr, - 8 * regs->av1d_paras.reg67_global_len * 16, 64, 0, 0); + memset(vdpu38x_dump_cur_fname_path, 0, sizeof(vdpu38x_dump_cur_fname_path)); + sprintf(vdpu38x_dump_cur_fname_path, "%s/%s", vdpu38x_dump_cur_dir, cur_fname); + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, ctx->bufs_ptr, + 8 * regs->av1d_paras.reg67_global_len * 16, 64, 0, 0); } #endif // input strm @@ -1269,21 +453,21 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task) mpp_dev_set_reg_offset(p_hal->dev, 128, ctx->offset_uncomps & 0xfffffff0); /* error */ regs->av1d_addrs.reg169_error_ref_base = mpp_buffer_get_fd(mbuffer); -#ifdef DUMP_AV1D_VDPU383_DATAS +#ifdef DUMP_VDPU38X_DATAS { char *cur_fname = "stream_in.dat"; - memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path)); - sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname); - dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer) - + ctx->offset_uncomps, - 8 * p_hal->strm_len, 128, 0, 0); + memset(vdpu38x_dump_cur_fname_path, 0, sizeof(vdpu38x_dump_cur_fname_path)); + sprintf(vdpu38x_dump_cur_fname_path, "%s/%s", vdpu38x_dump_cur_dir, cur_fname); + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer) + + ctx->offset_uncomps, + 8 * p_hal->strm_len, 128, 0, 0); } { char *cur_fname = "stream_in_no_offset.dat"; - memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path)); - sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname); - dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer), - 8 * p_hal->strm_len, 128, 0, 0); + memset(vdpu38x_dump_cur_fname_path, 0, sizeof(vdpu38x_dump_cur_fname_path)); + sprintf(vdpu38x_dump_cur_fname_path, "%s/%s", vdpu38x_dump_cur_dir, cur_fname); + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer), + 8 * p_hal->strm_len, 128, 0, 0); } #endif } @@ -1362,7 +546,6 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task) mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_BUFFER, &mbuffer); regs->av1d_addrs.reg168_decout_base = mpp_buffer_get_fd(mbuffer); regs->av1d_addrs.reg192_payload_st_cur_base = mpp_buffer_get_fd(mbuffer); - // VDPU383_SET_BUF_PROTECT_VAL(mpp_buffer_get_ptr(mbuffer), mpp_buffer_get_size(mbuffer), 0xbb, 128); for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++) { mapped_idx = dxva->ref_frame_idx[i]; @@ -1380,33 +563,37 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task) } HalBuf *mv_buf = NULL; - vdpu383_av1d_colmv_setup(p_hal, dxva); + vdpu38x_av1d_colmv_setup(p_hal, dxva); mv_buf = hal_bufs_get_buf(ctx->colmv_bufs, dxva->CurrPic.Index7Bits); regs->av1d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]); -#ifdef DUMP_AV1D_VDPU383_DATAS +#ifdef DUMP_VDPU38X_DATAS memset(mpp_buffer_get_ptr(mv_buf->buf[0]), 0, mpp_buffer_get_size(mv_buf->buf[0])); #endif for (i = 0; i < NUM_REF_FRAMES; i++) { if (dxva->frame_refs[i].Index != (CHAR)0xff && dxva->frame_refs[i].Index != 0x7f) { mv_buf = hal_bufs_get_buf(ctx->colmv_bufs, dxva->frame_refs[i].Index); regs->av1d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]); -#ifdef DUMP_AV1D_VDPU383_DATAS +#ifdef DUMP_VDPU38X_DATAS { char *cur_fname = "colmv_ref_frame"; - memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path)); - sprintf(dump_cur_fname_path, "%s/%s%d.dat", dump_cur_dir, cur_fname, i); - dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mv_buf->buf[0]), - 8 * mpp_buffer_get_size(mv_buf->buf[0]), 64, 0, 0); + memset(vdpu38x_dump_cur_fname_path, 0, sizeof(vdpu38x_dump_cur_fname_path)); + sprintf(vdpu38x_dump_cur_fname_path, "%s/%s%d.dat", vdpu38x_dump_cur_dir, cur_fname, i); + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mv_buf->buf[0]), + 8 * mpp_buffer_get_size(mv_buf->buf[0]), 64, 0, 0); } #endif } } } - { - vdpu383_av1d_cdf_setup(p_hal, dxva); - vdpu383_av1d_set_cdf(p_hal, dxva); - } + vdpu38x_av1d_cdf_setup(p_hal, dxva); + vdpu38x_av1d_set_cdf_segid(p_hal, dxva, + ®s->av1d_addrs.reg178_av1_coef_rd_base, + ®s->av1d_addrs.reg179_av1_coef_wr_base, + ®s->av1d_addrs.reg181_av1_rd_segid_base, + ®s->av1d_addrs.reg182_av1_wr_segid_base, + ®s->av1d_addrs.reg184_av1_noncoef_rd_base, + ®s->av1d_addrs.reg185_av1_noncoef_wr_base); mpp_buffer_sync_end(ctx->bufs); { @@ -1487,7 +674,7 @@ MPP_RET vdpu383_av1d_start(void *hal, HalTaskInfo *task) wr_cfg.reg = ®s->av1d_paras; wr_cfg.size = sizeof(regs->av1d_paras); - wr_cfg.offset = OFFSET_AV1D_PARAS_REGS; + wr_cfg.offset = OFFSET_CODEC_PARAS_REGS; ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); if (ret) { mpp_err_f("set register write failed %d\n", ret); @@ -1496,7 +683,7 @@ MPP_RET vdpu383_av1d_start(void *hal, HalTaskInfo *task) wr_cfg.reg = ®s->av1d_addrs; wr_cfg.size = sizeof(regs->av1d_addrs); - wr_cfg.offset = OFFSET_AV1D_ADDR_REGS; + wr_cfg.offset = OFFSET_CODEC_ADDR_REGS; ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); if (ret) { mpp_err_f("set register write failed %d\n", ret); @@ -1537,25 +724,25 @@ MPP_RET vdpu383_av1d_wait(void *hal, HalTaskInfo *task) Vdpu383Av1dRegSet *p_regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs; -#ifdef DUMP_AV1D_VDPU383_DATAS +#ifdef DUMP_VDPU38X_DATAS { char *cur_fname = "colmv_cur_frame.dat"; DXVA_PicParams_AV1 *dxva = (DXVA_PicParams_AV1*)task->dec.syntax.data; HalBuf *mv_buf = NULL; mv_buf = hal_bufs_get_buf(reg_ctx->colmv_bufs, dxva->CurrPic.Index7Bits); - memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path)); - sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname); - dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mv_buf->buf[0]), - 8 * mpp_buffer_get_size(mv_buf->buf[0]), 64, 0, 0); + memset(vdpu38x_dump_cur_fname_path, 0, sizeof(vdpu38x_dump_cur_fname_path)); + sprintf(vdpu38x_dump_cur_fname_path, "%s/%s", vdpu38x_dump_cur_dir, cur_fname); + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mv_buf->buf[0]), + 8 * mpp_buffer_get_size(mv_buf->buf[0]), 64, 0, 0); } { char *cur_fname = "decout.dat"; MppBuffer mbuffer = NULL; mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_BUFFER, &mbuffer); - memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path)); - sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname); - dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer), - 8 * mpp_buffer_get_size(mbuffer), 128, 0, 0); + memset(vdpu38x_dump_cur_fname_path, 0, sizeof(vdpu38x_dump_cur_fname_path)); + sprintf(vdpu38x_dump_cur_fname_path, "%s/%s", vdpu38x_dump_cur_dir, cur_fname); + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer), + 8 * mpp_buffer_get_size(mbuffer), 128, 0, 0); } #endif @@ -1564,26 +751,19 @@ MPP_RET vdpu383_av1d_wait(void *hal, HalTaskInfo *task) goto __SKIP_HARD; } - // rcb_buf_dump_edge(reg_ctx, p_hal->fast_mode ? reg_ctx->rcb_bufs[task->dec.reg_index] : reg_ctx->rcb_bufs[0]); - // { - // MppBuffer mbuffer = NULL; - // mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_BUFFER, &mbuffer); - // VDPU383_DUMP_BUF_PROTECT_VAL(mpp_buffer_get_ptr(mbuffer), mpp_buffer_get_size(mbuffer), 128); - // } - ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL); if (ret) mpp_err_f("poll cmd failed %d\n", ret); -#ifdef DUMP_AV1D_VDPU383_DATAS +#ifdef DUMP_VDPU38X_DATAS { char *cur_fname = "cabac_cdf_out.dat"; HalBuf *cdf_buf = NULL; DXVA_PicParams_AV1 *dxva = (DXVA_PicParams_AV1*)task->dec.syntax.data; - memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path)); - sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname); + memset(vdpu38x_dump_cur_fname_path, 0, sizeof(vdpu38x_dump_cur_fname_path)); + sprintf(vdpu38x_dump_cur_fname_path, "%s/%s", vdpu38x_dump_cur_dir, cur_fname); cdf_buf = hal_bufs_get_buf(reg_ctx->cdf_segid_bufs, dxva->CurrPic.Index7Bits); - dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(cdf_buf->buf[0]), - (NON_COEF_CDF_SIZE + COEF_CDF_SIZE) * 8, 128, 0, 0); + vdpu38x_dump_data_to_file(vdpu38x_dump_cur_fname_path, (void *)mpp_buffer_get_ptr(cdf_buf->buf[0]), + (NON_COEF_CDF_SIZE + COEF_CDF_SIZE) * 8, 128, 0, 0); } #endif @@ -1611,66 +791,6 @@ __RETURN: return ret = MPP_OK; } -MPP_RET vdpu383_av1d_reset(void *hal) -{ - MPP_RET ret = MPP_ERR_UNKNOW; - Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; - - INP_CHECK(ret, NULL == p_hal); - - -__RETURN: - return ret = MPP_OK; -} - -MPP_RET vdpu383_av1d_flush(void *hal) -{ - MPP_RET ret = MPP_ERR_UNKNOW; - Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; - - INP_CHECK(ret, NULL == p_hal); - -__RETURN: - return ret = MPP_OK; -} - -MPP_RET vdpu383_av1d_control(void *hal, MpiCmd cmd_type, void *param) -{ - Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; - MPP_RET ret = MPP_ERR_UNKNOW; - - INP_CHECK(ret, NULL == p_hal); - - switch ((MpiCmd)cmd_type) { - case MPP_DEC_SET_FRAME_INFO : { - MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param); - RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param); - RK_U32 imgheight = mpp_frame_get_height((MppFrame)param); - - AV1D_DBG(AV1D_DBG_LOG, "control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight); - if ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV422SP) { - mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, mpp_align_wxh2yuv422); - } - if (MPP_FRAME_FMT_IS_FBC(fmt)) { - vdpu383_afbc_align_calc(p_hal->slots, (MppFrame)param, 16); - } else if (imgwidth > 1920 || imgheight > 1088) { - mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64); - } - break; - } - case MPP_DEC_GET_THUMBNAIL_FRAME_INFO: { - vdpu383_update_thumbnail_frame_info((MppFrame)param); - } break; - case MPP_DEC_SET_OUTPUT_FORMAT : { - } break; - default : { - } break; - } - -__RETURN: - return ret = MPP_OK; -} - const MppHalApi hal_av1d_vdpu383 = { .name = "av1d_vdpu383", .type = MPP_CTX_DEC, @@ -1678,11 +798,11 @@ const MppHalApi hal_av1d_vdpu383 = { .ctx_size = sizeof(Vdpu38xAv1dRegCtx) + VDPU383_UNCMPS_HEADER_SIZE, .flag = 0, .init = vdpu383_av1d_init, - .deinit = vdpu383_av1d_deinit, + .deinit = vdpu38x_av1d_deinit, .reg_gen = vdpu383_av1d_gen_regs, .start = vdpu383_av1d_start, .wait = vdpu383_av1d_wait, - .reset = vdpu383_av1d_reset, - .flush = vdpu383_av1d_flush, - .control = vdpu383_av1d_control, + .reset = vdpu38x_av1d_reset, + .flush = vdpu38x_av1d_flush, + .control = vdpu38x_av1d_control, }; diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c index 030caa69..4b5fc402 100644 --- a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c +++ b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c @@ -23,6 +23,7 @@ #include "hal_avs2d_vdpu383.h" #include "mpp_dec_cb_param.h" #include "vdpu_com.h" +#include "vdpu38x_com.h" #include "hal_avs2d_ctx.h" #define MAX_REF_NUM (8) diff --git a/mpp/hal/rkdec/common/vdpu38x_com.c b/mpp/hal/rkdec/common/vdpu38x_com.c index fea9c3ea..70e03f52 100644 --- a/mpp/hal/rkdec/common/vdpu38x_com.c +++ b/mpp/hal/rkdec/common/vdpu38x_com.c @@ -632,6 +632,31 @@ void vdpu38x_setup_down_scale(MppFrame frame, MppDev dev, Vdpu38xCtrlReg *com, v } } +MPP_RET vdpu38x_setup_scale_origin_bufs(MppFrame mframe, HalBufs *org_bufs) +{ + /* for 8K FrameBuf scale mode */ + size_t origin_buf_size = 0; + + origin_buf_size = mpp_frame_get_buf_size(mframe); + + if (!origin_buf_size) { + mpp_err_f("origin_bufs get buf size failed\n"); + return MPP_NOK; + } + if (*org_bufs) { + hal_bufs_deinit(*org_bufs); + *org_bufs = NULL; + } + hal_bufs_init(org_bufs); + if (!(*org_bufs)) { + mpp_err_f("org_bufs init fail\n"); + return MPP_ERR_NOMEM; + } + hal_bufs_setup(*org_bufs, 16, 1, &origin_buf_size); + + return MPP_OK; +} + #ifdef DUMP_VDPU38X_DATAS RK_U32 vdpu38x_dump_cur_frm = 0; char vdpu38x_dump_cur_dir[128]; diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c index fdddf758..5d10a7ee 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c @@ -18,6 +18,7 @@ #include "vdpu383_h264d.h" #include "mpp_dec_cb_param.h" #include "vdpu_com.h" +#include "vdpu38x_com.h" #include "hal_h264d_ctx.h" /* Number registers for the decoder */ diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu384a.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu384a.c index b1dd65ce..70149105 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu384a.c +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu384a.c @@ -18,6 +18,7 @@ #include "vdpu384a_h264d.h" #include "mpp_dec_cb_param.h" #include "vdpu_com.h" +#include "vdpu38x_com.h" #include "hal_h264d_ctx.h" /* Number registers for the decoder */ diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c index 5d2377ee..0fccf85c 100644 --- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c +++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c @@ -28,6 +28,7 @@ #include "vdpu383_h265d.h" #include "vdpu383_com.h" #include "vdpu_com.h" +#include "vdpu38x_com.h" #define HW_RPS #define PPS_SIZE (112 * 64)//(96x64) diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu384a.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu384a.c index 7810b41c..a37a7cdb 100644 --- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu384a.c +++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu384a.c @@ -28,6 +28,7 @@ #include "vdpu384a_h265d.h" #include "vdpu384a_com.h" #include "vdpu_com.h" +#include "vdpu38x_com.h" #define PPS_SIZE (112 * 64)//(96x64) diff --git a/mpp/hal/rkdec/inc/vdpu383_com.h b/mpp/hal/rkdec/inc/vdpu383_com.h index e2d8feeb..b510f143 100644 --- a/mpp/hal/rkdec/inc/vdpu383_com.h +++ b/mpp/hal/rkdec/inc/vdpu383_com.h @@ -10,13 +10,6 @@ #include "mpp_buf_slot.h" #include "vdpu_com.h" -#define OFFSET_CTRL_REGS (8 * sizeof(RK_U32)) -#define OFFSET_COMMON_ADDR_REGS (128 * sizeof(RK_U32)) -#define OFFSET_COM_NEW_REGS (320 * sizeof(RK_U32)) -#define OFFSET_CODEC_PARAS_REGS (64 * sizeof(RK_U32)) -#define OFFSET_CODEC_ADDR_REGS (168 * sizeof(RK_U32)) -#define OFFSET_INTERRUPT_REGS (15 * sizeof(RK_U32)) - // #define DUMP_VDPU383_DATAS typedef struct Vdpu383RegVersion_t { diff --git a/mpp/hal/rkdec/inc/vdpu384a_com.h b/mpp/hal/rkdec/inc/vdpu384a_com.h index fa23052f..c168b52f 100644 --- a/mpp/hal/rkdec/inc/vdpu384a_com.h +++ b/mpp/hal/rkdec/inc/vdpu384a_com.h @@ -10,17 +10,11 @@ #include "mpp_buf_slot.h" #include "vdpu_com.h" -#define OFFSET_CTRL_REGS (8 * sizeof(RK_U32)) -#define OFFSET_COMMON_ADDR_REGS (128 * sizeof(RK_U32)) -#define OFFSET_COM_NEW_REGS (320 * sizeof(RK_U32)) -#define OFFSET_CODEC_PARAS_REGS (64 * sizeof(RK_U32)) -#define OFFSET_CODEC_ADDR_REGS (168 * sizeof(RK_U32)) -#define OFFSET_INTERRUPT_REGS (15 * sizeof(RK_U32)) - // #define DUMP_VDPU384A_DATAS typedef struct Vdpu384aRegVersion_t { - struct SWREG0_ID { + /* SWREG0_ID */ + struct { RK_U32 minor_ver : 8; RK_U32 major_ver : 8; RK_U32 prod_num : 16; @@ -32,7 +26,8 @@ typedef struct Vdpu384aCtrlReg_t { /* SWREG8_DEC_MODE */ RK_U32 reg8_dec_mode; - struct SWREG9_IMPORTANT_EN { + /* SWREG9_IMPORTANT_EN */ + struct { RK_U32 dpb_output_dis : 1; /* * 0: dpb data use rkfbc64x4 channel @@ -67,7 +62,8 @@ typedef struct Vdpu384aCtrlReg_t { RK_U32 reserve4 : 6; } reg9; - struct SWREG10_BLOCK_GATING_EN { + /* SWREG10_BLOCK_GATING_EN */ + struct { RK_U32 strmd_auto_gating_e : 1; RK_U32 inter_auto_gating_e : 1; RK_U32 intra_auto_gating_e : 1; @@ -81,7 +77,8 @@ typedef struct Vdpu384aCtrlReg_t { RK_U32 reserve0 : 22; } reg10; - struct SWREG11_CFG_PARA { + /* SWREG11_CFG_PARA */ + struct { RK_U32 frame_irq_dis : 1; RK_U32 reserve0 : 8; RK_U32 dec_timeout_dis : 1; @@ -90,7 +87,8 @@ typedef struct Vdpu384aCtrlReg_t { RK_U32 wr_outstanding : 8; } reg11; - struct SWREG12_CACHE_HASH_MASK { + /* SWREG12_CACHE_HASH_MASK */ + struct { RK_U32 reserve0 : 7; RK_U32 cache_hash_mask : 25; } reg12; @@ -98,13 +96,15 @@ typedef struct Vdpu384aCtrlReg_t { /* SWREG13_CORE_TIMEOUT_THRESHOLD */ RK_U32 reg13_core_timeout_threshold; - struct SWREG14_LINE_IRQ_CTRL { + /* SWREG14_LINE_IRQ_CTRL */ + struct { RK_U32 dec_line_irq_step : 16; RK_U32 dec_line_offset_y_st : 16; } reg14; /* copy from llp, media group add */ - struct SWREG15_IRQ_STA { + /* SWREG15_IRQ_STA */ + struct { RK_U32 rkvdec_frame_rdy_sta : 1; RK_U32 rkvdec_strm_error_sta : 1; RK_U32 rkvdec_core_timeout_sta : 1; @@ -125,7 +125,8 @@ typedef struct Vdpu384aCtrlReg_t { RK_U32 reserve0 : 1; } reg15; - struct SWREG16_ERROR_CTRL_SET { + /* SWREG16_ERROR_CTRL_SET */ + struct { RK_U32 error_proc_disable : 1; RK_U32 reserve0 : 3; RK_U32 error_proc_mode : 1; @@ -137,21 +138,24 @@ typedef struct Vdpu384aCtrlReg_t { RK_U32 reserve3 : 7; } reg16; - struct SWREG17_ERR_ROI_CTU_OFFSET_START { + /* SWREG17_ERR_ROI_CTU_OFFSET_START */ + struct { RK_U32 roi_x_ctu_offset_st : 12; RK_U32 reserve0 : 4; RK_U32 roi_y_ctu_offset_st : 12; RK_U32 reserve1 : 4; } reg17; - struct SWREG18_ERR_ROI_CTU_OFFSET_END { + /* SWREG18_ERR_ROI_CTU_OFFSET_END */ + struct { RK_U32 roi_x_ctu_offset_end : 12; RK_U32 reserve0 : 4; RK_U32 roi_y_ctu_offset_end : 12; RK_U32 reserve1 : 4; } reg18; - struct SWREG19_ERROR_REF_INFO { + /* SWREG19_ERROR_REF_INFO */ + struct { RK_U32 avs2_ref_error_field : 1; RK_U32 avs2_ref_error_topfield : 1; RK_U32 ref_error_topfield_used : 1; @@ -167,7 +171,8 @@ typedef struct Vdpu384aCtrlReg_t { RK_U32 reserve_reg22; - struct SWREG23_INVALID_PIXEL_FILL { + /* SWREG23_INVALID_PIXEL_FILL */ + struct { RK_U32 fill_y : 10; RK_U32 fill_u : 10; RK_U32 fill_v : 10; @@ -176,7 +181,8 @@ typedef struct Vdpu384aCtrlReg_t { RK_U32 reserve_reg24_27[4]; - struct SWREG28_DEBUG_PERF_LATENCY_CTRL0 { + /* SWREG28_DEBUG_PERF_LATENCY_CTRL0 */ + struct { RK_U32 axi_perf_work_e : 1; RK_U32 reserve0 : 2; RK_U32 axi_cnt_type : 1; @@ -186,7 +192,8 @@ typedef struct Vdpu384aCtrlReg_t { RK_U32 reserve2 : 4; } reg28; - struct SWREG29_DEBUG_PERF_LATENCY_CTRL1 { + /* SWREG29_DEBUG_PERF_LATENCY_CTRL1 */ + struct { RK_U32 addr_align_type : 2; RK_U32 ar_cnt_id_type : 1; RK_U32 aw_cnt_id_type : 1; @@ -197,7 +204,8 @@ typedef struct Vdpu384aCtrlReg_t { RK_U32 reserve1 : 7; } reg29; - struct SWREG30_QOS_CTRL { + /* SWREG30_QOS_CTRL */ + struct { RK_U32 axi_wr_qos_level : 4; RK_U32 reserve0 : 4; RK_U32 axi_wr_qos : 4; @@ -429,7 +437,8 @@ typedef struct Vdpu384aRegCommParas_t { } Vdpu384aRegCommParas; typedef struct Vdpu384aRegStatistic_t { - struct SWREG256_IDLE_FLAG { + /* SWREG256_IDLE_FLAG */ + struct { RK_U32 reserve0 : 24; RK_U32 rkvdec_bus_idle_flag : 1; RK_U32 reserve1 : 7; @@ -465,19 +474,22 @@ typedef struct Vdpu384aRegStatistic_t { /* SWREG285_PAYLOAD_CNT */ RK_U32 reg285_filterd_payload_total_cnt; - struct SWREG286_WR_OFFSET { + /* SWREG286_WR_OFFSET */ + struct { RK_U32 filterd_report_offsety : 16; RK_U32 filterd_report_offsetx : 16; } reg286; - struct SWREG287_MAX_PIX { + /* SWREG287_MAX_PIX */ + struct { RK_U32 filterd_max_y : 10; RK_U32 filterd_max_u : 10; RK_U32 filterd_max_v : 10; RK_U32 reserve0 : 2; } reg287; - struct SWREG288_MIN_PIX { + /* SWREG288_MIN_PIX */ + struct { RK_U32 filterd_min_y : 10; RK_U32 filterd_min_u : 10; RK_U32 filterd_min_v : 10; @@ -489,7 +501,8 @@ typedef struct Vdpu384aRegStatistic_t { RK_U32 reserve_reg290_291[2]; - struct SWREG292_RCB_RW_SUM { + /* SWREG292_RCB_RW_SUM */ + struct { RK_U32 rcb_rd_sum_chk : 8; RK_U32 rcb_wr_sum_chk : 8; RK_U32 reserve0 : 16; @@ -497,7 +510,8 @@ typedef struct Vdpu384aRegStatistic_t { RK_U32 reserve_reg293; - struct SWREG294_ERR_CTU_NUM0 { + /* SWREG294_ERR_CTU_NUM0 */ + struct { RK_U32 error_ctu_num : 24; RK_U32 roi_error_ctu_num_lowbit : 8; } reg294; @@ -508,7 +522,8 @@ typedef struct Vdpu384aRegStatistic_t { } Vdpu384aRegStatistic; typedef struct Vdpu384aRegLlp_t { - struct SWREG0_LINK_MODE { + /* SWREG0_LINK_MODE */ + struct { RK_U32 llp_mmu_zap_cache_dis : 1; RK_U32 reserve0 : 15; RK_U32 core_work_mode : 1; @@ -518,12 +533,14 @@ typedef struct Vdpu384aRegLlp_t { RK_U32 reserve2 : 10; } reg0; - struct SWREG1_CFG_START_ADDR { + /* SWREG1_CFG_START_ADDR */ + struct { RK_U32 reserve0 : 4; RK_U32 reg_cfg_addr : 28; } reg1; - struct SWREG2_LINK_MODE { + /* SWREG2_LINK_MODE */ + struct { RK_U32 pre_frame_num : 30; RK_U32 reserve0 : 1; RK_U32 link_mode : 1; @@ -555,7 +572,8 @@ typedef struct Vdpu384aRegLlp_t { /* SWREG17_SOFT_RST */ RK_U32 reg17_rkvdec_ip_rst_p; - struct SWREG18_IRQ { + /* SWREG18_IRQ */ + struct { RK_U32 rkvdec_irq : 1; RK_U32 rkvdec_line_irq : 1; RK_U32 reserve0 : 14; @@ -563,7 +581,8 @@ typedef struct Vdpu384aRegLlp_t { RK_U32 reserve1 : 14; } reg18; - struct SWREG19_STA { + /* SWREG19_STA */ + struct { RK_U32 rkvdec_frame_rdy_sta : 1; RK_U32 rkvdec_strm_error_sta : 1; RK_U32 rkvdec_core_timeout_sta : 1; @@ -589,7 +608,8 @@ typedef struct Vdpu384aRegLlp_t { /* SWREG21_IP_TIMEOUT_THRESHOD */ RK_U32 reg21_ip_timeout_threshold; - struct SWREG22_IP_EN { + /* SWREG22_IP_EN */ + struct { RK_U32 ip_timeout_pause_flag : 1; RK_U32 reserve0 : 3; RK_U32 abnormal_auto_reset_dis : 1; @@ -607,7 +627,8 @@ typedef struct Vdpu384aRegLlp_t { RK_U32 mmu_sel : 1; } reg22; - struct SWREG23_IN_OUT { + /* SWREG23_IN_OUT */ + struct { RK_U32 endian : 1; RK_U32 swap32_e : 1; RK_U32 swap64_e : 1; diff --git a/mpp/hal/rkdec/inc/vdpu38x_com.h b/mpp/hal/rkdec/inc/vdpu38x_com.h index 12dea4f8..ef371152 100644 --- a/mpp/hal/rkdec/inc/vdpu38x_com.h +++ b/mpp/hal/rkdec/inc/vdpu38x_com.h @@ -12,14 +12,18 @@ #include "mpp_buf_slot.h" #include "vdpu_com.h" +#include "hal_bufs.h" // #define DUMP_VDPU38X_DATAS -#define OFFSET_CTRL_REGS (8 * sizeof(RK_U32)) -#define OFFSET_INTERRUPT_REGS (15 * sizeof(RK_U32)) -#define OFFSET_CODEC_PARAS_REGS (64 * sizeof(RK_U32)) -#define OFFSET_COMMON_ADDR_REGS (128 * sizeof(RK_U32)) -#define OFFSET_COM_STATISTIC_REGS (256 * sizeof(RK_U32)) +#define OFFSET_CTRL_REGS (8 * sizeof(RK_U32)) +#define OFFSET_INTERRUPT_REGS (15 * sizeof(RK_U32)) +#define OFFSET_CODEC_PARAS_REGS (64 * sizeof(RK_U32)) +#define OFFSET_COMMON_ADDR_REGS (128 * sizeof(RK_U32)) +#define OFFSET_CODEC_ADDR_REGS (168 * sizeof(RK_U32)) +#define OFFSET_COM_STATISTIC_REGS_VDPU383 (320 * sizeof(RK_U32)) +#define OFFSET_COM_STATISTIC_REGS_VDPU384A (320 * sizeof(RK_U32)) +#define OFFSET_COM_STATISTIC_REGS_VDPU384B (256 * sizeof(RK_U32)) typedef enum Vdpu38xFmt_e { MPP_HAL_FMT_YUV400 = 0, @@ -896,6 +900,7 @@ void vdpu38x_setup_statistic(Vdpu38xCtrlReg *com); void vdpu38x_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand); void vdpu38x_setup_down_scale(MppFrame frame, MppDev dev, Vdpu38xCtrlReg *com, void* comParas); void vdpu38x_update_thumbnail_frame_info(MppFrame frame); +MPP_RET vdpu38x_setup_scale_origin_bufs(MppFrame mframe, HalBufs *org_bufs); #ifdef DUMP_VDPU38X_DATAS extern RK_U32 vdpu38x_dump_cur_frm; diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c index 463b04d3..6df99a2d 100644 --- a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c +++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c @@ -22,6 +22,7 @@ #include "vdpu383_vp9d.h" #include "vp9d_syntax.h" #include "vdpu_com.h" +#include "vdpu38x_com.h" #define HW_PROB 1 #define VP9_CTU_SIZE 64 diff --git a/mpp/hal/vpu/av1d/hal_av1d_vdpu.c b/mpp/hal/vpu/av1d/hal_av1d_vdpu.c index e0d96165..cfb16c6f 100644 --- a/mpp/hal/vpu/av1d/hal_av1d_vdpu.c +++ b/mpp/hal/vpu/av1d/hal_av1d_vdpu.c @@ -653,7 +653,6 @@ static void set_ref_sign_bias(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) } #define MAX_FRAME_DISTANCE 31 -#define MAX_ACTIVE_REFS AV1_ACTIVE_REFS_EX static RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b) {