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feat[mpp_enc_cfg]: Change to object implement

Browse source 
Modification Point:
1. Use enc configure object macro.
2. Use kmpp_obj_update to sync user cfg setup.
3. Distinguish between user mode and kernel mode for enc obj.
4. EncImpl only check codec related SET_CFG result.
5. Refactor SET_CFG flow.
6. Adapter jpeg q_mode feature.

Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Signed-off-by: xiaoxu.chen <xiaoxu.chen@rock-chips.com>
Change-Id: I2856acdf863189fdaa29121ad8bc007fe90b5ab5
This commit is contained in:
Herman Chen 2025-09-10 14:47:39 +08:00 • committed by xiaoxu.chen
parent 17a370d2d0
commit 067de5647a
38 changed files with 1627 additions and 2918 deletions
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374
inc/rk_venc_cmd.h
View file

@ -1,17 +1,6 @@
/* SPDX-License-Identifier: Apache-2.0 OR MIT */
/*
* Copyright 2015 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* Copyright (c) 2015 Rockchip Electronics Co., Ltd.
*/
#ifndef __RK_VENC_CMD_H__
@ -195,57 +184,17 @@ typedef struct MppEncQueryCfg_t {
/*
* base working mode parameter
*/
typedef enum MppEncBaseCfgChange_e {
MPP_ENC_BASE_CFG_CHANGE_LOW_DELAY = (1 << 0),
MPP_ENC_BASE_CFG_CHANGE_SMART_EN = (1 << 1),
MPP_ENC_BASE_CFG_CHANGE_CODING = (1 << 2),
MPP_ENC_BASE_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncBaseCfgChange;
typedef struct MppEncBaseCfg_t {
RK_U32 change;
MppCodingType coding;
RK_S32 low_delay;
RK_S32 smart_en;
MppCodingType coding;
RK_S32 smt1_en;
RK_S32 smt3_en;
} MppEncBaseCfg;
/*
* Rate control parameter
*/
typedef enum MppEncRcCfgChange_e {
MPP_ENC_RC_CFG_CHANGE_RC_MODE = (1 << 0),
MPP_ENC_RC_CFG_CHANGE_QUALITY = (1 << 1),
MPP_ENC_RC_CFG_CHANGE_BPS = (1 << 2), /* change on bps target / max / min */
MPP_ENC_RC_CFG_CHANGE_FPS_IN = (1 << 5), /* change on fps in flex / numerator / denominator */
MPP_ENC_RC_CFG_CHANGE_FPS_OUT = (1 << 6), /* change on fps out flex / numerator / denominator */
MPP_ENC_RC_CFG_CHANGE_GOP = (1 << 7),
MPP_ENC_RC_CFG_CHANGE_SKIP_CNT = (1 << 8),
MPP_ENC_RC_CFG_CHANGE_MAX_REENC = (1 << 9),
MPP_ENC_RC_CFG_CHANGE_DROP_FRM = (1 << 10),
MPP_ENC_RC_CFG_CHANGE_MAX_I_PROP = (1 << 11),
MPP_ENC_RC_CFG_CHANGE_MIN_I_PROP = (1 << 12),
MPP_ENC_RC_CFG_CHANGE_INIT_IP_RATIO = (1 << 13),
MPP_ENC_RC_CFG_CHANGE_PRIORITY = (1 << 14),
MPP_ENC_RC_CFG_CHANGE_SUPER_FRM = (1 << 15),
/* qp related change flag */
MPP_ENC_RC_CFG_CHANGE_QP_INIT = (1 << 16),
MPP_ENC_RC_CFG_CHANGE_QP_RANGE = (1 << 17),
MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I = (1 << 18),
MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP = (1 << 19),
MPP_ENC_RC_CFG_CHANGE_QP_IP = (1 << 20),
MPP_ENC_RC_CFG_CHANGE_QP_VI = (1 << 21),
MPP_ENC_RC_CFG_CHANGE_QP_ROW = (1 << 22),
MPP_ENC_RC_CFG_CHANGE_QP_ROW_I = (1 << 23),
MPP_ENC_RC_CFG_CHANGE_DEBREATH = (1 << 24),
MPP_ENC_RC_CFG_CHANGE_HIER_QP = (1 << 25),
MPP_ENC_RC_CFG_CHANGE_ST_TIME = (1 << 26),
MPP_ENC_RC_CFG_CHANGE_REFRESH = (1 << 27),
MPP_ENC_RC_CFG_CHANGE_GOP_REF_CFG = (1 << 28),
MPP_ENC_RC_CFG_CHANGE_FQP = (1 << 29),
MPP_ENC_RC_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncRcCfgChange;
typedef enum MppEncRcQuality_e {
MPP_ENC_RC_QUALITY_WORST,
MPP_ENC_RC_QUALITY_WORSE,
@ -258,8 +207,6 @@ typedef enum MppEncRcQuality_e {
} MppEncRcQuality;
typedef struct MppEncRcCfg_t {
RK_U32 change;
/*
* rc_mode - rate control mode
*
@ -351,6 +298,8 @@ typedef struct MppEncRcCfg_t {
* etc...
*/
RK_S32 gop;
/* internal gop mode: 0 - normal P; 1 - smart P */
RK_S32 gop_mode;
void *ref_cfg;
/*
@ -430,30 +379,9 @@ typedef struct MppEncRcCfg_t {
MppEncRcRefreshMode refresh_mode;
RK_U32 refresh_num;
RK_S32 refresh_length;
RK_S32 inst_br_lvl;
} MppEncRcCfg;
typedef enum MppEncHwCfgChange_e {
/* qp related hardware config flag */
MPP_ENC_HW_CFG_CHANGE_QP_ROW = (1 << 0),
MPP_ENC_HW_CFG_CHANGE_QP_ROW_I = (1 << 1),
MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I = (1 << 2),
MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P = (1 << 3),
MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I = (1 << 4),
MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P = (1 << 5),
MPP_ENC_HW_CFG_CHANGE_MB_RC = (1 << 6),
MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS = (1 << 8),
MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS = (1 << 9),
MPP_ENC_HW_CFG_CHANGE_QBIAS_I = (1 << 10),
MPP_ENC_HW_CFG_CHANGE_QBIAS_P = (1 << 11),
MPP_ENC_HW_CFG_CHANGE_QBIAS_EN = (1 << 12),
MPP_ENC_HW_CFG_CHANGE_AQ_RNGE_ARR = (1 << 13),
MPP_ENC_HW_CFG_CHANGE_QBIAS_ARR = (1 << 14),
MPP_ENC_HW_CFG_CHANGE_FLT_STR_I = (1 << 15),
MPP_ENC_HW_CFG_CHANGE_FLT_STR_P = (1 << 16),
MPP_ENC_HW_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncHwCfgChange;
/*
* Hardware related rate control config
*
@ -461,8 +389,6 @@ typedef enum MppEncHwCfgChange_e {
* hardware behavior directly.
*/
typedef struct MppEncHwCfg_t {
RK_U32 change;
/* vepu541/vepu540 */
RK_S32 qp_delta_row; /* delta qp between two row in P frame */
RK_S32 qp_delta_row_i; /* delta qp between two row in I frame */
@ -525,25 +451,6 @@ typedef struct MppEncHwCfg_t {
/*
* Mpp preprocess parameter
*/
typedef enum MppEncPrepCfgChange_e {
MPP_ENC_PREP_CFG_CHANGE_INPUT = (1 << 0), /* change on input config */
MPP_ENC_PREP_CFG_CHANGE_FORMAT = (1 << 2), /* change on format */
/* transform parameter */
MPP_ENC_PREP_CFG_CHANGE_ROTATION = (1 << 4), /* change on rotation */
MPP_ENC_PREP_CFG_CHANGE_MIRRORING = (1 << 5), /* change on mirroring */
MPP_ENC_PREP_CFG_CHANGE_FLIP = (1 << 6), /* change on flip */
/* enhancement parameter */
MPP_ENC_PREP_CFG_CHANGE_DENOISE = (1 << 8), /* change on denoise */
MPP_ENC_PREP_CFG_CHANGE_SHARPEN = (1 << 9), /* change on denoise */
/* color related parameter */
MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE = (1 << 16), /* change on color range */
MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE = (1 << 17), /* change on color range */
MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME = (1 << 18), /* change on color primaries */
MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC = (1 << 19), /* change on color transfer */
MPP_ENC_PREP_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncPrepCfgChange;
/*
* Preprocess sharpen parameter
*
@ -576,8 +483,6 @@ typedef enum MppEncRotationCfg_e {
} MppEncRotationCfg;
typedef struct MppEncPrepCfg_t {
RK_U32 change;
/*
* Mpp encoder input data dimension config
*
@ -586,6 +491,10 @@ typedef struct MppEncPrepCfg_t {
* The output format is always YUV420. So if input is RGB then color
* conversion will be done internally
*/
/* width / height set - user set value */
RK_S32 width_set;
RK_S32 height_set;
/* width / height - final value in bitstream */
RK_S32 width;
RK_S32 height;
RK_S32 hor_stride;
@ -593,6 +502,9 @@ typedef struct MppEncPrepCfg_t {
RK_S32 max_width;
RK_S32 max_height;
/* resolution change flag */
RK_S32 change_res;
/*
* Mpp encoder input/output color config
*/
@ -692,63 +604,6 @@ typedef struct MppEncVuiCfg_t {
/*
* H.264 configurable parameter
*/
typedef enum MppEncH264CfgChange_e {
/* change on stream type */
MPP_ENC_H264_CFG_STREAM_TYPE = (1 << 0),
/* change on svc / profile / level */
MPP_ENC_H264_CFG_CHANGE_PROFILE = (1 << 1),
/* change on entropy_coding_mode / cabac_init_idc */
MPP_ENC_H264_CFG_CHANGE_ENTROPY = (1 << 2),
/* change on transform8x8_mode */
MPP_ENC_H264_CFG_CHANGE_TRANS_8x8 = (1 << 4),
/* change on constrained_intra_pred_mode */
MPP_ENC_H264_CFG_CHANGE_CONST_INTRA = (1 << 5),
/* change on chroma_cb_qp_offset/ chroma_cr_qp_offset */
MPP_ENC_H264_CFG_CHANGE_CHROMA_QP = (1 << 6),
/* change on deblock_disable / deblock_offset_alpha / deblock_offset_beta */
MPP_ENC_H264_CFG_CHANGE_DEBLOCKING = (1 << 7),
/* change on use_longterm */
MPP_ENC_H264_CFG_CHANGE_LONG_TERM = (1 << 8),
/* change on scaling_list_mode */
MPP_ENC_H264_CFG_CHANGE_SCALING_LIST = (1 << 9),
/* change on poc type */
MPP_ENC_H264_CFG_CHANGE_POC_TYPE = (1 << 10),
/* change on log2 max poc lsb minus 4 */
MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB = (1 << 11),
/* change on log2 max frame number minus 4 */
MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM = (1 << 12),
/* change on gaps_in_frame_num_value_allowed_flag */
MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM = (1 << 13),
/* change on max_qp / min_qp */
MPP_ENC_H264_CFG_CHANGE_QP_LIMIT = (1 << 16),
/* change on max_qp_i / min_qp_i */
MPP_ENC_H264_CFG_CHANGE_QP_LIMIT_I = (1 << 17),
/* change on max_qp_step */
MPP_ENC_H264_CFG_CHANGE_MAX_QP_STEP = (1 << 18),
/* change on qp_delta_ip */
MPP_ENC_H264_CFG_CHANGE_QP_DELTA = (1 << 19),
/* change on intra_refresh_mode / intra_refresh_arg */
MPP_ENC_H264_CFG_CHANGE_INTRA_REFRESH = (1 << 20),
/* change on max long-term reference frame count */
MPP_ENC_H264_CFG_CHANGE_MAX_LTR = (1 << 21),
/* change on max temporal id */
MPP_ENC_H264_CFG_CHANGE_MAX_TID = (1 << 22),
/* change on adding prefix nal */
MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX = (1 << 23),
/* change on base layer priority id */
MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID = (1 << 24),
/* change on vui */
MPP_ENC_H264_CFG_CHANGE_VUI = (1 << 28),
/* change on constraint */
MPP_ENC_H264_CFG_CHANGE_CONSTRAINT_SET = (1 << 29),
MPP_ENC_H264_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncH264CfgChange;
/* default H.264 hardware config */
typedef struct MppEncH264HwCfg_t {
/*
@ -765,12 +620,7 @@ typedef struct MppEncH264HwCfg_t {
RK_U32 hw_split_out;
} MppEncH264HwCfg;
/*
* H.264 configurable parameter
*/
typedef struct MppEncH264Cfg_t {
RK_U32 change;
/*
* H.264 stream format
* 0 - H.264 Annex B: NAL unit starts with '00 00 00 01'
@ -939,27 +789,6 @@ typedef struct H265eRoi_Region_t {
H265eRect rect;
} H265eRoiRegion;
/*
* roi region only can be setting when rc_enable = 1
*/
typedef struct MppEncH265RoiCfg_t {
/*
* the value is defined by H265eCtuMethod
*/
RK_U8 method;
/*
* the number of roi,the value must less than H265E_MAX_ROI_NUMBER
*/
RK_S32 num;
/* delat qp using in roi region*/
RK_U32 delta_qp;
/* roi region */
H265eRoiRegion region[H265E_MAX_ROI_NUMBER];
} MppEncH265RoiCfg;
typedef struct H265eCtuQp_t {
/* the qp value using in ctu region */
RK_U32 qp;
@ -972,21 +801,6 @@ typedef struct H265eCtuQp_t {
H265eRect rect;
} H265eCtu;
typedef struct H265eCtuRegion_t {
/*
* the value is defined by H265eCtuMethod
*/
RK_U8 method;
/*
* the number of ctu,the value must less than H265E_MAX_ROI_NUMBER
*/
RK_S32 num;
/* ctu region */
H265eCtu ctu[H265E_MAX_ROI_NUMBER];
} MppEncH265CtuCfg;
/*
* define the method when set CTU/ROI parameters
* this value is using by method in H265eCtuRegion or H265eRoi struct
@ -999,41 +813,6 @@ typedef enum {
/*
* H.265 configurable parameter
*/
typedef enum MppEncH265CfgChange_e {
/* change on stream type */
MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE = (1 << 0),
MPP_ENC_H265_CFG_INTRA_QP_CHANGE = (1 << 1),
MPP_ENC_H265_CFG_FRAME_RATE_CHANGE = (1 << 2),
MPP_ENC_H265_CFG_BITRATE_CHANGE = (1 << 3),
MPP_ENC_H265_CFG_GOP_SIZE = (1 << 4),
MPP_ENC_H265_CFG_RC_QP_CHANGE = (1 << 5),
MPP_ENC_H265_CFG_INTRA_REFRESH_CHANGE = (1 << 6),
MPP_ENC_H265_CFG_INDEPEND_SLICE_CHANGE = (1 << 7),
MPP_ENC_H265_CFG_DEPEND_SLICE_CHANGE = (1 << 8),
MPP_ENC_H265_CFG_CTU_CHANGE = (1 << 9),
MPP_ENC_H265_CFG_ROI_CHANGE = (1 << 10),
MPP_ENC_H265_CFG_CU_CHANGE = (1 << 11),
MPP_ENC_H265_CFG_DBLK_CHANGE = (1 << 12),
MPP_ENC_H265_CFG_SAO_CHANGE = (1 << 13),
MPP_ENC_H265_CFG_TRANS_CHANGE = (1 << 14),
MPP_ENC_H265_CFG_SLICE_CHANGE = (1 << 15),
MPP_ENC_H265_CFG_ENTROPY_CHANGE = (1 << 16),
MPP_ENC_H265_CFG_MERGE_CHANGE = (1 << 17),
MPP_ENC_H265_CFG_CHANGE_VUI = (1 << 18),
MPP_ENC_H265_CFG_RC_I_QP_CHANGE = (1 << 19),
MPP_ENC_H265_CFG_RC_MAX_QP_STEP_CHANGE = (1 << 21),
MPP_ENC_H265_CFG_RC_IP_DELTA_QP_CHANGE = (1 << 20),
MPP_ENC_H265_CFG_TILE_CHANGE = (1 << 22),
MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE = (1 << 23),
MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE = (1 << 24),
MPP_ENC_H265_CFG_CHANGE_CONST_INTRA = (1 << 25),
MPP_ENC_H265_CFG_CHANGE_LCU_SIZE = (1 << 26),
MPP_ENC_H265_CFG_CHANGE_MAX_TID = (1 << 27),
MPP_ENC_H265_CFG_CHANGE_MAX_LTR = (1 << 28),
MPP_ENC_H265_CFG_CHANGE_BASE_LAYER_PID = (1 << 29),
MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncH265CfgChange;
typedef struct MppEncH265SliceCfg_t {
/* default value: 0, means no slice split*/
RK_U32 split_enable;
@ -1062,10 +841,6 @@ typedef struct MppEncH265CuCfg_t {
RK_U32 pcm_loop_filter_disabled_flag;
} MppEncH265CuCfg;
typedef struct MppEncH265RefCfg_t {
RK_U32 num_lt_ref_pic; /*default: 0*/
} MppEncH265RefCfg;
typedef struct MppEncH265DblkCfg_t {
RK_U32 slice_deblocking_filter_disabled_flag; /* default value: 0. {0,1} */
RK_S32 slice_beta_offset_div2; /* default value: 0. [-6,+6] */
@ -1081,7 +856,7 @@ typedef struct MppEncH265SaoCfg_t {
typedef struct MppEncH265TransCfg_t {
RK_U32 transquant_bypass_enabled_flag;
RK_U32 transform_skip_enabled_flag;
RK_U32 defalut_ScalingList_enable; /* default: 0 */
RK_U32 scaling_list_mode; /* default: 0 */
RK_S32 cb_qp_offset;
RK_S32 cr_qp_offset;
RK_S32 diff_cu_qp_delta_depth;
@ -1098,8 +873,6 @@ typedef struct MppEncH265EntropyCfg_t {
} MppEncH265EntropyCfg;
typedef struct MppEncH265Cfg_t {
RK_U32 change;
/* H.265 codec syntax config */
RK_S32 profile;
RK_S32 level;
@ -1117,43 +890,22 @@ typedef struct MppEncH265Cfg_t {
RK_U32 num_ref;
/* quality config */
RK_S32 max_qp;
RK_S32 min_qp;
RK_S32 max_i_qp;
RK_S32 min_i_qp;
RK_S32 ip_qp_delta;
RK_S32 max_delta_qp;
RK_S32 intra_qp;
RK_S32 gop_delta_qp;
RK_S32 qp_init;
RK_S32 qp_max_step;
RK_S32 raw_dealt_qp;
RK_U8 qpmax_map[8];
RK_U8 qpmin_map[8];
RK_S32 qpmap_mode;
/* intra fresh config */
RK_S32 intra_refresh_mode;
RK_S32 intra_refresh_arg;
/* extra mode config */
RK_S32 max_ltr_frames;
RK_S32 max_tid;
RK_S32 base_layer_pid;
/* slice mode config */
RK_S32 independ_slice_mode;
RK_S32 independ_slice_arg;
RK_S32 depend_slice_mode;
RK_S32 depend_slice_arg;
MppEncH265CuCfg cu_cfg;
MppEncH265SliceCfg slice_cfg;
MppEncH265EntropyCfg entropy_cfg;
MppEncH265TransCfg trans_cfg;
MppEncH265SaoCfg sao_cfg;
MppEncH265DblkCfg_t dblk_cfg;
MppEncH265RefCfg ref_cfg;
MppEncH265MergesCfg merge_cfg;
RK_S32 auto_tile;
RK_U32 lpf_acs_sli_en;
@ -1161,25 +913,24 @@ typedef struct MppEncH265Cfg_t {
/* extra info */
MppEncVuiCfg vui;
MppEncH265CtuCfg ctu;
MppEncH265RoiCfg roi;
} MppEncH265Cfg;
/*
* motion jpeg configurable parameter
*/
typedef enum MppEncJpegCfgChange_e {
/* change on quant parameter */
MPP_ENC_JPEG_CFG_CHANGE_QP = (1 << 0),
MPP_ENC_JPEG_CFG_CHANGE_QTABLE = (1 << 1),
MPP_ENC_JPEG_CFG_CHANGE_QFACTOR = (1 << 2),
MPP_ENC_JPEG_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncJpegCfgChange;
typedef enum MppEncJpegQpMode_e {
JPEG_QP_NA = 0,
JPEG_QUANT = 1,
JPEG_QFACTOR = 2,
JPEG_QTABLE = 3,
} MppEncJpegQpMode;
typedef struct MppEncJpegCfg_t {
RK_U32 change;
RK_S32 q_mode;
RK_S32 update;
RK_S32 quant;
RK_S32 quant_ext;
/*
* quality factor config
*
@ -1191,47 +942,35 @@ typedef struct MppEncJpegCfg_t {
* qtable_v: default equal qtable_u
*/
RK_S32 q_factor;
RK_S32 q_factor_ext;
RK_S32 qf_max;
RK_S32 qf_max_ext;
RK_S32 qf_min;
RK_U8 *qtable_y;
RK_U8 *qtable_u;
RK_U8 *qtable_v;
RK_S32 qf_min_ext;
/*
* qtable_y: qtable for luma
* qtable_u: qtable for chroma u
* qtable_v: qtable for chroma v
* for most case u and v use the same table
*/
RK_U8 qtable_y[64];
RK_U8 qtable_u[64];
RK_U8 qtable_v[64];
} MppEncJpegCfg;
/*
* vp8 configurable parameter
*/
typedef enum MppEncVP8CfgChange_e {
MPP_ENC_VP8_CFG_CHANGE_QP = (1 << 0),
MPP_ENC_VP8_CFG_CHANGE_DIS_IVF = (1 << 1),
MPP_ENC_VP8_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncVP8CfgChange;
typedef struct MppEncVp8Cfg_t {
RK_U32 change;
RK_S32 quant;
RK_S32 qp_init;
RK_S32 qp_max;
RK_S32 qp_max_i;
RK_S32 qp_min;
RK_S32 qp_min_i;
RK_S32 qp_max_step;
RK_S32 disable_ivf;
} MppEncVp8Cfg;
typedef enum MppEncSliceSplit_e {
/* change on quant parameter */
MPP_ENC_SPLIT_CFG_CHANGE_MODE = (1 << 0),
MPP_ENC_SPLIT_CFG_CHANGE_ARG = (1 << 1),
MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT = (1 << 2),
MPP_ENC_SPLIT_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncSliceSplitChange;
typedef enum MppEncSplitMode_e {
MPP_ENC_SPLIT_NONE,
MPP_ENC_SPLIT_BY_BYTE,
MPP_ENC_SPLIT_BY_CTU,
MPP_ENC_SPLIT_MODE_BUTT,
} MppEncSplitMode;
typedef enum MppEncSplitOutMode_e {
@ -1240,8 +979,6 @@ typedef enum MppEncSplitOutMode_e {
} MppEncSplitOutMode;
typedef struct MppEncSliceSplit_t {
RK_U32 change;
/*
* slice split mode
*
@ -1517,37 +1254,7 @@ typedef enum MppEncSceneMode_e {
MPP_ENC_SCENE_MODE_BUTT,
} MppEncSceneMode;
typedef enum MppEncFineTuneCfgChange_e {
/* change on scene mode */
MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE = (1 << 0),
MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_EN = (1 << 1),
MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_STR = (1 << 2),
MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR = (1 << 3),
MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I = (1 << 5),
MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P = (1 << 6),
MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_I = (1 << 7),
MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_P = (1 << 8),
MPP_ENC_TUNE_CFG_CHANGE_ATL_STR = (1 << 9),
MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_I = (1 << 10),
MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_P = (1 << 11),
MPP_ENC_TUNE_CFG_CHANGE_SE_MODE = (1 << 12),
MPP_ENC_TUNE_CFG_CHANGE_RC_CONTAINER = (1 << 13),
MPP_ENC_TUNE_CFG_CHANGE_VMAF_OPT = (1 << 14),
MPP_ENC_TUNE_CFG_CHANGE_MOTION_STATIC_SWITCH_ENABLE = (1 << 15),
MPP_ENC_TUNE_CFG_CHANGE_ATF_STR = (1 << 16),
MPP_ENC_TUNE_CFG_CHANGE_LGT_CHG_LVL = (1 << 17),
MPP_ENC_TUNE_CFG_CHANGE_STATIC_FRM_NUM = (1 << 18),
MPP_ENC_TUNE_CFG_CHANGE_MADP16_TH = (1 << 19),
MPP_ENC_TUNE_CFG_CHANGE_SKIP16_WGT = (1 << 20),
MPP_ENC_TUNE_CFG_CHANGE_SKIP32_WGT = (1 << 21),
MPP_ENC_TUNE_CFG_CHANGE_SPEED = (1 << 22),
MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG = (1 << 23),
MPP_ENC_TUNE_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncFineTuneCfgChange;
typedef struct MppEncFineTuneCfg_t {
RK_U32 change;
MppEncSceneMode scene_mode;
MppEncSeMode se_mode;
RK_S32 deblur_en; /* qpmap_en */
@ -1572,7 +1279,7 @@ typedef struct MppEncFineTuneCfg_t {
RK_S32 skip16_wgt; /* weight for skip16, 0 or [3, 8] */
RK_S32 skip32_wgt; /* weight for skip32, 0 or [3, 8] */
RK_S32 qpmap_en;
RK_S32 speed; /*enc speed [0..3], 0:full mode; 1:fast; 2:faster; 3:fastest */
RK_S32 speed; /* encoder speed [0..3], 0:normal; 1:fast; 2:faster; 3:fastest */
/* smart v3 only */
RK_S32 bg_delta_qp_i; /* background delta qp for i frame */
@ -1587,6 +1294,7 @@ typedef struct MppEncFineTuneCfg_t {
RK_S32 max_bg_fqp; /* max frame qp for background region */
RK_S32 min_fg_fqp; /* min frame qp for foreground region */
RK_S32 max_fg_fqp; /* max frame qp for foreground region */
RK_S32 fg_area; /* foreground area, [-1, 100] */
} MppEncFineTuneCfg;
#endif /*__RK_VENC_CMD_H__*/

1
inc/rk_venc_kcfg.h
View file

@ -21,6 +21,7 @@ typedef enum {
MPP_VENC_KCFG_TYPE_RESET,
MPP_VENC_KCFG_TYPE_START,
MPP_VENC_KCFG_TYPE_STOP,
MPP_VENC_KCFG_TYPE_ST_CFG,
MPP_VENC_KCFG_TYPE_BUTT,
} MppVencKcfgType;

1
kmpp/base/kmpp_venc_cfg.c
View file

@ -37,6 +37,7 @@ static char *kcfg_names[] = {
[MPP_VENC_KCFG_TYPE_RESET] = "KmppVencResetCfg",
[MPP_VENC_KCFG_TYPE_START] = "KmppVencStartCfg",
[MPP_VENC_KCFG_TYPE_STOP] = "KmppVencStopCfg",
[MPP_VENC_KCFG_TYPE_ST_CFG] = "KmppVencStCfg",
};
static KmppObjDef kcfg_defs[MPP_VENC_KCFG_TYPE_BUTT] = {NULL};

9
kmpp/kmpp.c
View file

@ -492,16 +492,13 @@ static MPP_RET control(Kmpp *ctx, MpiCmd cmd, MppParam param)
switch (cmd) {
case MPP_ENC_SET_CFG :
case MPP_ENC_GET_CFG : {
MppEncCfgImpl *impl = (MppEncCfgImpl *)param;
mpp_assert(impl->is_kobj);
if (impl->is_kobj) {
KmppObj obj = impl->obj;
KmppObj obj = (KmppObj)param;
if (kmpp_obj_is_kobj(obj)) {
arg = kmpp_obj_to_shm(obj);
size = kmpp_obj_to_shm_size(obj);
} else {
mpp_loge("can not set non-kobj %p to kmpp\n", impl);
mpp_loge("can not set non-kobj %p to kmpp\n", obj);
return MPP_NOK;
}
} break;

52
mpp/base/mpp_dec_cfg.c
View file

@ -24,34 +24,34 @@
#define MPP_DEC_CFG_ENTRY_TABLE(prefix, ENTRY, STRCT, EHOOK, SHOOK, ALIAS) \
CFG_DEF_START() \
STRUCT_START(base) \
ENTRY(prefix, u32, rk_u32, type, FLAG_BASE(0), base, type) \
ENTRY(prefix, u32, rk_u32, coding, FLAG_AT(1), base, coding) \
ENTRY(prefix, u32, rk_u32, hw_type, FLAG_AT(2), base, hw_type) \
ENTRY(prefix, u32, rk_u32, batch_mode, FLAG_AT(3), base, batch_mode) \
ENTRY(prefix, u32, rk_u32, out_fmt, FLAG_AT(4), base, out_fmt) \
ENTRY(prefix, u32, rk_u32, fast_out, FLAG_AT(5), base, fast_out) \
ENTRY(prefix, u32, rk_u32, fast_parse, FLAG_AT(6), base, fast_parse) \
ENTRY(prefix, u32, rk_u32, split_parse, FLAG_AT(7), base, split_parse) \
ENTRY(prefix, u32, rk_u32, internal_pts, FLAG_AT(8), base, internal_pts) \
ENTRY(prefix, u32, rk_u32, sort_pts, FLAG_AT(9), base, sort_pts) \
ENTRY(prefix, u32, rk_u32, disable_error, FLAG_AT(10), base, disable_error) \
ENTRY(prefix, u32, rk_u32, enable_vproc, FLAG_AT(11), base, enable_vproc) \
ENTRY(prefix, u32, rk_u32, enable_fast_play, FLAG_AT(12), base, enable_fast_play) \
ENTRY(prefix, u32, rk_u32, enable_hdr_meta, FLAG_AT(13), base, enable_hdr_meta) \
ENTRY(prefix, u32, rk_u32, enable_thumbnail, FLAG_AT(14), base, enable_thumbnail) \
ENTRY(prefix, u32, rk_u32, enable_mvc, FLAG_AT(15), base, enable_mvc) \
ENTRY(prefix, u32, rk_u32, disable_dpb_chk, FLAG_AT(16), base, disable_dpb_chk) \
ENTRY(prefix, u32, rk_u32, disable_thread, FLAG_AT(17), base, disable_thread) \
ENTRY(prefix, u32, rk_u32, codec_mode, FLAG_AT(18), base, codec_mode) \
ENTRY(prefix, u32, rk_u32, dis_err_clr_mark, FLAG_AT(19), base, dis_err_clr_mark) \
ENTRY(prefix, u32, rk_u32, type, FLAG_BASE(0), base, type) \
ENTRY(prefix, u32, rk_u32, coding, FLAG_INCR, base, coding) \
ENTRY(prefix, u32, rk_u32, hw_type, FLAG_INCR, base, hw_type) \
ENTRY(prefix, u32, rk_u32, batch_mode, FLAG_INCR, base, batch_mode) \
ENTRY(prefix, u32, rk_u32, out_fmt, FLAG_INCR, base, out_fmt) \
ENTRY(prefix, u32, rk_u32, fast_out, FLAG_INCR, base, fast_out) \
ENTRY(prefix, u32, rk_u32, fast_parse, FLAG_INCR, base, fast_parse) \
ENTRY(prefix, u32, rk_u32, split_parse, FLAG_INCR, base, split_parse) \
ENTRY(prefix, u32, rk_u32, internal_pts, FLAG_INCR, base, internal_pts) \
ENTRY(prefix, u32, rk_u32, sort_pts, FLAG_INCR, base, sort_pts) \
ENTRY(prefix, u32, rk_u32, disable_error, FLAG_INCR, base, disable_error) \
ENTRY(prefix, u32, rk_u32, enable_vproc, FLAG_INCR, base, enable_vproc) \
ENTRY(prefix, u32, rk_u32, enable_fast_play, FLAG_INCR, base, enable_fast_play) \
ENTRY(prefix, u32, rk_u32, enable_hdr_meta, FLAG_INCR, base, enable_hdr_meta) \
ENTRY(prefix, u32, rk_u32, enable_thumbnail, FLAG_INCR, base, enable_thumbnail) \
ENTRY(prefix, u32, rk_u32, enable_mvc, FLAG_INCR, base, enable_mvc) \
ENTRY(prefix, u32, rk_u32, disable_dpb_chk, FLAG_INCR, base, disable_dpb_chk) \
ENTRY(prefix, u32, rk_u32, disable_thread, FLAG_INCR, base, disable_thread) \
ENTRY(prefix, u32, rk_u32, codec_mode, FLAG_INCR, base, codec_mode) \
ENTRY(prefix, u32, rk_u32, dis_err_clr_mark, FLAG_INCR, base, dis_err_clr_mark) \
STRUCT_END(base) \
STRUCT_START(cb) \
ENTRY(prefix, ptr, void *, pkt_rdy_cb, FLAG_BASE(0), cb, pkt_rdy_cb) \
ENTRY(prefix, ptr, void *, pkt_rdy_ctx, FLAG_AT(0), cb, pkt_rdy_ctx) \
ENTRY(prefix, s32, rk_s32, pkt_rdy_cmd, FLAG_AT(0), cb, pkt_rdy_cmd) \
ENTRY(prefix, ptr, void *, frm_rdy_cb, FLAG_AT(1), cb, frm_rdy_cb) \
ENTRY(prefix, ptr, void *, frm_rdy_ctx, FLAG_AT(1), cb, frm_rdy_ctx) \
ENTRY(prefix, s32, rk_s32, frm_rdy_cmd, FLAG_AT(1), cb, frm_rdy_cmd) \
ENTRY(prefix, ptr, void *, pkt_rdy_cb, FLAG_BASE(0), cb, pkt_rdy_cb) \
ENTRY(prefix, ptr, void *, pkt_rdy_ctx, FLAG_PREV, cb, pkt_rdy_ctx) \
ENTRY(prefix, s32, rk_s32, pkt_rdy_cmd, FLAG_PREV, cb, pkt_rdy_cmd) \
ENTRY(prefix, ptr, void *, frm_rdy_cb, FLAG_INCR, cb, frm_rdy_cb) \
ENTRY(prefix, ptr, void *, frm_rdy_ctx, FLAG_PREV, cb, frm_rdy_ctx) \
ENTRY(prefix, s32, rk_s32, frm_rdy_cmd, FLAG_PREV, cb, frm_rdy_cmd) \
STRUCT_END(cb) \
CFG_DEF_END()

750
mpp/base/mpp_enc_cfg.c
View file

@ -8,6 +8,7 @@
#include <string.h>
#include "rk_venc_cfg.h"
#include "rk_venc_kcfg.h"
#include "mpp_env.h"
#include "mpp_mem.h"
@ -32,313 +33,251 @@
#define enc_cfg_dbg_set(fmt, ...) enc_cfg_dbg(ENC_CFG_DBG_SET, fmt, ## __VA_ARGS__)
#define enc_cfg_dbg_get(fmt, ...) enc_cfg_dbg(ENC_CFG_DBG_GET, fmt, ## __VA_ARGS__)
#define get_srv_enc_cfg_f() \
({ \
MppEncCfgSrv *__tmp; \
if (srv_enc_cfg) { \
__tmp = srv_enc_cfg; \
} else { \
mpp_enc_cfg_srv_init(); \
__tmp = srv_enc_cfg; \
if (!__tmp) \
mpp_err("mpp enc cfg srv not init at %s\n", __FUNCTION__); \
} \
__tmp; \
})
typedef struct MppEncCfgSrv_t {
MppTrie trie;
} MppEncCfgSrv;
static MppEncCfgSrv *srv_enc_cfg = NULL;
static RK_U32 mpp_enc_cfg_debug = 0;
#define EXPAND_AS_TRIE(base, name, cfg_type, flag, field_change, field_data) \
do { \
MppCfgInfo tmp = { \
CFG_FUNC_TYPE_##cfg_type, \
(RK_U32)((long)&(((MppEncCfgSet *)0)->field_change.change)), \
flag, \
(RK_U32)((long)&(((MppEncCfgSet *)0)->field_change.field_data)), \
sizeof((((MppEncCfgSet *)0)->field_change.field_data)), \
}; \
mpp_trie_add_info(srv->trie, #base":"#name, &tmp, sizeof(tmp)); \
} while (0);
#define ENTRY_TABLE(ENTRY) \
/* base config */ \
ENTRY(base, low_delay, S32, MPP_ENC_BASE_CFG_CHANGE_LOW_DELAY, base, low_delay) \
ENTRY(base, smart_en, S32, MPP_ENC_BASE_CFG_CHANGE_SMART_EN, base, smart_en) \
/* codec coding config */ \
ENTRY(codec, type, S32, MPP_ENC_BASE_CFG_CHANGE_CODING, base, coding) \
/* rc config */ \
ENTRY(rc, mode, S32, MPP_ENC_RC_CFG_CHANGE_RC_MODE, rc, rc_mode) \
ENTRY(rc, bps_target, S32, MPP_ENC_RC_CFG_CHANGE_BPS, rc, bps_target) \
ENTRY(rc, bps_max, S32, MPP_ENC_RC_CFG_CHANGE_BPS, rc, bps_max) \
ENTRY(rc, bps_min, S32, MPP_ENC_RC_CFG_CHANGE_BPS, rc, bps_min) \
ENTRY(rc, fps_in_flex, S32, MPP_ENC_RC_CFG_CHANGE_FPS_IN, rc, fps_in_flex) \
ENTRY(rc, fps_in_num, S32, MPP_ENC_RC_CFG_CHANGE_FPS_IN, rc, fps_in_num) \
ENTRY(rc, fps_in_denom, S32, MPP_ENC_RC_CFG_CHANGE_FPS_IN, rc, fps_in_denom) \
ENTRY(rc, fps_in_denorm, S32, MPP_ENC_RC_CFG_CHANGE_FPS_IN, rc, fps_in_denom) \
ENTRY(rc, fps_out_flex, S32, MPP_ENC_RC_CFG_CHANGE_FPS_OUT, rc, fps_out_flex) \
ENTRY(rc, fps_out_num, S32, MPP_ENC_RC_CFG_CHANGE_FPS_OUT, rc, fps_out_num) \
ENTRY(rc, fps_out_denom, S32, MPP_ENC_RC_CFG_CHANGE_FPS_OUT, rc, fps_out_denom) \
ENTRY(rc, fps_out_denorm, S32, MPP_ENC_RC_CFG_CHANGE_FPS_OUT, rc, fps_out_denom) \
ENTRY(rc, fps_chg_no_idr, S32, MPP_ENC_RC_CFG_CHANGE_FPS_OUT, rc, fps_chg_no_idr) \
ENTRY(rc, gop, S32, MPP_ENC_RC_CFG_CHANGE_GOP, rc, gop) \
ENTRY(rc, ref_cfg, Ptr, MPP_ENC_RC_CFG_CHANGE_GOP_REF_CFG, rc, ref_cfg) \
ENTRY(rc, max_reenc_times,U32, MPP_ENC_RC_CFG_CHANGE_MAX_REENC, rc, max_reenc_times) \
ENTRY(rc, priority, U32, MPP_ENC_RC_CFG_CHANGE_PRIORITY, rc, rc_priority) \
ENTRY(rc, drop_mode, U32, MPP_ENC_RC_CFG_CHANGE_DROP_FRM, rc, drop_mode) \
ENTRY(rc, drop_thd, U32, MPP_ENC_RC_CFG_CHANGE_DROP_FRM, rc, drop_threshold) \
ENTRY(rc, drop_gap, U32, MPP_ENC_RC_CFG_CHANGE_DROP_FRM, rc, drop_gap) \
ENTRY(rc, max_i_prop, S32, MPP_ENC_RC_CFG_CHANGE_MAX_I_PROP, rc, max_i_prop) \
ENTRY(rc, min_i_prop, S32, MPP_ENC_RC_CFG_CHANGE_MIN_I_PROP, rc, min_i_prop) \
ENTRY(rc, init_ip_ratio, S32, MPP_ENC_RC_CFG_CHANGE_INIT_IP_RATIO, rc, init_ip_ratio) \
ENTRY(rc, super_mode, U32, MPP_ENC_RC_CFG_CHANGE_SUPER_FRM, rc, super_mode) \
ENTRY(rc, super_i_thd, U32, MPP_ENC_RC_CFG_CHANGE_SUPER_FRM, rc, super_i_thd) \
ENTRY(rc, super_p_thd, U32, MPP_ENC_RC_CFG_CHANGE_SUPER_FRM, rc, super_p_thd) \
ENTRY(rc, debreath_en, U32, MPP_ENC_RC_CFG_CHANGE_DEBREATH, rc, debreath_en) \
ENTRY(rc, debreath_strength, U32, MPP_ENC_RC_CFG_CHANGE_DEBREATH, rc, debre_strength) \
ENTRY(rc, qp_init, S32, MPP_ENC_RC_CFG_CHANGE_QP_INIT, rc, qp_init) \
ENTRY(rc, qp_min, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE, rc, qp_min) \
ENTRY(rc, qp_max, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE, rc, qp_max) \
ENTRY(rc, qp_min_i, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I, rc, qp_min_i) \
ENTRY(rc, qp_max_i, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I, rc, qp_max_i) \
ENTRY(rc, qp_step, S32, MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP, rc, qp_max_step) \
ENTRY(rc, qp_ip, S32, MPP_ENC_RC_CFG_CHANGE_QP_IP, rc, qp_delta_ip) \
ENTRY(rc, qp_vi, S32, MPP_ENC_RC_CFG_CHANGE_QP_VI, rc, qp_delta_vi) \
ENTRY(rc, hier_qp_en, S32, MPP_ENC_RC_CFG_CHANGE_HIER_QP, rc, hier_qp_en) \
ENTRY(rc, hier_qp_delta, St, MPP_ENC_RC_CFG_CHANGE_HIER_QP, rc, hier_qp_delta) \
ENTRY(rc, hier_frame_num, St, MPP_ENC_RC_CFG_CHANGE_HIER_QP, rc, hier_frame_num) \
ENTRY(rc, stats_time, S32, MPP_ENC_RC_CFG_CHANGE_ST_TIME, rc, stats_time) \
ENTRY(rc, refresh_en, U32, MPP_ENC_RC_CFG_CHANGE_REFRESH, rc, refresh_en) \
ENTRY(rc, refresh_mode, U32, MPP_ENC_RC_CFG_CHANGE_REFRESH, rc, refresh_mode) \
ENTRY(rc, refresh_num, U32, MPP_ENC_RC_CFG_CHANGE_REFRESH, rc, refresh_num) \
ENTRY(rc, fqp_min_i, S32, MPP_ENC_RC_CFG_CHANGE_FQP, rc, fqp_min_i) \
ENTRY(rc, fqp_min_p, S32, MPP_ENC_RC_CFG_CHANGE_FQP, rc, fqp_min_p) \
ENTRY(rc, fqp_max_i, S32, MPP_ENC_RC_CFG_CHANGE_FQP, rc, fqp_max_i) \
ENTRY(rc, fqp_max_p, S32, MPP_ENC_RC_CFG_CHANGE_FQP, rc, fqp_max_p) \
ENTRY(rc, mt_st_swth_frm_qp, S32, MPP_ENC_RC_CFG_CHANGE_FQP, rc, mt_st_swth_frm_qp) \
/* prep config */ \
ENTRY(prep, width, S32, MPP_ENC_PREP_CFG_CHANGE_INPUT, prep, width) \
ENTRY(prep, height, S32, MPP_ENC_PREP_CFG_CHANGE_INPUT, prep, height) \
ENTRY(prep, max_width, S32, MPP_ENC_PREP_CFG_CHANGE_INPUT, prep, max_width) \
ENTRY(prep, max_height, S32, MPP_ENC_PREP_CFG_CHANGE_INPUT, prep, max_height) \
ENTRY(prep, hor_stride, S32, MPP_ENC_PREP_CFG_CHANGE_INPUT, prep, hor_stride) \
ENTRY(prep, ver_stride, S32, MPP_ENC_PREP_CFG_CHANGE_INPUT, prep, ver_stride) \
ENTRY(prep, format, S32, MPP_ENC_PREP_CFG_CHANGE_FORMAT, prep, format) \
ENTRY(prep, format_out, S32, MPP_ENC_PREP_CFG_CHANGE_FORMAT, prep, format_out) \
ENTRY(prep, chroma_ds_mode, S32, MPP_ENC_PREP_CFG_CHANGE_FORMAT, prep, chroma_ds_mode) \
ENTRY(prep, fix_chroma_en, S32, MPP_ENC_PREP_CFG_CHANGE_FORMAT, prep, fix_chroma_en) \
ENTRY(prep, fix_chroma_u, S32, MPP_ENC_PREP_CFG_CHANGE_FORMAT, prep, fix_chroma_u) \
ENTRY(prep, fix_chroma_v, S32, MPP_ENC_PREP_CFG_CHANGE_FORMAT, prep, fix_chroma_v) \
ENTRY(prep, colorspace, S32, MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE, prep, color) \
ENTRY(prep, colorprim, S32, MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME, prep, colorprim) \
ENTRY(prep, colortrc, S32, MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC, prep, colortrc) \
ENTRY(prep, colorrange, S32, MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE, prep, range) \
ENTRY(prep, range, S32, MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE, prep, range) \
ENTRY(prep, range_out, S32, MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE, prep, range_out) \
ENTRY(prep, rotation, S32, MPP_ENC_PREP_CFG_CHANGE_ROTATION, prep, rotation_ext) \
ENTRY(prep, mirroring, S32, MPP_ENC_PREP_CFG_CHANGE_MIRRORING, prep, mirroring_ext) \
ENTRY(prep, flip, S32, MPP_ENC_PREP_CFG_CHANGE_FLIP, prep, flip) \
#define MPP_ENC_CFG_ENTRY_TABLE(prefix, ENTRY, STRCT, EHOOK, SHOOK, ALIAS) \
CFG_DEF_START() \
/* prefix ElemType base type trie name update flag type element address */ \
STRUCT_START(codec); \
ENTRY(prefix, s32, rk_s32, type, FLAG_BASE(0), base, coding); \
STRUCT_END(codec); \
STRUCT_START(base) \
ENTRY(prefix, s32, rk_s32, low_delay, FLAG_INCR, base, low_delay) \
ENTRY(prefix, s32, rk_s32, smt1_en, FLAG_INCR, base, smt1_en) \
ENTRY(prefix, s32, rk_s32, smt3_en, FLAG_INCR, base, smt3_en) \
STRUCT_END(base) \
STRUCT_START(rc) \
ENTRY(prefix, s32, rk_s32, mode, FLAG_BASE(0), rc, rc_mode) \
ENTRY(prefix, s32, rk_s32, quality, FLAG_INCR, rc, quality); \
ENTRY(prefix, s32, rk_s32, bps_target, FLAG_INCR, rc, bps_target) \
ENTRY(prefix, s32, rk_s32, bps_max, FLAG_PREV, rc, bps_max) \
ENTRY(prefix, s32, rk_s32, bps_min, FLAG_PREV, rc, bps_min) \
ENTRY(prefix, s32, rk_s32, fps_in_flex, FLAG_INCR, rc, fps_in_flex) \
ENTRY(prefix, s32, rk_s32, fps_in_num, FLAG_PREV, rc, fps_in_num) \
ENTRY(prefix, s32, rk_s32, fps_in_denorm, FLAG_PREV, rc, fps_in_denom) \
ALIAS(prefix, s32, rk_s32, fps_in_denom, FLAG_PREV, rc, fps_in_denom) \
ENTRY(prefix, s32, rk_s32, fps_out_flex, FLAG_INCR, rc, fps_out_flex) \
ENTRY(prefix, s32, rk_s32, fps_out_num, FLAG_PREV, rc, fps_out_num) \
ENTRY(prefix, s32, rk_s32, fps_out_denorm, FLAG_PREV, rc, fps_out_denom) \
ALIAS(prefix, s32, rk_s32, fps_out_denom, FLAG_PREV, rc, fps_out_denom) \
ENTRY(prefix, s32, rk_s32, fps_chg_no_idr, FLAG_PREV, rc, fps_chg_no_idr) \
ENTRY(prefix, s32, rk_s32, gop, FLAG_INCR, rc, gop) \
ENTRY(prefix, kptr, void *, ref_cfg, FLAG_INCR, rc, ref_cfg) \
ENTRY(prefix, u32, rk_u32, max_reenc_times, FLAG_INCR, rc, max_reenc_times) \
ENTRY(prefix, u32, rk_u32, priority, FLAG_INCR, rc, rc_priority) \
ENTRY(prefix, u32, rk_u32, drop_mode, FLAG_INCR, rc, drop_mode) \
ENTRY(prefix, u32, rk_u32, drop_thd, FLAG_PREV, rc, drop_threshold) \
ENTRY(prefix, u32, rk_u32, drop_gap, FLAG_PREV, rc, drop_gap) \
ENTRY(prefix, s32, rk_s32, max_i_prop, FLAG_INCR, rc, max_i_prop) \
ENTRY(prefix, s32, rk_s32, min_i_prop, FLAG_INCR, rc, min_i_prop) \
ENTRY(prefix, s32, rk_s32, init_ip_ratio, FLAG_INCR, rc, init_ip_ratio) \
ENTRY(prefix, u32, rk_u32, super_mode, FLAG_INCR, rc, super_mode) \
ENTRY(prefix, u32, rk_u32, super_i_thd, FLAG_PREV, rc, super_i_thd) \
ENTRY(prefix, u32, rk_u32, super_p_thd, FLAG_PREV, rc, super_p_thd) \
ENTRY(prefix, u32, rk_u32, debreath_en, FLAG_INCR, rc, debreath_en) \
ENTRY(prefix, u32, rk_u32, debreath_strength, FLAG_PREV, rc, debre_strength) \
ENTRY(prefix, s32, rk_s32, qp_init, FLAG_REC_INC(0), rc, qp_init) \
ENTRY(prefix, s32, rk_s32, qp_min, FLAG_REC_INC(1), rc, qp_min) \
ENTRY(prefix, s32, rk_s32, qp_max, FLAG_REPLAY(1), rc, qp_max) \
ENTRY(prefix, s32, rk_s32, qp_min_i, FLAG_REC_INC(2), rc, qp_min_i) \
ENTRY(prefix, s32, rk_s32, qp_max_i, FLAG_REPLAY(2), rc, qp_max_i) \
ENTRY(prefix, s32, rk_s32, qp_step, FLAG_REC_INC(3), rc, qp_max_step) \
ENTRY(prefix, s32, rk_s32, qp_ip, FLAG_REC_INC(4), rc, qp_delta_ip) \
ENTRY(prefix, s32, rk_s32, qp_vi, FLAG_INCR, rc, qp_delta_vi) \
ENTRY(prefix, s32, rk_s32, hier_qp_en, FLAG_INCR, rc, hier_qp_en) \
STRCT(prefix, st, void *, hier_qp_delta, FLAG_PREV, rc, hier_qp_delta); \
STRCT(prefix, st, void *, hier_frame_num, FLAG_PREV, rc, hier_frame_num); \
ENTRY(prefix, s32, rk_s32, stats_time, FLAG_INCR, rc, stats_time) \
ENTRY(prefix, u32, rk_u32, refresh_en, FLAG_INCR, rc, refresh_en) \
ENTRY(prefix, u32, rk_u32, refresh_mode, FLAG_PREV, rc, refresh_mode) \
ENTRY(prefix, u32, rk_u32, refresh_num, FLAG_PREV, rc, refresh_num) \
ENTRY(prefix, s32, rk_s32, fqp_min_i, FLAG_INCR, rc, fqp_min_i) \
ENTRY(prefix, s32, rk_s32, fqp_min_p, FLAG_PREV, rc, fqp_min_p) \
ENTRY(prefix, s32, rk_s32, fqp_max_i, FLAG_PREV, rc, fqp_max_i) \
ENTRY(prefix, s32, rk_s32, fqp_max_p, FLAG_PREV, rc, fqp_max_p) \
ENTRY(prefix, s32, rk_s32, mt_st_swth_frm_qp, FLAG_PREV, rc, mt_st_swth_frm_qp) \
ENTRY(prefix, s32, rk_s32, inst_br_lvl, FLAG_INCR, rc, inst_br_lvl) \
STRUCT_END(rc) \
STRUCT_START(prep); \
ENTRY(prefix, s32, rk_s32, width, FLAG_BASE(0), prep, width_set); \
ENTRY(prefix, s32, rk_s32, height, FLAG_PREV, prep, height_set); \
ENTRY(prefix, s32, rk_s32, max_width, FLAG_PREV, prep, max_width); \
ENTRY(prefix, s32, rk_s32, max_height, FLAG_PREV, prep, max_height); \
ENTRY(prefix, s32, rk_s32, hor_stride, FLAG_PREV, prep, hor_stride); \
ENTRY(prefix, s32, rk_s32, ver_stride, FLAG_PREV, prep, ver_stride); \
ENTRY(prefix, s32, rk_s32, format, FLAG_INCR, prep, format); \
ENTRY(prefix, s32, rk_s32, format_out, FLAG_PREV, prep, format_out); \
ENTRY(prefix, s32, rk_s32, chroma_ds_mode, FLAG_PREV, prep, chroma_ds_mode); \
ENTRY(prefix, s32, rk_s32, fix_chroma_en, FLAG_PREV, prep, fix_chroma_en); \
ENTRY(prefix, s32, rk_s32, fix_chroma_u, FLAG_PREV, prep, fix_chroma_u); \
ENTRY(prefix, s32, rk_s32, fix_chroma_v, FLAG_PREV, prep, fix_chroma_v); \
ENTRY(prefix, s32, rk_s32, colorspace, FLAG_INCR, prep, color); \
ENTRY(prefix, s32, rk_s32, colorprim, FLAG_INCR, prep, colorprim); \
ENTRY(prefix, s32, rk_s32, colortrc, FLAG_INCR, prep, colortrc); \
ENTRY(prefix, s32, rk_s32, colorrange, FLAG_INCR, prep, range); \
ALIAS(prefix, s32, rk_s32, range, FLAG_PREV, prep, range); \
ENTRY(prefix, s32, rk_s32, range_out, FLAG_PREV, prep, range_out); \
ENTRY(prefix, s32, rk_s32, rotation, FLAG_INCR, prep, rotation_ext); \
ENTRY(prefix, s32, rk_s32, mirroring, FLAG_INCR, prep, mirroring_ext); \
ENTRY(prefix, s32, rk_s32, flip, FLAG_INCR, prep, flip); \
STRUCT_END(prep); \
STRUCT_START(h264); \
/* h264 config */ \
ENTRY(h264, stream_type, S32, MPP_ENC_H264_CFG_STREAM_TYPE, h264, stream_type) \
ENTRY(h264, profile, S32, MPP_ENC_H264_CFG_CHANGE_PROFILE, h264, profile) \
ENTRY(h264, level, S32, MPP_ENC_H264_CFG_CHANGE_PROFILE, h264, level) \
ENTRY(h264, poc_type, U32, MPP_ENC_H264_CFG_CHANGE_POC_TYPE, h264, poc_type) \
ENTRY(h264, log2_max_poc_lsb, U32, MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB, h264, log2_max_poc_lsb) \
ENTRY(h264, log2_max_frm_num, U32, MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM, h264, log2_max_frame_num) \
ENTRY(h264, gaps_not_allowed, U32, MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM, h264, gaps_not_allowed) \
ENTRY(h264, cabac_en, S32, MPP_ENC_H264_CFG_CHANGE_ENTROPY, h264, entropy_coding_mode_ex) \
ENTRY(h264, cabac_idc, S32, MPP_ENC_H264_CFG_CHANGE_ENTROPY, h264, cabac_init_idc_ex) \
ENTRY(h264, trans8x8, S32, MPP_ENC_H264_CFG_CHANGE_TRANS_8x8, h264, transform8x8_mode_ex) \
ENTRY(h264, const_intra, S32, MPP_ENC_H264_CFG_CHANGE_CONST_INTRA, h264, constrained_intra_pred_mode) \
ENTRY(h264, scaling_list, S32, MPP_ENC_H264_CFG_CHANGE_SCALING_LIST, h264, scaling_list_mode) \
ENTRY(h264, cb_qp_offset, S32, MPP_ENC_H264_CFG_CHANGE_CHROMA_QP, h264, chroma_cb_qp_offset) \
ENTRY(h264, cr_qp_offset, S32, MPP_ENC_H264_CFG_CHANGE_CHROMA_QP, h264, chroma_cr_qp_offset) \
ENTRY(h264, dblk_disable, S32, MPP_ENC_H264_CFG_CHANGE_DEBLOCKING, h264, deblock_disable) \
ENTRY(h264, dblk_alpha, S32, MPP_ENC_H264_CFG_CHANGE_DEBLOCKING, h264, deblock_offset_alpha) \
ENTRY(h264, dblk_beta, S32, MPP_ENC_H264_CFG_CHANGE_DEBLOCKING, h264, deblock_offset_beta) \
ENTRY(h264, qp_init, S32, MPP_ENC_RC_CFG_CHANGE_QP_INIT, rc, qp_init) \
ENTRY(h264, qp_min, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE, rc, qp_min) \
ENTRY(h264, qp_max, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE, rc, qp_max) \
ENTRY(h264, qp_min_i, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I, rc, qp_min_i) \
ENTRY(h264, qp_max_i, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I, rc, qp_max_i) \
ENTRY(h264, qp_step, S32, MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP, rc, qp_max_step) \
ENTRY(h264, qp_delta_ip, S32, MPP_ENC_RC_CFG_CHANGE_QP_IP, rc, qp_delta_ip) \
ENTRY(h264, max_tid, S32, MPP_ENC_H264_CFG_CHANGE_MAX_TID, h264, max_tid) \
ENTRY(h264, max_ltr, S32, MPP_ENC_H264_CFG_CHANGE_MAX_LTR, h264, max_ltr_frames) \
ENTRY(h264, prefix_mode, S32, MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX, h264, prefix_mode) \
ENTRY(h264, base_layer_pid, S32, MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID, h264, base_layer_pid) \
ENTRY(h264, constraint_set, U32, MPP_ENC_H264_CFG_CHANGE_CONSTRAINT_SET, h264, constraint_set) \
ENTRY(h264, vui_en, U32, MPP_ENC_H264_CFG_CHANGE_VUI, h264, vui.vui_en) \
ENTRY(prefix, s32, rk_s32, stream_type, FLAG_BASE(0), h264, stream_type); \
ENTRY(prefix, s32, rk_s32, profile, FLAG_INCR, h264, profile); \
ENTRY(prefix, s32, rk_s32, level, FLAG_PREV, h264, level); \
ENTRY(prefix, u32, rk_u32, poc_type, FLAG_INCR, h264, poc_type); \
ENTRY(prefix, u32, rk_u32, log2_max_poc_lsb, FLAG_INCR, h264, log2_max_poc_lsb); \
ENTRY(prefix, u32, rk_u32, log2_max_frm_num, FLAG_INCR, h264, log2_max_frame_num); \
ENTRY(prefix, u32, rk_u32, gaps_not_allowed, FLAG_INCR, h264, gaps_not_allowed); \
ENTRY(prefix, s32, rk_s32, cabac_en, FLAG_INCR, h264, entropy_coding_mode_ex); \
ENTRY(prefix, s32, rk_s32, cabac_idc, FLAG_PREV, h264, cabac_init_idc_ex); \
ENTRY(prefix, s32, rk_s32, trans8x8, FLAG_INCR, h264, transform8x8_mode_ex); \
ENTRY(prefix, s32, rk_s32, const_intra, FLAG_INCR, h264, constrained_intra_pred_mode); \
ENTRY(prefix, s32, rk_s32, scaling_list, FLAG_INCR, h264, scaling_list_mode); \
ENTRY(prefix, s32, rk_s32, cb_qp_offset, FLAG_INCR, h264, chroma_cb_qp_offset); \
ENTRY(prefix, s32, rk_s32, cr_qp_offset, FLAG_PREV, h264, chroma_cr_qp_offset); \
ENTRY(prefix, s32, rk_s32, dblk_disable, FLAG_INCR, h264, deblock_disable); \
ENTRY(prefix, s32, rk_s32, dblk_alpha, FLAG_PREV, h264, deblock_offset_alpha); \
ENTRY(prefix, s32, rk_s32, dblk_beta, FLAG_PREV, h264, deblock_offset_beta); \
ALIAS(prefix, s32, rk_s32, qp_init, FLAG_REPLAY(0), rc, qp_init); \
ALIAS(prefix, s32, rk_s32, qp_min, FLAG_REPLAY(1), rc, qp_min); \
ALIAS(prefix, s32, rk_s32, qp_max, FLAG_REPLAY(1), rc, qp_max); \
ALIAS(prefix, s32, rk_s32, qp_min_i, FLAG_REPLAY(2), rc, qp_min_i); \
ALIAS(prefix, s32, rk_s32, qp_max_i, FLAG_REPLAY(2), rc, qp_max_i); \
ALIAS(prefix, s32, rk_s32, qp_step, FLAG_REPLAY(3), rc, qp_max_step); \
ALIAS(prefix, s32, rk_s32, qp_delta_ip, FLAG_REPLAY(4), rc, qp_delta_ip); \
ENTRY(prefix, s32, rk_s32, max_tid, FLAG_INCR, h264, max_tid); \
ENTRY(prefix, s32, rk_s32, max_ltr, FLAG_INCR, h264, max_ltr_frames); \
ENTRY(prefix, s32, rk_s32, prefix_mode, FLAG_INCR, h264, prefix_mode); \
ENTRY(prefix, s32, rk_s32, base_layer_pid, FLAG_INCR, h264, base_layer_pid); \
ENTRY(prefix, u32, rk_u32, constraint_set, FLAG_INCR, h264, constraint_set); \
ENTRY(prefix, u32, rk_u32, vui_en, FLAG_INCR, h264, vui, vui_en); \
STRUCT_END(h264); \
/* h265 config*/ \
ENTRY(h265, profile, S32, MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE, h265, profile) \
ENTRY(h265, tier , S32, MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE, h265, tier) \
ENTRY(h265, level, S32, MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE, h265, level) \
ENTRY(h265, scaling_list, U32, MPP_ENC_H265_CFG_TRANS_CHANGE, h265, trans_cfg.defalut_ScalingList_enable) \
ENTRY(h265, cb_qp_offset, S32, MPP_ENC_H265_CFG_TRANS_CHANGE, h265, trans_cfg.cb_qp_offset) \
ENTRY(h265, cr_qp_offset, S32, MPP_ENC_H265_CFG_TRANS_CHANGE, h265, trans_cfg.cr_qp_offset) \
ENTRY(h265, diff_cu_qp_delta_depth, S32, MPP_ENC_H265_CFG_TRANS_CHANGE, h265, trans_cfg.diff_cu_qp_delta_depth) \
ENTRY(h265, dblk_disable, U32, MPP_ENC_H265_CFG_DBLK_CHANGE, h265, dblk_cfg.slice_deblocking_filter_disabled_flag) \
ENTRY(h265, dblk_alpha, S32, MPP_ENC_H265_CFG_DBLK_CHANGE, h265, dblk_cfg.slice_beta_offset_div2) \
ENTRY(h265, dblk_beta, S32, MPP_ENC_H265_CFG_DBLK_CHANGE, h265, dblk_cfg.slice_tc_offset_div2) \
ENTRY(h265, qp_init, S32, MPP_ENC_RC_CFG_CHANGE_QP_INIT, rc, qp_init) \
ENTRY(h265, qp_min, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE, rc, qp_min) \
ENTRY(h265, qp_max, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE, rc, qp_max) \
ENTRY(h265, qp_min_i, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I, rc, qp_min_i) \
ENTRY(h265, qp_max_i, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I, rc, qp_max_i) \
ENTRY(h265, qp_step, S32, MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP, rc, qp_max_step) \
ENTRY(h265, qp_delta_ip, S32, MPP_ENC_RC_CFG_CHANGE_QP_IP, rc, qp_delta_ip) \
ENTRY(h265, sao_luma_disable, S32, MPP_ENC_H265_CFG_SAO_CHANGE, h265, sao_cfg.slice_sao_luma_disable) \
ENTRY(h265, sao_chroma_disable, S32, MPP_ENC_H265_CFG_SAO_CHANGE, h265, sao_cfg.slice_sao_chroma_disable) \
ENTRY(h265, sao_bit_ratio, S32, MPP_ENC_H265_CFG_SAO_CHANGE, h265, sao_cfg.sao_bit_ratio) \
ENTRY(h265, lpf_acs_sli_en, U32, MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE, h265, lpf_acs_sli_en) \
ENTRY(h265, lpf_acs_tile_disable, U32, MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE, h265, lpf_acs_tile_disable) \
ENTRY(h265, auto_tile, S32, MPP_ENC_H265_CFG_TILE_CHANGE, h265, auto_tile) \
ENTRY(h265, max_tid, S32, MPP_ENC_H265_CFG_CHANGE_MAX_TID, h265, max_tid) \
ENTRY(h265, max_ltr, S32, MPP_ENC_H265_CFG_CHANGE_MAX_LTR, h265, max_ltr_frames) \
ENTRY(h265, base_layer_pid, S32, MPP_ENC_H265_CFG_CHANGE_BASE_LAYER_PID, h265, base_layer_pid) \
ENTRY(h265, const_intra, S32, MPP_ENC_H265_CFG_CHANGE_CONST_INTRA, h265, const_intra_pred) \
ENTRY(h265, lcu_size, S32, MPP_ENC_H265_CFG_CHANGE_LCU_SIZE, h265, max_cu_size) \
ENTRY(h265, vui_en, U32, MPP_ENC_H265_CFG_CHANGE_VUI, h265, vui.vui_en) \
STRUCT_START(h265); \
ENTRY(prefix, s32, rk_s32, profile, FLAG_BASE(0), h265, profile); \
ENTRY(prefix, s32, rk_s32, tier, FLAG_PREV, h265, tier); \
ENTRY(prefix, s32, rk_s32, level, FLAG_PREV, h265, level); \
ENTRY(prefix, u32, rk_u32, scaling_list, FLAG_INCR, h265, trans_cfg, scaling_list_mode); \
ENTRY(prefix, s32, rk_s32, cb_qp_offset, FLAG_PREV, h265, trans_cfg, cb_qp_offset); \
ENTRY(prefix, s32, rk_s32, cr_qp_offset, FLAG_PREV, h265, trans_cfg, cr_qp_offset); \
ENTRY(prefix, s32, rk_s32, diff_cu_qp_delta_depth, FLAG_PREV, h265, trans_cfg, diff_cu_qp_delta_depth); \
ENTRY(prefix, u32, rk_u32, dblk_disable, FLAG_INCR, h265, dblk_cfg, slice_deblocking_filter_disabled_flag); \
ENTRY(prefix, s32, rk_s32, dblk_alpha, FLAG_PREV, h265, dblk_cfg, slice_beta_offset_div2); \
ENTRY(prefix, s32, rk_s32, dblk_beta, FLAG_PREV, h265, dblk_cfg, slice_tc_offset_div2); \
ALIAS(prefix, s32, rk_s32, qp_init, FLAG_REPLAY(0), rc, qp_init); \
ALIAS(prefix, s32, rk_s32, qp_min, FLAG_REPLAY(1), rc, qp_min); \
ALIAS(prefix, s32, rk_s32, qp_max, FLAG_REPLAY(1), rc, qp_max); \
ALIAS(prefix, s32, rk_s32, qp_min_i, FLAG_REPLAY(2), rc, qp_min_i); \
ALIAS(prefix, s32, rk_s32, qp_max_i, FLAG_REPLAY(2), rc, qp_max_i); \
ALIAS(prefix, s32, rk_s32, qp_step, FLAG_REPLAY(3), rc, qp_max_step); \
ALIAS(prefix, s32, rk_s32, qp_delta_ip, FLAG_REPLAY(4), rc, qp_delta_ip); \
ENTRY(prefix, s32, rk_s32, sao_luma_disable, FLAG_INCR, h265, sao_cfg, slice_sao_luma_disable); \
ENTRY(prefix, s32, rk_s32, sao_chroma_disable, FLAG_PREV, h265, sao_cfg, slice_sao_chroma_disable); \
ENTRY(prefix, s32, rk_s32, sao_bit_ratio, FLAG_PREV, h265, sao_cfg, sao_bit_ratio); \
ENTRY(prefix, u32, rk_u32, lpf_acs_sli_en, FLAG_INCR, h265, lpf_acs_sli_en); \
ENTRY(prefix, u32, rk_u32, lpf_acs_tile_disable, FLAG_INCR, h265, lpf_acs_tile_disable); \
ENTRY(prefix, s32, rk_s32, auto_tile, FLAG_INCR, h265, auto_tile); \
ENTRY(prefix, s32, rk_s32, max_tid, FLAG_INCR, h265, max_tid); \
ENTRY(prefix, s32, rk_s32, max_ltr, FLAG_INCR, h265, max_ltr_frames); \
ENTRY(prefix, s32, rk_s32, base_layer_pid, FLAG_INCR, h265, base_layer_pid); \
ENTRY(prefix, s32, rk_s32, const_intra, FLAG_INCR, h265, const_intra_pred); \
ENTRY(prefix, s32, rk_s32, lcu_size, FLAG_INCR, h265, max_cu_size); \
ENTRY(prefix, s32, rk_s32, vui_en, FLAG_INCR, h265, vui, vui_en); \
STRUCT_END(h265); \
/* vp8 config */ \
ENTRY(vp8, qp_init, S32, MPP_ENC_RC_CFG_CHANGE_QP_INIT, rc, qp_init) \
ENTRY(vp8, qp_min, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE, rc, qp_min) \
ENTRY(vp8, qp_max, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE, rc, qp_max) \
ENTRY(vp8, qp_min_i, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I, rc, qp_min_i) \
ENTRY(vp8, qp_max_i, S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I, rc, qp_max_i) \
ENTRY(vp8, qp_step, S32, MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP, rc, qp_max_step) \
ENTRY(vp8, qp_delta_ip, S32, MPP_ENC_RC_CFG_CHANGE_QP_IP, rc, qp_delta_ip) \
ENTRY(vp8, disable_ivf, S32, MPP_ENC_VP8_CFG_CHANGE_DIS_IVF, vp8, disable_ivf) \
STRUCT_START(vp8); \
ENTRY(prefix, s32, rk_s32, disable_ivf, FLAG_BASE(0), vp8, disable_ivf); \
ALIAS(prefix, s32, rk_s32, qp_init, FLAG_REPLAY(0), rc, qp_init); \
ALIAS(prefix, s32, rk_s32, qp_min, FLAG_REPLAY(1), rc, qp_min); \
ALIAS(prefix, s32, rk_s32, qp_max, FLAG_REPLAY(1), rc, qp_max); \
ALIAS(prefix, s32, rk_s32, qp_min_i, FLAG_REPLAY(2), rc, qp_min_i); \
ALIAS(prefix, s32, rk_s32, qp_max_i, FLAG_REPLAY(2), rc, qp_max_i); \
ALIAS(prefix, s32, rk_s32, qp_step, FLAG_REPLAY(3), rc, qp_max_step); \
ALIAS(prefix, s32, rk_s32, qp_delta_ip, FLAG_REPLAY(4), rc, qp_delta_ip); \
STRUCT_END(vp8); \
/* jpeg config */ \
ENTRY(jpeg, quant, S32, MPP_ENC_JPEG_CFG_CHANGE_QP, jpeg, quant) \
ENTRY(jpeg, qtable_y, Ptr, MPP_ENC_JPEG_CFG_CHANGE_QTABLE, jpeg, qtable_y) \
ENTRY(jpeg, qtable_u, Ptr, MPP_ENC_JPEG_CFG_CHANGE_QTABLE, jpeg, qtable_u) \
ENTRY(jpeg, qtable_v, Ptr, MPP_ENC_JPEG_CFG_CHANGE_QTABLE, jpeg, qtable_v) \
ENTRY(jpeg, q_factor, S32, MPP_ENC_JPEG_CFG_CHANGE_QFACTOR, jpeg, q_factor) \
ENTRY(jpeg, qf_max, S32, MPP_ENC_JPEG_CFG_CHANGE_QFACTOR, jpeg, qf_max) \
ENTRY(jpeg, qf_min, S32, MPP_ENC_JPEG_CFG_CHANGE_QFACTOR, jpeg, qf_min) \
STRUCT_START(jpeg); \
ENTRY(prefix, st, rk_s32, q_mode, FLAG_BASE(0), jpeg, q_mode); \
ENTRY(prefix, s32, rk_s32, quant, FLAG_INCR, jpeg, quant_ext); \
ENTRY(prefix, s32, rk_s32, q_factor, FLAG_INCR, jpeg, q_factor_ext); \
ENTRY(prefix, s32, rk_s32, qf_max, FLAG_PREV, jpeg, qf_max_ext); \
ENTRY(prefix, s32, rk_s32, qf_min, FLAG_PREV, jpeg, qf_min_ext); \
ENTRY(prefix, st, void *, qtable_y, FLAG_INCR, jpeg, qtable_y); \
ENTRY(prefix, st, void *, qtable_u, FLAG_PREV, jpeg, qtable_u); \
ENTRY(prefix, st, void *, qtable_v, FLAG_PREV, jpeg, qtable_v); \
STRUCT_END(jpeg); \
/* split config */ \
ENTRY(split, mode, U32, MPP_ENC_SPLIT_CFG_CHANGE_MODE, split, split_mode) \
ENTRY(split, arg, U32, MPP_ENC_SPLIT_CFG_CHANGE_ARG, split, split_arg) \
ENTRY(split, out, U32, MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT, split, split_out) \
STRUCT_START(split); \
ENTRY(prefix, u32, rk_u32, mode, FLAG_BASE(0), split, split_mode) \
ENTRY(prefix, u32, rk_u32, arg, FLAG_INCR, split, split_arg) \
ENTRY(prefix, u32, rk_u32, out, FLAG_INCR, split, split_out) \
STRUCT_END(split); \
/* hardware detail config */ \
ENTRY(hw, qp_row, S32, MPP_ENC_HW_CFG_CHANGE_QP_ROW, hw, qp_delta_row) \
ENTRY(hw, qp_row_i, S32, MPP_ENC_HW_CFG_CHANGE_QP_ROW_I, hw, qp_delta_row_i) \
ENTRY(hw, aq_thrd_i, St, MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I, hw, aq_thrd_i) \
ENTRY(hw, aq_thrd_p, St, MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P, hw, aq_thrd_p) \
ENTRY(hw, aq_step_i, St, MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I, hw, aq_step_i) \
ENTRY(hw, aq_step_p, St, MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P, hw, aq_step_p) \
ENTRY(hw, mb_rc_disable, S32, MPP_ENC_HW_CFG_CHANGE_MB_RC, hw, mb_rc_disable) \
ENTRY(hw, aq_rnge_arr, St, MPP_ENC_HW_CFG_CHANGE_AQ_RNGE_ARR, hw, aq_rnge_arr) \
ENTRY(hw, mode_bias, St, MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS, hw, mode_bias) \
ENTRY(hw, skip_bias_en, S32, MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS, hw, skip_bias_en) \
ENTRY(hw, skip_sad, S32, MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS, hw, skip_sad) \
ENTRY(hw, skip_bias, S32, MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS, hw, skip_bias) \
ENTRY(hw, qbias_i, S32, MPP_ENC_HW_CFG_CHANGE_QBIAS_I, hw, qbias_i) \
ENTRY(hw, qbias_p, S32, MPP_ENC_HW_CFG_CHANGE_QBIAS_P, hw, qbias_p) \
ENTRY(hw, qbias_en, S32, MPP_ENC_HW_CFG_CHANGE_QBIAS_EN, hw, qbias_en) \
ENTRY(hw, qbias_arr, St, MPP_ENC_HW_CFG_CHANGE_QBIAS_ARR, hw, qbias_arr) \
ENTRY(hw, flt_str_i, S32, MPP_ENC_HW_CFG_CHANGE_FLT_STR_I, hw, flt_str_i) \
ENTRY(hw, flt_str_p, S32, MPP_ENC_HW_CFG_CHANGE_FLT_STR_P, hw, flt_str_p) \
STRUCT_START(hw); \
ENTRY(prefix, s32, rk_s32, qp_row, FLAG_BASE(0), hw, qp_delta_row) \
ENTRY(prefix, s32, rk_s32, qp_row_i, FLAG_INCR, hw, qp_delta_row_i) \
STRCT(prefix, st, void *, aq_thrd_i, FLAG_INCR, hw, aq_thrd_i) \
STRCT(prefix, st, void *, aq_thrd_p, FLAG_INCR, hw, aq_thrd_p) \
STRCT(prefix, st, void *, aq_step_i, FLAG_INCR, hw, aq_step_i) \
STRCT(prefix, st, void *, aq_step_p, FLAG_INCR, hw, aq_step_p) \
ENTRY(prefix, s32, rk_s32, mb_rc_disable, FLAG_INCR, hw, mb_rc_disable) \
STRCT(prefix, st, void *, aq_rnge_arr, FLAG_INCR, hw, aq_rnge_arr) \
STRCT(prefix, st, void *, mode_bias, FLAG_INCR, hw, mode_bias) \
ENTRY(prefix, s32, rk_s32, skip_bias_en, FLAG_INCR, hw, skip_bias_en) \
ENTRY(prefix, s32, rk_s32, skip_sad, FLAG_PREV, hw, skip_sad) \
ENTRY(prefix, s32, rk_s32, skip_bias, FLAG_PREV, hw, skip_bias) \
ENTRY(prefix, s32, rk_s32, qbias_i, FLAG_INCR, hw, qbias_i) \
ENTRY(prefix, s32, rk_s32, qbias_p, FLAG_INCR, hw, qbias_p) \
ENTRY(prefix, s32, rk_s32, qbias_en, FLAG_INCR, hw, qbias_en) \
STRCT(prefix, st, void *, qbias_arr, FLAG_INCR, hw, qbias_arr) \
ENTRY(prefix, s32, rk_s32, flt_str_i, FLAG_INCR, hw, flt_str_i) \
ENTRY(prefix, s32, rk_s32, flt_str_p, FLAG_INCR, hw, flt_str_p) \
STRUCT_END(hw); \
/* quality fine tuning config */ \
ENTRY(tune, scene_mode, S32, MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE, tune, scene_mode) \
ENTRY(tune, se_mode, S32, MPP_ENC_TUNE_CFG_CHANGE_SE_MODE, tune, se_mode) \
ENTRY(tune, deblur_en, S32, MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_EN, tune, deblur_en) \
ENTRY(tune, deblur_str, S32, MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_STR, tune, deblur_str) \
ENTRY(tune, anti_flicker_str,S32, MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR,tune, anti_flicker_str) \
ENTRY(tune, lambda_idx_i, S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I, tune, lambda_idx_i) \
ENTRY(tune, lambda_idx_p, S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P, tune, lambda_idx_p) \
ENTRY(tune, atr_str_i, S32, MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_I, tune, atr_str_i) \
ENTRY(tune, atr_str_p, S32, MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_P, tune, atr_str_p) \
ENTRY(tune, atl_str, S32, MPP_ENC_TUNE_CFG_CHANGE_ATL_STR, tune, atl_str) \
ENTRY(tune, sao_str_i, S32, MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_I, tune, sao_str_i) \
ENTRY(tune, sao_str_p, S32, MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_P, tune, sao_str_p) \
ENTRY(tune, rc_container, S32, MPP_ENC_TUNE_CFG_CHANGE_RC_CONTAINER, tune, rc_container) \
ENTRY(tune, vmaf_opt, S32, MPP_ENC_TUNE_CFG_CHANGE_VMAF_OPT, tune, vmaf_opt) \
ENTRY(tune, motion_static_switch_enable, S32, MPP_ENC_TUNE_CFG_CHANGE_MOTION_STATIC_SWITCH_ENABLE, tune, motion_static_switch_enable) \
ENTRY(tune, atf_str, S32, MPP_ENC_TUNE_CFG_CHANGE_ATF_STR, tune, atf_str) \
ENTRY(tune, lgt_chg_lvl, S32, MPP_ENC_TUNE_CFG_CHANGE_LGT_CHG_LVL, tune, lgt_chg_lvl) \
ENTRY(tune, static_frm_num, S32, MPP_ENC_TUNE_CFG_CHANGE_STATIC_FRM_NUM, tune, static_frm_num) \
ENTRY(tune, madp16_th, S32, MPP_ENC_TUNE_CFG_CHANGE_MADP16_TH, tune, madp16_th) \
ENTRY(tune, skip16_wgt, S32, MPP_ENC_TUNE_CFG_CHANGE_SKIP16_WGT, tune, skip16_wgt) \
ENTRY(tune, skip32_wgt, S32, MPP_ENC_TUNE_CFG_CHANGE_SKIP32_WGT, tune, skip32_wgt) \
ENTRY(tune, speed, S32, MPP_ENC_TUNE_CFG_CHANGE_SPEED, tune, speed) \
ENTRY(tune, bg_delta_qp_i, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, bg_delta_qp_i) \
ENTRY(tune, bg_delta_qp_p, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, bg_delta_qp_p) \
ENTRY(tune, fg_delta_qp_i, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, fg_delta_qp_i) \
ENTRY(tune, fg_delta_qp_p, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, fg_delta_qp_p) \
ENTRY(tune, bmap_qpmin_i, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, bmap_qpmin_i) \
ENTRY(tune, bmap_qpmin_p, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, bmap_qpmin_p) \
ENTRY(tune, bmap_qpmax_i, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, bmap_qpmax_i) \
ENTRY(tune, bmap_qpmax_p, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, bmap_qpmax_p) \
ENTRY(tune, min_bg_fqp, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, min_bg_fqp) \
ENTRY(tune, max_bg_fqp, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, max_bg_fqp) \
ENTRY(tune, min_fg_fqp, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, min_fg_fqp) \
ENTRY(tune, max_fg_fqp, S32, MPP_ENC_TUNE_CFG_CHANGE_SMART_V3_CFG, tune, max_fg_fqp)
STRUCT_START(tune); \
ENTRY(prefix, s32, rk_s32, scene_mode, FLAG_BASE(0), tune, scene_mode); \
ENTRY(prefix, s32, rk_s32, se_mode, FLAG_INCR, tune, se_mode); \
ENTRY(prefix, s32, rk_s32, deblur_en, FLAG_INCR, tune, deblur_en); \
ENTRY(prefix, s32, rk_s32, deblur_str, FLAG_INCR, tune, deblur_str); \
ENTRY(prefix, s32, rk_s32, anti_flicker_str, FLAG_INCR, tune, anti_flicker_str); \
ENTRY(prefix, s32, rk_s32, lambda_idx_i, FLAG_INCR, tune, lambda_idx_i); \
ENTRY(prefix, s32, rk_s32, lambda_idx_p, FLAG_INCR, tune, lambda_idx_p); \
ENTRY(prefix, s32, rk_s32, atr_str_i, FLAG_INCR, tune, atr_str_i); \
ENTRY(prefix, s32, rk_s32, atr_str_p, FLAG_INCR, tune, atr_str_p); \
ENTRY(prefix, s32, rk_s32, atl_str, FLAG_INCR, tune, atl_str); \
ENTRY(prefix, s32, rk_s32, sao_str_i, FLAG_INCR, tune, sao_str_i); \
ENTRY(prefix, s32, rk_s32, sao_str_p, FLAG_INCR, tune, sao_str_p); \
ENTRY(prefix, s32, rk_s32, rc_container, FLAG_INCR, tune, rc_container); \
ENTRY(prefix, s32, rk_s32, vmaf_opt, FLAG_INCR, tune, vmaf_opt); \
ENTRY(prefix, s32, rk_s32, motion_static_switch_enable, FLAG_INCR, tune, motion_static_switch_enable); \
ENTRY(prefix, s32, rk_s32, atf_str, FLAG_INCR, tune, atf_str); \
ENTRY(prefix, s32, rk_s32, lgt_chg_lvl, FLAG_INCR, tune, lgt_chg_lvl); \
ENTRY(prefix, s32, rk_s32, static_frm_num, FLAG_INCR, tune, static_frm_num); \
ENTRY(prefix, s32, rk_s32, madp16_th, FLAG_INCR, tune, madp16_th); \
ENTRY(prefix, s32, rk_s32, skip16_wgt, FLAG_INCR, tune, skip16_wgt); \
ENTRY(prefix, s32, rk_s32, skip32_wgt, FLAG_INCR, tune, skip32_wgt); \
ENTRY(prefix, s32, rk_s32, speed, FLAG_INCR, tune, speed); \
ENTRY(prefix, s32, rk_s32, bg_delta_qp_i, FLAG_INCR, tune, bg_delta_qp_i); \
ENTRY(prefix, s32, rk_s32, bg_delta_qp_p, FLAG_PREV, tune, bg_delta_qp_p); \
ENTRY(prefix, s32, rk_s32, fg_delta_qp_i, FLAG_PREV, tune, fg_delta_qp_i); \
ENTRY(prefix, s32, rk_s32, fg_delta_qp_p, FLAG_PREV, tune, fg_delta_qp_p); \
ENTRY(prefix, s32, rk_s32, bmap_qpmin_i, FLAG_PREV, tune, bmap_qpmin_i); \
ENTRY(prefix, s32, rk_s32, bmap_qpmin_p, FLAG_PREV, tune, bmap_qpmin_p); \
ENTRY(prefix, s32, rk_s32, bmap_qpmax_i, FLAG_PREV, tune, bmap_qpmax_i); \
ENTRY(prefix, s32, rk_s32, bmap_qpmax_p, FLAG_PREV, tune, bmap_qpmax_p); \
ENTRY(prefix, s32, rk_s32, min_bg_fqp, FLAG_PREV, tune, min_bg_fqp); \
ENTRY(prefix, s32, rk_s32, max_bg_fqp, FLAG_PREV, tune, max_bg_fqp); \
ENTRY(prefix, s32, rk_s32, min_fg_fqp, FLAG_PREV, tune, min_fg_fqp); \
ENTRY(prefix, s32, rk_s32, max_fg_fqp, FLAG_PREV, tune, max_fg_fqp); \
ENTRY(prefix, s32, rk_s32, fg_area, FLAG_PREV, tune, fg_area); \
ENTRY(prefix, s32, rk_s32, qpmap_en, FLAG_INCR, tune, qpmap_en); \
STRUCT_END(tune); \
CFG_DEF_END()
static void mpp_enc_cfg_srv_init()
static rk_s32 mpp_enc_cfg_impl_init(void *entry, KmppObj obj, const char *caller)
{
MppEncCfgSrv *srv = srv_enc_cfg;
mpp_env_get_u32("mpp_enc_cfg_debug", &mpp_enc_cfg_debug, mpp_enc_cfg_debug);
if (srv)
return ;
srv = mpp_calloc(MppEncCfgSrv, 1);
if (!srv) {
mpp_err_f("failed to allocate enc cfg set service\n");
return ;
}
srv_enc_cfg = srv;
mpp_trie_init(&srv->trie, "MppEncCfg");
if (srv->trie) {
ENTRY_TABLE(EXPAND_AS_TRIE)
mpp_trie_add_info(srv->trie, NULL, NULL, 0);
}
enc_cfg_dbg_func("info cnt %d node cnt %d size %d\n",
mpp_trie_get_info_count(srv->trie),
mpp_trie_get_node_count(srv->trie),
mpp_trie_get_buf_size(srv->trie));
}
static void mpp_enc_cfg_srv_deinit()
{
MppEncCfgSrv *srv = srv_enc_cfg;
if (!srv)
return ;
if (srv->trie) {
mpp_trie_deinit(srv->trie);
srv->trie = NULL;
}
MPP_FREE(srv_enc_cfg);
}
MPP_SINGLETON(MPP_SGLN_ENC_CFG, mpp_enc_cfg, mpp_enc_cfg_srv_init, mpp_enc_cfg_srv_deinit)
static MppTrieInfo *service_get_info(const char *name)
{
MppEncCfgSrv *srv = get_srv_enc_cfg_f();
if (!srv)
return NULL;
return mpp_trie_get_info(srv->trie, name);
}
static void mpp_enc_cfg_set_default(MppEncCfgSet *cfg)
{
RK_U32 i;
MppEncCfgSet *cfg = (MppEncCfgSet *)entry;
rk_u32 i;
cfg->rc.max_reenc_times = 1;
@ -355,104 +294,87 @@ static void mpp_enc_cfg_set_default(MppEncCfgSet *cfg)
cfg->hw.skip_sad = 8;
cfg->hw.skip_bias = 8;
(void) obj;
(void) caller;
return rk_ok;
}
static rk_s32 mpp_enc_cfg_impl_dump(void *entry)
{
MppEncCfgSet *cfg = (MppEncCfgSet *)entry;
rk_u32 *flag;
if (!cfg)
return rk_nok;
flag = mpp_enc_cfg_prep_change(cfg);
mpp_logi("cfg %p prep flag %p\n", cfg, flag);
mpp_logi("prep change %x\n", *flag);
mpp_logi("width %4d -> %4d\n", cfg->prep.width, cfg->prep.width_set);
mpp_logi("height %4d -> %4d\n", cfg->prep.height, cfg->prep.height_set);
mpp_logi("hor_stride %d\n", cfg->prep.hor_stride);
mpp_logi("ver_stride %d\n", cfg->prep.ver_stride);
mpp_logi("format_in %d\n", cfg->prep.format);
mpp_logi("format_out %d\n", cfg->prep.format_out);
mpp_logi("rotation %d -> %d\n", cfg->prep.rotation, cfg->prep.rotation_ext);
mpp_logi("mirroring %d -> %d\n", cfg->prep.mirroring, cfg->prep.mirroring_ext);
return rk_ok;
}
#define KMPP_OBJ_NAME mpp_enc_cfg
#define KMPP_OBJ_INTF_TYPE MppEncCfg
#define KMPP_OBJ_IMPL_TYPE MppEncCfgSet
#define KMPP_OBJ_SGLN_ID MPP_SGLN_ENC_CFG
#define KMPP_OBJ_FUNC_INIT mpp_enc_cfg_impl_init
#define KMPP_OBJ_FUNC_DUMP mpp_enc_cfg_impl_dump
#define KMPP_OBJ_ENTRY_TABLE MPP_ENC_CFG_ENTRY_TABLE
#define KMPP_OBJ_ACCESS_DISABLE
#define KMPP_OBJ_HIERARCHY_ENABLE
#include "kmpp_obj_helper.h"
#define TO_CHANGE_POS(name, ...) \
static rk_s32 to_change_pos_##name(void) \
{ \
static rk_s32 CONCAT_US(name, flag, pos) = -1; \
if (CONCAT_US(name, flag, pos) < 0) { \
KmppEntry *tbl = NULL; \
kmpp_objdef_get_entry(mpp_enc_cfg_def, CONCAT_STR(name, __VA_ARGS__), &tbl); \
CONCAT_US(name, flag, pos) = tbl ? (tbl->tbl.flag_offset / 8) : 0; \
} \
return CONCAT_US(name, flag, pos); \
}
/* vcodec type -> base.change */
TO_CHANGE_POS(rc, mode)
TO_CHANGE_POS(prep, width)
TO_CHANGE_POS(h264, stream_type)
TO_CHANGE_POS(h265, profile)
TO_CHANGE_POS(vp8, disable_ivf)
TO_CHANGE_POS(jpeg, q_mode)
TO_CHANGE_POS(hw, qp_row)
TO_CHANGE_POS(tune, scene_mode)
MPP_RET mpp_enc_cfg_init(MppEncCfg *cfg)
{
MppEncCfgImpl *impl = NULL;
MPP_RET ret = MPP_OK;
if (!cfg) {
mpp_err_f("invalid NULL input config\n");
return MPP_ERR_NULL_PTR;
}
mpp_env_get_u32("mpp_enc_cfg_debug", &mpp_enc_cfg_debug, 0);
*cfg = NULL;
do {
impl = mpp_calloc(MppEncCfgImpl, 1);
if (!impl) {
mpp_err_f("create MppEncCfgImpl failed\n");
ret = MPP_ERR_NOMEM;
break;
}
impl->cfg = mpp_calloc(MppEncCfgSet, 1);
if (!impl->cfg) {
mpp_err_f("create MppEncCfgSet failed\n");
ret = MPP_ERR_NOMEM;
break;
}
/* NOTE: compatible to old struct size */
impl->cfg->size = sizeof(*impl->cfg);
mpp_enc_cfg_set_default(impl->cfg);
*cfg = impl;
} while (0);
if (ret) {
if (impl) {
MPP_FREE(impl->cfg);
MPP_FREE(impl);
}
}
return ret;
return mpp_enc_cfg_get(cfg);
}
RK_S32 mpp_enc_cfg_init_k(MppEncCfg *cfg)
{
static const char *kcfg_name = "KmppVencStCfg";
MppEncCfgImpl *impl = NULL;
if (!cfg) {
mpp_err_f("invalid NULL input config\n");
return MPP_ERR_NULL_PTR;
}
mpp_env_get_u32("mpp_enc_cfg_debug", &mpp_enc_cfg_debug, 0);
*cfg = NULL;
impl = mpp_calloc(MppEncCfgImpl, 1);
if (!impl) {
mpp_err_f("create MppEncCfgImpl failed\n");
return MPP_ERR_NOMEM;
}
impl->is_kobj = 1;
kmpp_obj_get_by_name_f(&impl->obj, kcfg_name);
if (!impl->obj) {
mpp_err_f("failed to get obj by name %s\n", kcfg_name);
MPP_FREE(impl);
return MPP_ERR_NOMEM;
}
*cfg = impl;
return MPP_OK;
return mpp_venc_kcfg_init(cfg, MPP_VENC_KCFG_TYPE_ST_CFG);
}
RK_S32 mpp_enc_cfg_deinit(MppEncCfg cfg)
{
MppEncCfgImpl *impl = (MppEncCfgImpl *)cfg;
if (!impl) {
mpp_err_f("invalid NULL input config\n");
return MPP_ERR_NULL_PTR;
}
if (!impl->is_kobj) {
MPP_FREE(impl->cfg);
} else {
kmpp_obj_put_f(impl->obj);
}
MPP_FREE(impl);
return MPP_OK;
return kmpp_obj_put_f(cfg);
}
#define kmpp_obj_set_S32(obj, name, val) \
@ -471,23 +393,7 @@ RK_S32 mpp_enc_cfg_deinit(MppEncCfg cfg)
#define ENC_CFG_SET_ACCESS(func_name, in_type, cfg_type) \
MPP_RET func_name(MppEncCfg cfg, const char *name, in_type val) \
{ \
MppEncCfgImpl *impl = (MppEncCfgImpl *)cfg; \
if (!impl || !impl->cfg || !name) { \
mpp_err_f("invalid input cfg %p name %p\n", cfg, name); \
return MPP_ERR_NULL_PTR; \
} \
if (impl->is_kobj) { \
return kmpp_obj_set_##cfg_type(impl->obj, name, val); \
} else { \
MppEncCfgSet *p = impl->cfg; \
MppTrieInfo *node = service_get_info(name); \
MppCfgInfo *info = (MppCfgInfo *)mpp_trie_info_ctx(node); \
if (CHECK_CFG_INFO(info, name, CFG_FUNC_TYPE_##cfg_type)) { \
return MPP_NOK; \
} \
enc_cfg_dbg_set("name %s type %s\n", mpp_trie_info_name(node), strof_cfg_type(info->data_type)); \
return MPP_CFG_SET_##cfg_type(info, p, val); \
} \
return kmpp_obj_set_##cfg_type((KmppObj)cfg, name, val); \
}
ENC_CFG_SET_ACCESS(mpp_enc_cfg_set_s32, RK_S32, S32);
@ -513,23 +419,7 @@ ENC_CFG_SET_ACCESS(mpp_enc_cfg_set_st, void *, St);
#define ENC_CFG_GET_ACCESS(func_name, in_type, cfg_type) \
MPP_RET func_name(MppEncCfg cfg, const char *name, in_type *val) \
{ \
MppEncCfgImpl *impl = (MppEncCfgImpl *)cfg; \
if (!impl || !impl->cfg || !name) { \
mpp_err_f("invalid input cfg %p name %p\n", cfg, name); \
return MPP_ERR_NULL_PTR; \
} \
if (impl->is_kobj) { \
return kmpp_obj_get_##cfg_type(impl->obj, name, val); \
} else { \
MppEncCfgSet *p = impl->cfg; \
MppTrieInfo *node = service_get_info(name); \
MppCfgInfo *info = (MppCfgInfo *)mpp_trie_info_ctx(node); \
if (CHECK_CFG_INFO(info, name, CFG_FUNC_TYPE_##cfg_type)) { \
return MPP_NOK; \
} \
enc_cfg_dbg_set("name %s type %s\n", mpp_trie_info_name(node), strof_cfg_type(info->data_type)); \
return MPP_CFG_GET_##cfg_type(info, p, val); \
} \
return kmpp_obj_get_##cfg_type((KmppObj)cfg, name, val); \
}
ENC_CFG_GET_ACCESS(mpp_enc_cfg_get_s32, RK_S32, S32);
@ -541,16 +431,14 @@ ENC_CFG_GET_ACCESS(mpp_enc_cfg_get_st, void , St);
void mpp_enc_cfg_show(void)
{
MppEncCfgSrv *srv = get_srv_enc_cfg_f();
MppTrie trie = kmpp_objdef_get_trie(mpp_enc_cfg_def);
MppTrieInfo *root;
MppTrie trie;
if (!srv)
if (!trie)
return;
mpp_log("dumping valid configure string start\n");
trie = srv->trie;
root = mpp_trie_get_info_first(trie);
if (root) {
MppTrieInfo *node = root;
@ -560,11 +448,12 @@ void mpp_enc_cfg_show(void)
if (mpp_trie_info_is_self(node))
continue;
if (node->ctx_len == sizeof(MppCfgInfo)) {
MppCfgInfo *info = (MppCfgInfo *)mpp_trie_info_ctx(node);
if (node->ctx_len == sizeof(KmppEntry)) {
KmppEntry *entry = (KmppEntry *)mpp_trie_info_ctx(node);
mpp_log("%-*s type %s - %d:%d\n", len, mpp_trie_info_name(node),
strof_cfg_type(info->data_type), info->data_offset, info->data_size);
mpp_log("%-*s %-6s | %-6d | %-4d | %-4x\n", len, mpp_trie_info_name(node),
strof_elem_type(entry->tbl.elem_type), entry->tbl.elem_offset,
entry->tbl.elem_size, entry->tbl.flag_offset);
} else {
mpp_log("%-*s size - %d\n", len, mpp_trie_info_name(node), node->ctx_len);
}
@ -576,3 +465,20 @@ void mpp_enc_cfg_show(void)
sizeof(MppEncCfgSet), mpp_trie_get_info_count(trie),
mpp_trie_get_node_count(trie), mpp_trie_get_buf_size(trie));
}
#define GET_ENC_CFG_CHANGE(name) \
rk_u32 *mpp_enc_cfg_##name##_change(MppEncCfgSet *cfg) \
{ \
if (cfg) \
return (rk_u32 *)(POS_TO_FLAG(cfg, to_change_pos_##name())); \
return NULL; \
}
GET_ENC_CFG_CHANGE(prep)
GET_ENC_CFG_CHANGE(rc)
GET_ENC_CFG_CHANGE(hw)
GET_ENC_CFG_CHANGE(tune)
GET_ENC_CFG_CHANGE(h264)
GET_ENC_CFG_CHANGE(h265)
GET_ENC_CFG_CHANGE(jpeg)
GET_ENC_CFG_CHANGE(vp8)

2
mpp/base/test/mpp_enc_cfg_test.c
View file

@ -46,7 +46,7 @@ int main()
-1, -1, -1, -1,
};
MppEncCfgSet *impl = (MppEncCfgSet *)cfg;
MppEncCfgSet *impl = (MppEncCfgSet *)kmpp_obj_to_entry(cfg);
mpp_log("before set: rc mode %d bps_target %d\n",
impl->rc.rc_mode, impl->rc.bps_target);

378
mpp/codec/enc/h264/h264e_api_v2.c
View file

@ -143,7 +143,6 @@ static void init_h264e_cfg_set(MppEncCfgSet *cfg, MppClientType type)
* 720p
* YUV420SP
*/
prep->change = 0;
prep->width = 1280;
prep->height = 720;
prep->hor_stride = 1280;
@ -167,7 +166,6 @@ static void init_h264e_cfg_set(MppEncCfgSet *cfg, MppClientType type)
* 30fps
* gop 60
*/
rc_cfg->change = 0;
rc_cfg->quality = MPP_ENC_RC_QUALITY_MEDIUM;
rc_cfg->bps_target = 2000 * 1000;
rc_cfg->bps_max = rc_cfg->bps_target * 5 / 4;
@ -274,336 +272,6 @@ static MPP_RET h264e_deinit(void *ctx)
return MPP_OK;
}
static MPP_RET h264e_proc_prep_cfg(MppEncPrepCfg *dst, MppEncPrepCfg *src)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
mpp_assert(change);
if (change) {
RK_S32 mirroring;
RK_S32 rotation;
MppEncPrepCfg bak = *dst;
if (change & MPP_ENC_PREP_CFG_CHANGE_FORMAT)
dst->format = src->format;
if (change & MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE)
dst->range = src->range;
if (change & MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE)
dst->color = src->color;
if (change & MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME)
dst->colorprim = src->colorprim;
if (change & MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC)
dst->colortrc = src->colortrc;
if (change & MPP_ENC_PREP_CFG_CHANGE_ROTATION)
dst->rotation_ext = src->rotation_ext;
if (change & MPP_ENC_PREP_CFG_CHANGE_MIRRORING)
dst->mirroring_ext = src->mirroring_ext;
if (change & MPP_ENC_PREP_CFG_CHANGE_FLIP)
dst->flip = src->flip;
if (change & MPP_ENC_PREP_CFG_CHANGE_DENOISE)
dst->denoise = src->denoise;
if (change & MPP_ENC_PREP_CFG_CHANGE_SHARPEN)
dst->sharpen = src->sharpen;
// parameter checking
if (dst->rotation_ext >= MPP_ENC_ROT_BUTT || dst->rotation_ext < 0 ||
dst->mirroring_ext < 0 || dst->flip < 0) {
mpp_err("invalid trans: rotation %d, mirroring %d\n", dst->rotation_ext, dst->mirroring_ext);
ret = MPP_ERR_VALUE;
}
/* For unifying the encoder's params used by CFG_SET and CFG_GET command,
* there is distinction between user's set and set in hal.
* User can externally set rotation_ext, mirroring_ext and flip,
* which should be transformed to mirroring and rotation in hal.
*/
mirroring = dst->mirroring_ext;
rotation = dst->rotation_ext;
if (dst->flip) {
mirroring = !mirroring;
rotation += MPP_ENC_ROT_180;
rotation &= MPP_ENC_ROT_270;
}
dst->mirroring = mirroring;
dst->rotation = rotation;
if ((change & MPP_ENC_PREP_CFG_CHANGE_INPUT) ||
(change & MPP_ENC_PREP_CFG_CHANGE_ROTATION)) {
if (dst->rotation == MPP_ENC_ROT_90 || dst->rotation == MPP_ENC_ROT_270) {
dst->width = src->height;
dst->height = src->width;
} else {
dst->width = src->width;
dst->height = src->height;
}
dst->hor_stride = src->hor_stride;
dst->ver_stride = src->ver_stride;
}
dst->change |= change;
// parameter checking
if (dst->rotation == MPP_ENC_ROT_90 || dst->rotation == MPP_ENC_ROT_270) {
if (dst->height > dst->hor_stride || dst->width > dst->ver_stride) {
mpp_err("invalid size w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height, dst->hor_stride, dst->ver_stride);
ret = MPP_ERR_VALUE;
}
} else {
if (dst->width > dst->hor_stride || dst->height > dst->ver_stride) {
mpp_err("invalid size w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height, dst->hor_stride, dst->ver_stride);
ret = MPP_ERR_VALUE;
}
}
if (MPP_FRAME_FMT_IS_FBC(dst->format) && (dst->mirroring || dst->rotation || dst->flip)) {
// rk3588 rkvenc support fbc with rotation
if (mpp_get_soc_type() != ROCKCHIP_SOC_RK3588) {
mpp_err("invalid cfg fbc data no support mirror %d, rotation %d, or flip %d",
dst->mirroring, dst->rotation, dst->flip);
ret = MPP_ERR_VALUE;
}
}
if (dst->range >= MPP_FRAME_RANGE_NB ||
dst->color >= MPP_FRAME_SPC_NB ||
dst->colorprim >= MPP_FRAME_PRI_NB ||
dst->colortrc >= MPP_FRAME_TRC_NB) {
mpp_err("invalid color range %d colorspace %d primaries %d transfer characteristic %d\n",
dst->range, dst->color, dst->colorprim, dst->colortrc);
ret = MPP_ERR_VALUE;
}
if (ret) {
mpp_err_f("failed to accept new prep config\n");
*dst = bak;
} else {
mpp_log("MPP_ENC_SET_PREP_CFG w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height,
dst->hor_stride, dst->ver_stride);
}
}
src->change = 0;
return ret;
}
static MPP_RET h264e_proc_h264_cfg(MppEncH264Cfg *dst, MppEncH264Cfg *src)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
// TODO: do codec check first
if (change) {
RK_S32 entropy_coding_mode;
RK_S32 cabac_init_idc;
RK_S32 transform8x8_mode;
RK_U32 disable_cabac;
if (change & MPP_ENC_H264_CFG_STREAM_TYPE)
dst->stream_type = src->stream_type;
if ((change & MPP_ENC_H264_CFG_CHANGE_PROFILE) &&
((dst->profile != src->profile) || (dst->level != src->level))) {
dst->profile = src->profile;
dst->level = src->level;
dst->change |= MPP_ENC_H264_CFG_CHANGE_PROFILE;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_POC_TYPE) &&
(dst->poc_type != src->poc_type)) {
dst->poc_type = src->poc_type;
dst->change |= MPP_ENC_H264_CFG_CHANGE_POC_TYPE;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB) &&
(dst->log2_max_poc_lsb != src->log2_max_poc_lsb)) {
dst->log2_max_poc_lsb = src->log2_max_poc_lsb;
dst->change |= MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM) &&
(dst->log2_max_frame_num != src->log2_max_frame_num)) {
dst->log2_max_frame_num = src->log2_max_frame_num;
dst->change |= MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM) &&
(dst->gaps_not_allowed != src->gaps_not_allowed)) {
dst->gaps_not_allowed = src->gaps_not_allowed;
dst->change |= MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_ENTROPY) &&
((dst->entropy_coding_mode_ex != src->entropy_coding_mode_ex) ||
(dst->cabac_init_idc_ex != src->cabac_init_idc_ex))) {
dst->entropy_coding_mode_ex = src->entropy_coding_mode_ex;
dst->cabac_init_idc_ex = src->cabac_init_idc_ex;
dst->change |= MPP_ENC_H264_CFG_CHANGE_ENTROPY;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_TRANS_8x8) &&
(dst->transform8x8_mode_ex != src->transform8x8_mode_ex)) {
dst->transform8x8_mode_ex = src->transform8x8_mode_ex;
dst->change |= MPP_ENC_H264_CFG_CHANGE_TRANS_8x8;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_CONST_INTRA) &&
(dst->constrained_intra_pred_mode != src->constrained_intra_pred_mode)) {
dst->constrained_intra_pred_mode = src->constrained_intra_pred_mode;
dst->change |= MPP_ENC_H264_CFG_CHANGE_CONST_INTRA;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_CHROMA_QP) &&
(dst->chroma_cb_qp_offset != src->chroma_cb_qp_offset ||
dst->chroma_cr_qp_offset != src->chroma_cr_qp_offset)) {
dst->chroma_cb_qp_offset = src->chroma_cb_qp_offset;
dst->chroma_cr_qp_offset = src->chroma_cr_qp_offset;
dst->change |= MPP_ENC_H264_CFG_CHANGE_CHROMA_QP;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_DEBLOCKING) &&
((dst->deblock_disable != src->deblock_disable) ||
(dst->deblock_offset_alpha != src->deblock_offset_alpha) ||
(dst->deblock_offset_beta != src->deblock_offset_beta))) {
dst->deblock_disable = src->deblock_disable;
dst->deblock_offset_alpha = src->deblock_offset_alpha;
dst->deblock_offset_beta = src->deblock_offset_beta;
dst->change |= MPP_ENC_H264_CFG_CHANGE_DEBLOCKING;
}
if (change & MPP_ENC_H264_CFG_CHANGE_LONG_TERM)
dst->use_longterm = src->use_longterm;
if ((change & MPP_ENC_H264_CFG_CHANGE_SCALING_LIST) &&
(dst->scaling_list_mode != src->scaling_list_mode)) {
dst->scaling_list_mode = src->scaling_list_mode;
dst->change |= MPP_ENC_H264_CFG_CHANGE_SCALING_LIST;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_INTRA_REFRESH) &&
((dst->intra_refresh_mode != src->intra_refresh_mode) ||
(dst->intra_refresh_arg != src->intra_refresh_arg))) {
dst->intra_refresh_mode = src->intra_refresh_mode;
dst->intra_refresh_arg = src->intra_refresh_arg;
dst->change |= MPP_ENC_H264_CFG_CHANGE_INTRA_REFRESH;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_MAX_LTR) &&
(dst->max_ltr_frames != src->max_ltr_frames)) {
dst->max_ltr_frames = src->max_ltr_frames;
dst->change |= MPP_ENC_H264_CFG_CHANGE_MAX_LTR;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_MAX_TID) &&
(dst->max_tid != src->max_tid)) {
dst->max_tid = src->max_tid;
dst->change |= MPP_ENC_H264_CFG_CHANGE_MAX_TID;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX) &&
(dst->prefix_mode != src->prefix_mode)) {
dst->prefix_mode = src->prefix_mode;
dst->change |= MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID) &&
(dst->base_layer_pid != src->base_layer_pid)) {
dst->base_layer_pid = src->base_layer_pid;
dst->change |= MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID;
}
if ((change & MPP_ENC_H264_CFG_CHANGE_CONSTRAINT_SET) &&
(dst->constraint_set != src->constraint_set)) {
dst->constraint_set = src->constraint_set;
dst->change |= MPP_ENC_H264_CFG_CHANGE_CONSTRAINT_SET;
}
if (change & MPP_ENC_H264_CFG_CHANGE_VUI) {
dst->vui = src->vui;
dst->change |= MPP_ENC_H264_CFG_CHANGE_VUI;
}
// check user h.264 config. If valid, set to HAL.
entropy_coding_mode = dst->entropy_coding_mode_ex;
cabac_init_idc = dst->cabac_init_idc_ex;
transform8x8_mode = dst->transform8x8_mode_ex;
disable_cabac = (H264_PROFILE_FREXT_CAVLC444 == dst->profile ||
H264_PROFILE_BASELINE == dst->profile ||
H264_PROFILE_EXTENDED == dst->profile);
if (disable_cabac && entropy_coding_mode) {
mpp_err("Warning: invalid cabac_en %d for profile %d, set to 0.\n",
entropy_coding_mode, dst->profile);
entropy_coding_mode = 0;
}
if (disable_cabac && cabac_init_idc >= 0) {
mpp_err("Warning: invalid cabac_init_idc %d for profile %d, set to -1.\n",
cabac_init_idc, dst->profile);
cabac_init_idc = -1;
}
if (dst->profile < H264_PROFILE_HIGH && transform8x8_mode) {
mpp_err("Warning: invalid transform8x8_mode %d for profile %d, set to 0.\n",
transform8x8_mode, dst->profile);
transform8x8_mode = 0;
}
dst->entropy_coding_mode = entropy_coding_mode;
dst->cabac_init_idc = cabac_init_idc;
dst->transform8x8_mode = transform8x8_mode;
}
src->change = 0;
return ret;
}
static MPP_RET h264e_proc_split_cfg(MppEncSliceSplit *dst, MppEncSliceSplit *src)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
if (change & MPP_ENC_SPLIT_CFG_CHANGE_MODE) {
dst->split_mode = src->split_mode;
dst->split_arg = src->split_arg;
}
if (change & MPP_ENC_SPLIT_CFG_CHANGE_ARG)
dst->split_arg = src->split_arg;
if (change & MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT)
dst->split_out = src->split_out;
/* cleanup arg and out when split mode is disabled */
if (!dst->split_mode) {
dst->split_arg = 0;
dst->split_out = 0;
}
dst->change |= change;
src->change = 0;
return ret;
}
static void h264e_check_cfg(MppEncCfgSet *cfg)
{
MppEncRcCfg *rc = &cfg->rc;
@ -612,7 +280,7 @@ static void h264e_check_cfg(MppEncCfgSet *cfg)
if (rc->drop_mode == MPP_ENC_RC_DROP_FRM_PSKIP &&
rc->drop_gap == 0 &&
h264->poc_type == 2) {
mpp_err("poc type 2 is ocnflict with successive non-reference pskip mode\n");
mpp_err("poc type 2 is conflict with successive non-reference pskip mode\n");
mpp_err("set drop gap to 1\n");
rc->drop_gap = 1;
}
@ -628,43 +296,11 @@ static MPP_RET h264e_proc_cfg(void *ctx, MpiCmd cmd, void *param)
switch (cmd) {
case MPP_ENC_SET_CFG : {
MppEncCfgSet *src = (MppEncCfgSet *)param;
if (src->prep.change)
ret |= h264e_proc_prep_cfg(&cfg->prep, &src->prep);
// TODO: rc cfg shouldn't be done here
if (cfg->rc.refresh_en) {
RK_U32 mb_rows;
if (MPP_ENC_RC_INTRA_REFRESH_ROW == cfg->rc.refresh_mode)
mb_rows = MPP_ALIGN(cfg->prep.height, 16) / 16;
else
mb_rows = MPP_ALIGN(cfg->prep.width, 16) / 16;
cfg->rc.refresh_length = (mb_rows + cfg->rc.refresh_num - 1) / cfg->rc.refresh_num;
if (cfg->rc.gop < cfg->rc.refresh_length)
cfg->rc.refresh_length = cfg->rc.gop;
}
if (src->h264.change)
ret |= h264e_proc_h264_cfg(&cfg->h264, &src->h264);
if (src->split.change)
ret |= h264e_proc_split_cfg(&cfg->split, &src->split);
} break;
case MPP_ENC_SET_PREP_CFG : {
ret = h264e_proc_prep_cfg(&cfg->prep, param);
} break;
case MPP_ENC_SET_CODEC_CFG : {
MppEncH264Cfg *h264 = (MppEncH264Cfg *)param;
ret = h264e_proc_h264_cfg(&cfg->h264, h264);
h264e_check_cfg(cfg);
} break;
case MPP_ENC_SET_SEI_CFG : {
} break;
case MPP_ENC_SET_SPLIT : {
ret = h264e_proc_split_cfg(&cfg->split, param);
} break;
default:
mpp_err("No correspond cmd found, and can not config!");
@ -672,8 +308,6 @@ static MPP_RET h264e_proc_cfg(void *ctx, MpiCmd cmd, void *param)
break;
}
h264e_check_cfg(cfg);
h264e_dbg_func("leave ret %d\n", ret);
return ret;
@ -710,13 +344,6 @@ static MPP_RET h264e_gen_hdr(void *ctx, MppPacket pkt)
p->pps_offset, p->pps_len);
}
/*
* After gen_hdr, the change of codec/prep must be cleared to 0,
* otherwise the change will affect the next idr frame
*/
p->cfg->h264.change = 0;
p->cfg->prep.change = 0;
h264e_dbg_func("leave\n");
return MPP_OK;
}
@ -921,7 +548,6 @@ static MPP_RET h264e_proc_hal(void *ctx, HalEncTask *task)
task->valid = 1;
task->syntax.data = &p->syntax[0];
task->syntax.number = p->syn_num;
h264->change = 0;
h264e_dbg_func("leave\n");

326
mpp/codec/enc/h265/h265e_api.c
View file

@ -64,21 +64,7 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
/* set defualt value of codec */
h265 = &p->cfg->h265;
h265->intra_qp = 26;
h265->max_qp = 51;
h265->min_qp = 10;
h265->max_i_qp = 51;
h265->min_i_qp = 10;
h265->qpmap_mode = 1;
h265->ip_qp_delta = 5;
h265->raw_dealt_qp = 4;
h265->max_delta_qp = 10;
h265->gop_delta_qp = 0;
h265->intra_refresh_mode = 0;
h265->intra_refresh_arg = 0;
h265->independ_slice_mode = 0;
h265->independ_slice_arg = 0;
h265->depend_slice_mode = 0;
h265->depend_slice_arg = 0;
h265->profile = MPP_PROFILE_HEVC_MAIN;
h265->level = 120;
@ -142,7 +128,6 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
* 720p
* YUV420SP
*/
prep->change = 0;
prep->width = 1280;
prep->height = 720;
prep->hor_stride = 1280;
@ -166,7 +151,6 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
* 30fps
* gop 60
*/
rc_cfg->change = 0;
rc_cfg->quality = MPP_ENC_RC_QUALITY_MEDIUM;
rc_cfg->bps_target = 2000 * 1000;
rc_cfg->bps_max = rc_cfg->bps_target * 5 / 4;
@ -232,13 +216,6 @@ static MPP_RET h265e_gen_hdr(void *ctx, MppPacket pkt)
if (NULL == p->dpb)
h265e_dpb_init(&p->dpb);
/*
* After gen_hdr, the change of codec/prep must be cleared to 0,
* otherwise the change will affect the next idr frame
*/
p->cfg->h265.change = 0;
p->cfg->prep.change = 0;
h265e_dbg_func("leave ctx %p\n", ctx);
return MPP_OK;
@ -425,272 +402,6 @@ static MPP_RET h265e_add_sei(MppPacket pkt, RK_S32 *length, RK_U8 uuid[16],
return MPP_OK;
}
static MPP_RET h265e_proc_prep_cfg(MppEncPrepCfg *dst, MppEncPrepCfg *src)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
RK_S32 mirroring;
RK_S32 rotation;
mpp_assert(change);
MppEncPrepCfg bak = *dst;
if (change & MPP_ENC_PREP_CFG_CHANGE_FORMAT)
dst->format = src->format;
if (change & MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE)
dst->range = src->range;
if (change & MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE)
dst->color = src->color;
if (change & MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME)
dst->colorprim = src->colorprim;
if (change & MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC)
dst->colortrc = src->colortrc;
if (change & MPP_ENC_PREP_CFG_CHANGE_ROTATION)
dst->rotation_ext = src->rotation_ext;
if (change & MPP_ENC_PREP_CFG_CHANGE_MIRRORING)
dst->mirroring_ext = src->mirroring_ext;
if (change & MPP_ENC_PREP_CFG_CHANGE_FLIP)
dst->flip = src->flip;
if (change & MPP_ENC_PREP_CFG_CHANGE_DENOISE)
dst->denoise = src->denoise;
if (change & MPP_ENC_PREP_CFG_CHANGE_SHARPEN)
dst->sharpen = src->sharpen;
// parameter checking
if (dst->rotation_ext >= MPP_ENC_ROT_BUTT || dst->rotation_ext < 0 ||
dst->mirroring_ext < 0 || dst->flip < 0) {
mpp_err("invalid trans: rotation %d, mirroring %d\n", dst->rotation_ext, dst->mirroring_ext);
ret = MPP_ERR_VALUE;
}
/* For unifying the encoder's params used by CFG_SET and CFG_GET command,
* there is distinction between user's set and set in hal.
* User can externally set rotation_ext, mirroring_ext and flip,
* which should be transformed to mirroring and rotation in hal.
*/
mirroring = dst->mirroring_ext;
rotation = dst->rotation_ext;
if (dst->flip) {
mirroring = !mirroring;
rotation += MPP_ENC_ROT_180;
rotation &= MPP_ENC_ROT_270;
}
dst->mirroring = mirroring;
dst->rotation = rotation;
if ((change & MPP_ENC_PREP_CFG_CHANGE_INPUT) ||
(change & MPP_ENC_PREP_CFG_CHANGE_ROTATION)) {
if (dst->rotation == MPP_ENC_ROT_90 || dst->rotation == MPP_ENC_ROT_270) {
dst->width = src->height;
dst->height = src->width;
} else {
dst->width = src->width;
dst->height = src->height;
}
dst->hor_stride = src->hor_stride;
dst->ver_stride = src->ver_stride;
}
dst->change |= change;
// parameter checking
if (dst->rotation == MPP_ENC_ROT_90 || dst->rotation == MPP_ENC_ROT_270) {
if (dst->height > dst->hor_stride || dst->width > dst->ver_stride) {
mpp_err("invalid size w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height, dst->hor_stride, dst->ver_stride);
ret = MPP_ERR_VALUE;
}
} else {
if (dst->width > dst->hor_stride || dst->height > dst->ver_stride) {
mpp_err("invalid size w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height, dst->hor_stride, dst->ver_stride);
ret = MPP_ERR_VALUE;
}
}
if (MPP_FRAME_FMT_IS_FBC(dst->format) && (dst->mirroring || dst->rotation || dst->flip)) {
// rk3588 rkvenc support fbc with rotation
if (mpp_get_soc_type() != ROCKCHIP_SOC_RK3588) {
mpp_err("invalid cfg fbc data no support mirror %d, rotation %d, or flip %d",
dst->mirroring, dst->rotation, dst->flip);
ret = MPP_ERR_VALUE;
}
}
if (dst->range >= MPP_FRAME_RANGE_NB ||
dst->color >= MPP_FRAME_SPC_NB ||
dst->colorprim >= MPP_FRAME_PRI_NB ||
dst->colortrc >= MPP_FRAME_TRC_NB) {
mpp_err("invalid color range %d colorspace %d primaries %d transfer characteristic %d\n",
dst->range, dst->color, dst->colorprim, dst->colortrc);
ret = MPP_ERR_VALUE;
}
if (ret) {
mpp_err_f("failed to accept new prep config\n");
*dst = bak;
} else {
mpp_log_f("MPP_ENC_SET_PREP_CFG w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height,
dst->hor_stride, dst->ver_stride);
}
return ret;
}
static MPP_RET h265e_proc_h265_cfg(MppEncH265Cfg *dst, MppEncH265Cfg *src)
{
RK_U32 change = src->change;
// TODO: do codec check first
if (change & MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE) {
RK_S32 profile = src->profile;
if (MPP_PROFILE_HEVC_MAIN == profile ||
MPP_PROFILE_HEVC_MAIN_STILL_PICTURE == profile) {
dst->profile = profile;
// TODO: proc main still profile
} else {
mpp_err("invalid profile_idc %d, keep %d", profile, dst->profile);
}
dst->level = src->level;
dst->tier = (src->level >= 120) ? src->tier : 0;
}
if (change & MPP_ENC_H265_CFG_CU_CHANGE) {
memcpy(&dst->cu_cfg, &src->cu_cfg, sizeof(src->cu_cfg));
}
if (change & MPP_ENC_H265_CFG_DBLK_CHANGE) {
memcpy(&dst->dblk_cfg, &src->dblk_cfg, sizeof(src->dblk_cfg));
}
if (change & MPP_ENC_H265_CFG_SAO_CHANGE) {
memcpy(&dst->sao_cfg, &src->sao_cfg, sizeof(src->sao_cfg));
}
if (change & MPP_ENC_H265_CFG_TRANS_CHANGE) {
if (src->trans_cfg.cb_qp_offset != src->trans_cfg.cr_qp_offset) {
mpp_log("cr_qp_offset %d MUST equal to cb_qp_offset %d. FORCE to same value\n",
src->trans_cfg.cb_qp_offset, src->trans_cfg.cr_qp_offset);
src->trans_cfg.cr_qp_offset = src->trans_cfg.cb_qp_offset;
}
if (src->trans_cfg.diff_cu_qp_delta_depth > 2 || src->trans_cfg.diff_cu_qp_delta_depth < 0) {
mpp_log("diff_cu_qp_delta_depth must be in [0, 2]\n");
src->trans_cfg.diff_cu_qp_delta_depth = 0;
}
memcpy(&dst->trans_cfg, &src->trans_cfg, sizeof(src->trans_cfg));
}
if (change & MPP_ENC_H265_CFG_SLICE_CHANGE) {
memcpy(&dst->slice_cfg, &src->slice_cfg, sizeof(src->slice_cfg));
}
if (change & MPP_ENC_H265_CFG_ENTROPY_CHANGE) {
memcpy(&dst->entropy_cfg, &src->entropy_cfg, sizeof(src->entropy_cfg));
}
if (change & MPP_ENC_H265_CFG_MERGE_CHANGE) {
memcpy(&dst->merge_cfg, &src->merge_cfg, sizeof(src->merge_cfg));
}
if (change & MPP_ENC_H265_CFG_CHANGE_VUI) {
memcpy(&dst->vui, &src->vui, sizeof(src->vui));
}
if (change & MPP_ENC_H265_CFG_SAO_CHANGE) {
memcpy(&dst->sao_cfg, &src->sao_cfg, sizeof(src->sao_cfg));
}
if (change & MPP_ENC_H265_CFG_TILE_CHANGE)
dst->auto_tile = src->auto_tile;
if (change & MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE)
dst->lpf_acs_sli_en = src->lpf_acs_sli_en;
if (change & MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE)
dst->lpf_acs_tile_disable = src->lpf_acs_tile_disable;
if ((change & MPP_ENC_H265_CFG_CHANGE_CONST_INTRA) &&
(dst->const_intra_pred != src->const_intra_pred)) {
RockchipSocType soc_type = mpp_get_soc_type();
if (soc_type != ROCKCHIP_SOC_RK3576 && src->const_intra_pred == 1) {
dst->const_intra_pred = 0;
mpp_log("warning: Only rk3576's HEVC encoder support constraint intra prediction flag = 1.");
} else
dst->const_intra_pred = src->const_intra_pred;
dst->change |= MPP_ENC_H265_CFG_CHANGE_CONST_INTRA;
}
if ((change & MPP_ENC_H265_CFG_CHANGE_MAX_LTR) &&
(dst->max_ltr_frames != src->max_ltr_frames)) {
dst->max_ltr_frames = src->max_ltr_frames;
dst->change |= MPP_ENC_H265_CFG_CHANGE_MAX_LTR;
}
if ((change & MPP_ENC_H265_CFG_CHANGE_MAX_TID) &&
(dst->max_tid != src->max_tid)) {
dst->max_tid = src->max_tid;
dst->change |= MPP_ENC_H265_CFG_CHANGE_MAX_TID;
}
if ((change & MPP_ENC_H265_CFG_CHANGE_BASE_LAYER_PID) &&
(dst->base_layer_pid != src->base_layer_pid)) {
dst->base_layer_pid = src->base_layer_pid;
dst->change |= MPP_ENC_H265_CFG_CHANGE_BASE_LAYER_PID;
}
/*
* NOTE: use OR here for avoiding overwrite on multiple config
* When next encoding is trigger the change flag will be clear
*/
dst->change |= change;
return MPP_OK;
}
static MPP_RET h265e_proc_split_cfg(MppEncSliceSplit *dst, MppEncSliceSplit *src)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
if (change & MPP_ENC_SPLIT_CFG_CHANGE_MODE) {
dst->split_mode = src->split_mode;
dst->split_arg = src->split_arg;
}
if (change & MPP_ENC_SPLIT_CFG_CHANGE_ARG)
dst->split_arg = src->split_arg;
if (change & MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT)
dst->split_out = src->split_out;
/* cleanup arg and out when split mode is disabled */
if (!dst->split_mode) {
dst->split_arg = 0;
dst->split_out = 0;
}
dst->change |= change;
src->change = 0;
return ret;
}
static MPP_RET h265e_proc_cfg(void *ctx, MpiCmd cmd, void *param)
{
H265eCtx *p = (H265eCtx *)ctx;
@ -701,49 +412,12 @@ static MPP_RET h265e_proc_cfg(void *ctx, MpiCmd cmd, void *param)
switch (cmd) {
case MPP_ENC_SET_CFG : {
MppEncCfgSet *src = (MppEncCfgSet *)param;
if (src->prep.change) {
ret |= h265e_proc_prep_cfg(&cfg->prep, &src->prep);
src->prep.change = 0;
}
if (cfg->rc.refresh_en) {
RK_U32 mb_rows;
if (MPP_ENC_RC_INTRA_REFRESH_ROW == cfg->rc.refresh_mode)
mb_rows = MPP_ALIGN(cfg->prep.height, 64) / 64;
else
mb_rows = MPP_ALIGN(cfg->prep.width, 64) / 64;
cfg->rc.refresh_length = (mb_rows + cfg->rc.refresh_num - 1) / cfg->rc.refresh_num;
if (cfg->rc.gop < cfg->rc.refresh_length)
cfg->rc.refresh_length = cfg->rc.gop;
}
if (src->h265.change) {
ret |= h265e_proc_h265_cfg(&cfg->h265, &src->h265);
src->h265.change = 0;
}
if (src->split.change) {
ret |= h265e_proc_split_cfg(&cfg->split, &src->split);
src->split.change = 0;
}
} break;
case MPP_ENC_GET_EXTRA_INFO: {
MppPacket pkt_out = (MppPacket )param;
h265e_set_extra_info(p);
h265e_get_extra_info(p, pkt_out);
} break;
case MPP_ENC_SET_PREP_CFG : {
ret = h265e_proc_prep_cfg(&cfg->prep, param);
} break;
case MPP_ENC_SET_CODEC_CFG: {
MppEncH265Cfg *h265 = (MppEncH265Cfg *)param;
ret = h265e_proc_h265_cfg(&cfg->h265, h265);
} break;
case MPP_ENC_SET_SEI_CFG: {
} break;
case MPP_ENC_SET_SPLIT : {

2
mpp/codec/enc/h265/h265e_ps.c
View file

@ -310,7 +310,7 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps)
sps->m_pcmBitDepthChroma = 8;
sps->m_bPCMFilterDisableFlag = 0;
sps->m_scalingListEnabledFlag = codec->trans_cfg.defalut_ScalingList_enable == 0 ? 0 : 1;
sps->m_scalingListEnabledFlag = codec->trans_cfg.scaling_list_mode == 0 ? 0 : 1;
sps->m_bitsForPOC = 16;
sps->m_numLongTermRefPicSPS = 0;

334
mpp/codec/enc/jpeg/jpege_api_v2.c
View file

@ -36,32 +36,9 @@ typedef struct {
JpegeSyntax syntax;
} JpegeCtx;
#define QUANTIZE_TABLE_SIZE 64
/*
* from RFC435 spec.
*/
static const RK_U8 jpege_luma_quantizer[QUANTIZE_TABLE_SIZE] = {
16, 11, 10, 16, 24, 40, 51, 61,
12, 12, 14, 19, 26, 58, 60, 55,
14, 13, 16, 24, 40, 57, 69, 56,
14, 17, 22, 29, 51, 87, 80, 62,
18, 22, 37, 56, 68, 109, 103, 77,
24, 35, 55, 64, 81, 104, 113, 92,
49, 64, 78, 87, 103, 121, 120, 101,
72, 92, 95, 98, 112, 100, 103, 99
};
static const RK_U8 jpege_chroma_quantizer[QUANTIZE_TABLE_SIZE] = {
17, 18, 24, 47, 99, 99, 99, 99,
18, 21, 26, 66, 99, 99, 99, 99,
24, 26, 56, 99, 99, 99, 99, 99,
47, 66, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99
};
RK_U32 jpege_debug = 0;
@ -87,9 +64,11 @@ static MPP_RET jpege_init_v2(void *ctx, EncImplCfg *cfg)
rc->fps_out_flex = 0;
rc->fps_out_num = 30;
rc->fps_out_denom = 1;
rc->rc_mode = MPP_ENC_RC_MODE_VBR;
/* init default quant */
jpeg_cfg->quant = 10;
rc->rc_mode = MPP_ENC_RC_MODE_FIXQP;
/* set quant to invalid value */
jpeg_cfg->quant = -1;
jpeg_cfg->quant_ext = -1;
}
jpege_dbg_func("leave ctx %p\n", ctx);
@ -98,315 +77,20 @@ static MPP_RET jpege_init_v2(void *ctx, EncImplCfg *cfg)
static MPP_RET jpege_deinit_v2(void *ctx)
{
JpegeCtx *p = (JpegeCtx *)ctx;
MppEncJpegCfg *jpeg_cfg = &p->cfg->jpeg;
jpege_dbg_func("enter ctx %p\n", ctx);
MPP_FREE(jpeg_cfg->qtable_y);
MPP_FREE(jpeg_cfg->qtable_u);
MPP_FREE(jpeg_cfg->qtable_v);
jpege_dbg_func("leave ctx %p\n", ctx);
return MPP_OK;
}
static MPP_RET jpege_proc_prep_cfg(MppEncPrepCfg *dst, MppEncPrepCfg *src)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
mpp_assert(change);
if (change) {
MppEncPrepCfg bak = *dst;
RK_S32 mirroring;
RK_S32 rotation;
if (change & MPP_ENC_PREP_CFG_CHANGE_FORMAT) {
dst->format = src->format;
dst->format_out = src->format_out;
dst->fix_chroma_en = src->fix_chroma_en;
dst->fix_chroma_u = src->fix_chroma_u;
dst->fix_chroma_v = src->fix_chroma_v;
dst->chroma_ds_mode = src->chroma_ds_mode;
}
if (change & MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE) {
dst->range = src->range;
dst->range_out = src->range_out;
}
if (change & MPP_ENC_PREP_CFG_CHANGE_ROTATION)
dst->rotation_ext = src->rotation_ext;
if (change & MPP_ENC_PREP_CFG_CHANGE_MIRRORING)
dst->mirroring_ext = src->mirroring_ext;
if (change & MPP_ENC_PREP_CFG_CHANGE_FLIP)
dst->flip = src->flip;
// parameter checking
if (dst->rotation_ext >= MPP_ENC_ROT_BUTT || dst->rotation_ext < 0 ||
dst->mirroring_ext < 0 || dst->flip < 0) {
mpp_err("invalid trans: rotation %d, mirroring %d\n", dst->rotation_ext, dst->mirroring_ext);
ret = MPP_ERR_VALUE;
}
rotation = dst->rotation_ext;
mirroring = dst->mirroring_ext;
if (dst->flip) {
mirroring = !mirroring;
rotation += MPP_ENC_ROT_180;
rotation &= MPP_ENC_ROT_270;
}
dst->mirroring = mirroring;
dst->rotation = rotation;
/* jpeg encoder do not have denoise/sharpen feature */
if ((change & MPP_ENC_PREP_CFG_CHANGE_INPUT) ||
(change & MPP_ENC_PREP_CFG_CHANGE_ROTATION)) {
if (dst->rotation == MPP_ENC_ROT_90 || dst->rotation == MPP_ENC_ROT_270) {
dst->width = src->height;
dst->height = src->width;
} else {
dst->width = src->width;
dst->height = src->height;
}
dst->hor_stride = src->hor_stride;
dst->ver_stride = src->ver_stride;
}
if (dst->width < 16 || dst->width > 8192) {
mpp_err_f("invalid width %d is not in range [16..8192]\n", dst->width);
ret = MPP_NOK;
}
if (dst->height < 16 || dst->height > 8192) {
mpp_err_f("invalid height %d is not in range [16..8192]\n", dst->height);
ret = MPP_NOK;
}
dst->change |= change;
// parameter checking
if (dst->rotation == MPP_ENC_ROT_90 || dst->rotation == MPP_ENC_ROT_270) {
if (dst->height > dst->hor_stride || dst->width > dst->ver_stride) {
mpp_err("invalid size w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height, dst->hor_stride, dst->ver_stride);
ret = MPP_ERR_VALUE;
}
} else {
if (dst->width > dst->hor_stride || dst->height > dst->ver_stride) {
mpp_err("invalid size w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height, dst->hor_stride, dst->ver_stride);
ret = MPP_ERR_VALUE;
}
}
if (ret) {
mpp_err_f("failed to accept new prep config\n");
*dst = bak;
} else {
jpege_dbg_ctrl("MPP_ENC_SET_PREP_CFG w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height,
dst->hor_stride, dst->ver_stride);
}
}
return ret;
}
/* gen quantizer table by q_factor according to RFC2435 spec. */
static MPP_RET jpege_gen_qt_by_qfactor(MppEncJpegCfg *cfg, RK_S32 *factor)
{
MPP_RET ret = MPP_OK;
RK_U32 q, qfactor = *factor;
RK_U32 i;
RK_U8 *qtable_y = NULL;
RK_U8 *qtable_c = NULL;
if (!cfg->qtable_y)
cfg->qtable_y = mpp_malloc(RK_U8, QUANTIZE_TABLE_SIZE);
if (!cfg->qtable_u)
cfg->qtable_u = mpp_malloc(RK_U8, QUANTIZE_TABLE_SIZE);
if (NULL == cfg->qtable_y || NULL == cfg->qtable_u) {
mpp_err_f("qtable is null, malloc err");
return MPP_ERR_MALLOC;
}
qtable_y = cfg->qtable_y;
qtable_c = cfg->qtable_u;
if (qfactor < 50)
q = 5000 / qfactor;
else
q = 200 - (qfactor << 1);
for (i = 0; i < QUANTIZE_TABLE_SIZE; i++) {
RK_S16 lq = (jpege_luma_quantizer[i] * q + 50) / 100;
RK_S16 cq = (jpege_chroma_quantizer[i] * q + 50) / 100;
/* Limit the quantizers to 1 <= q <= 255 */
qtable_y[i] = MPP_CLIP3(1, 255, lq);
qtable_c[i] = MPP_CLIP3(1, 255, cq);
}
return ret;
}
static MPP_RET jpege_proc_jpeg_cfg(MppEncJpegCfg *dst, MppEncJpegCfg *src, MppEncRcCfg *rc)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
if (change) {
MppEncJpegCfg bak = *dst;
if (change & MPP_ENC_JPEG_CFG_CHANGE_QP) {
dst->quant = src->quant;
if (dst->quant < 0 || dst->quant > 10) {
mpp_err_f("invalid quality level %d is not in range [0..10] set to default 8\n");
dst->quant = 8;
}
if (rc->rc_mode != MPP_ENC_RC_MODE_FIXQP) {
mpp_log("setup quant %d change mode %s fixqp", dst->quant,
strof_rc_mode(rc->rc_mode));
rc->rc_mode = MPP_ENC_RC_MODE_FIXQP;
}
} else if (change & MPP_ENC_JPEG_CFG_CHANGE_QFACTOR) {
if (src->q_factor < 1 || src->q_factor > 99) {
mpp_err_f("q_factor out of range, default set 80\n");
src->q_factor = 80;
}
if (dst->q_factor != src->q_factor)
ret = jpege_gen_qt_by_qfactor(dst, &src->q_factor);
dst->q_factor = src->q_factor;
if (src->qf_min < 1 || src->qf_min > 99) {
mpp_err_f("qf_min out of range, default set 1\n");
src->qf_min = 1;
}
dst->qf_min = src->qf_min;
if (src->qf_max < 1 || src->qf_max > 99) {
mpp_err_f("qf_max out of range, default set 99\n");
src->qf_max = 99;
}
dst->qf_max = src->qf_max;
jpege_dbg_input("q_factor %d, qf_min %d, qf_max %d\n",
dst->q_factor, dst->qf_min, dst->qf_max);
} else if (change & MPP_ENC_JPEG_CFG_CHANGE_QTABLE) {
if (src->qtable_y && src->qtable_u && src->qtable_v) {
if (NULL == dst->qtable_y)
dst->qtable_y = mpp_malloc(RK_U8, QUANTIZE_TABLE_SIZE);
if (NULL == dst->qtable_u)
dst->qtable_u = mpp_malloc(RK_U8, QUANTIZE_TABLE_SIZE);
if (NULL == dst->qtable_y || NULL == dst->qtable_u) {
mpp_err_f("qtable is null, malloc err\n");
return MPP_ERR_MALLOC;
}
/* check table value */
if (src->qtable_u != src->qtable_v) {
RK_U32 i;
for (i = 0; i < QUANTIZE_TABLE_SIZE; i++) {
if (src->qtable_u[i] != src->qtable_v[i]) {
RK_U32 j;
jpege_dbg_input("qtable_u and qtable_v are different, use qtable_u\n");
for (j = 0; j < QUANTIZE_TABLE_SIZE; j++)
jpege_dbg_input("qtable_u[%d] %d qtable_v[%d] %d\n",
j, src->qtable_u[j], j, src->qtable_v[j]);
break;
}
}
}
/* default use one chroma qtable, select qtable_u */
memcpy(dst->qtable_y, src->qtable_y, QUANTIZE_TABLE_SIZE);
memcpy(dst->qtable_u, src->qtable_u, QUANTIZE_TABLE_SIZE);
if (rc->rc_mode != MPP_ENC_RC_MODE_FIXQP) {
mpp_log("setup qtable will change mode %s fixqp",
strof_rc_mode(rc->rc_mode));
rc->rc_mode = MPP_ENC_RC_MODE_FIXQP;
}
} else {
mpp_err_f("invalid qtable y %p u %p v %p\n",
src->qtable_y, src->qtable_u, src->qtable_v);
ret = MPP_ERR_NULL_PTR;
}
}
if (ret) {
mpp_err_f("failed to accept new rc config\n");
*dst = bak;
} else {
jpege_dbg_ctrl("MPP_ENC_SET_CODEC_CFG change 0x%x jpeg quant %d q_factor %d\n",
change, dst->quant, dst->q_factor);
dst->change = src->change;
}
dst->change = src->change;
}
return ret;
}
static MPP_RET jpege_proc_split_cfg(MppEncSliceSplit *dst, MppEncSliceSplit *src)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
if (change & MPP_ENC_SPLIT_CFG_CHANGE_MODE) {
dst->split_mode = src->split_mode;
dst->split_arg = src->split_arg;
}
if (change & MPP_ENC_SPLIT_CFG_CHANGE_ARG)
dst->split_arg = src->split_arg;
dst->change |= change;
return ret;
}
static MPP_RET jpege_proc_cfg(void *ctx, MpiCmd cmd, void *param)
{
JpegeCtx *p = (JpegeCtx *)ctx;
MppEncCfgSet *cfg = p->cfg;
MPP_RET ret = MPP_OK;
jpege_dbg_func("enter ctx %p cmd %x param %p\n", ctx, cmd, param);
switch (cmd) {
case MPP_ENC_SET_CFG : {
MppEncCfgSet *src = (MppEncCfgSet *)param;
if (src->prep.change) {
ret |= jpege_proc_prep_cfg(&cfg->prep, &src->prep);
src->prep.change = 0;
}
if (src->jpeg.change) {
ret |= jpege_proc_jpeg_cfg(&cfg->jpeg, &src->jpeg, &cfg->rc);
src->jpeg.change = 0;
}
if (src->split.change) {
ret |= jpege_proc_split_cfg(&cfg->split, &src->split);
src->split.change = 0;
}
} break;
case MPP_ENC_SET_PREP_CFG : {
ret = jpege_proc_prep_cfg(&cfg->prep, param);
} break;
case MPP_ENC_SET_CODEC_CFG : {
MppEncJpegCfg *jpeg = (MppEncJpegCfg *)param;
ret = jpege_proc_jpeg_cfg(&cfg->jpeg, jpeg, &cfg->rc);
} break;
case MPP_ENC_SET_CFG :
case MPP_ENC_SET_IDR_FRAME :
case MPP_ENC_SET_OSD_PLT_CFG :
case MPP_ENC_SET_OSD_DATA_CFG :
@ -556,12 +240,14 @@ static MPP_RET jpege_proc_hal(void *ctx, HalEncTask *task)
syntax->mirroring = prep->mirroring;
syntax->offset_x = mpp_frame_get_offset_x(frame);
syntax->offset_y = mpp_frame_get_offset_y(frame);
syntax->quality = jpeg->quant;
syntax->q_mode = jpeg->q_mode;
syntax->quant = jpeg->quant;
syntax->q_factor = jpeg->q_factor;
syntax->qf_min = jpeg->qf_min;
syntax->qf_max = jpeg->qf_max;
syntax->qtable_y = jpeg->qtable_y;
syntax->qtable_c = jpeg->qtable_u;
syntax->qtable_u = jpeg->qtable_u;
syntax->qtable_v = jpeg->qtable_v;
syntax->part_rows = 0;
syntax->restart_ri = 0;
syntax->low_delay = 0;

150
mpp/codec/enc/vp8/vp8e_api_v2.c
View file

@ -69,7 +69,6 @@ static MPP_RET vp8e_init(void *ctx, EncImplCfg *ctrl_cfg)
* 720p
* YUV420SP
*/
prep->change = 0;
prep->width = 1280;
prep->height = 720;
prep->hor_stride = 1280;
@ -88,7 +87,6 @@ static MPP_RET vp8e_init(void *ctx, EncImplCfg *ctrl_cfg)
* 30fps
* gop 60
*/
rc_cfg->change = 0;
rc_cfg->rc_mode = MPP_ENC_RC_MODE_CBR;
rc_cfg->quality = MPP_ENC_RC_QUALITY_MEDIUM;
rc_cfg->bps_target = 2000 * 1000;
@ -156,161 +154,13 @@ static MPP_RET vp8e_proc_dpb(void *ctx, HalEncTask *task)
return MPP_OK;
}
static MPP_RET vp8e_proc_prep_cfg(MppEncPrepCfg *dst, MppEncPrepCfg *src)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
mpp_assert(change);
if (change) {
RK_S32 mirroring;
RK_S32 rotation;
if (change & MPP_ENC_PREP_CFG_CHANGE_FORMAT) {
if ((src->format < MPP_FRAME_FMT_RGB &&
src->format >= MPP_FMT_YUV_BUTT) ||
src->format >= MPP_FMT_RGB_BUTT) {
mpp_err("invalid format %d\n", src->format);
ret = MPP_NOK;
}
dst->format = src->format;
}
if (change & MPP_ENC_PREP_CFG_CHANGE_ROTATION)
dst->rotation_ext = src->rotation_ext;
if (change & MPP_ENC_PREP_CFG_CHANGE_MIRRORING)
dst->mirroring_ext = src->mirroring_ext;
if (change & MPP_ENC_PREP_CFG_CHANGE_FLIP)
dst->flip = src->flip;
// parameter checking
if (dst->rotation_ext >= MPP_ENC_ROT_BUTT || dst->rotation_ext < 0 ||
dst->mirroring_ext < 0 || dst->flip < 0) {
mpp_err("invalid trans: rotation %d, mirroring %d\n", dst->rotation_ext, dst->mirroring_ext);
ret = MPP_ERR_VALUE;
}
rotation = dst->rotation_ext;
mirroring = dst->mirroring_ext;
if (dst->flip) {
mirroring = !mirroring;
rotation += MPP_ENC_ROT_180;
rotation &= MPP_ENC_ROT_270;
}
dst->mirroring = mirroring;
dst->rotation = rotation;
/* vp8 encoder do not have denoise/sharpen feature */
if (change & MPP_ENC_PREP_CFG_CHANGE_INPUT ||
(change & MPP_ENC_PREP_CFG_CHANGE_ROTATION)) {
if ((src->width < 0 || src->width > 1920) ||
(src->height < 0 || src->height > 3840) ||
(src->hor_stride < 0 || src->hor_stride > 7680) ||
(src->ver_stride < 0 || src->ver_stride > 3840)) {
mpp_err("invalid input w:h [%d:%d] [%d:%d]\n",
src->width, src->height,
src->hor_stride, src->ver_stride);
ret = MPP_NOK;
}
if (dst->rotation == MPP_ENC_ROT_90 || dst->rotation == MPP_ENC_ROT_270) {
dst->width = src->height;
dst->height = src->width;
} else {
dst->width = src->width;
dst->height = src->height;
}
dst->ver_stride = src->ver_stride;
dst->hor_stride = src->hor_stride;
}
dst->change |= src->change;
if (dst->rotation == MPP_ENC_ROT_90 || dst->rotation == MPP_ENC_ROT_270) {
if (dst->height > dst->hor_stride || dst->width > dst->ver_stride) {
mpp_err("invalid size w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height, dst->hor_stride, dst->ver_stride);
ret = MPP_ERR_VALUE;
}
} else {
if (dst->width > dst->hor_stride || dst->height > dst->ver_stride) {
mpp_err("invalid size w:h [%d:%d] stride [%d:%d]\n",
dst->width, dst->height, dst->hor_stride, dst->ver_stride);
ret = MPP_ERR_VALUE;
}
}
vp8e_dbg_cfg("width %d height %d hor_stride %d ver_srtride %d format 0x%x\n",
dst->width, dst->height, dst->hor_stride, dst->ver_stride, dst->format);
}
return ret;
}
static MPP_RET vp8e_proc_split_cfg(MppEncSliceSplit *dst, MppEncSliceSplit *src)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
if (change & MPP_ENC_SPLIT_CFG_CHANGE_MODE) {
dst->split_mode = src->split_mode;
dst->split_arg = src->split_arg;
}
if (change & MPP_ENC_SPLIT_CFG_CHANGE_ARG)
dst->split_arg = src->split_arg;
dst->change |= change;
return ret;
}
static MPP_RET vp8e_proc_vp8_cfg(MppEncVp8Cfg *dst, MppEncVp8Cfg *src)
{
RK_U32 change = src->change;
if (change & MPP_ENC_VP8_CFG_CHANGE_QP) {
dst->qp_init = src->qp_init;
dst->qp_max = src->qp_max;
dst->qp_min = src->qp_min;
dst->qp_max_i = src->qp_max_i;
dst->qp_min_i = src->qp_min_i;
}
if (change & MPP_ENC_VP8_CFG_CHANGE_DIS_IVF) {
dst->disable_ivf = src->disable_ivf;
}
vp8e_dbg_cfg("rc cfg qp_init %d qp_max %d qp_min %d qp_max_i %d qp_min_i %d, disable_ivf %d\n",
dst->qp_init, dst->qp_max, dst->qp_min, dst->qp_max_i, dst->qp_min_i, dst->disable_ivf);
dst->change |= src->change;
return MPP_OK;
}
static MPP_RET vp8e_proc_cfg(void *ctx, MpiCmd cmd, void *param)
{
MPP_RET ret = MPP_OK;
Vp8eCtx *p = (Vp8eCtx *)ctx;
MppEncCfgSet *cfg = p->cfg;
MppEncCfgSet *src = (MppEncCfgSet *)param;
vp8e_dbg_fun("enter ctx %p cmd %x param %p\n", ctx, cmd, param);
switch (cmd) {
case MPP_ENC_SET_CFG : {
if (src->prep.change) {
ret |= vp8e_proc_prep_cfg(&cfg->prep, &src->prep);
src->prep.change = 0;
}
if (src->vp8.change) {
ret |= vp8e_proc_vp8_cfg(&cfg->vp8, &src->vp8);
src->vp8.change = 0;
}
if (src->split.change) {
ret |= vp8e_proc_split_cfg(&cfg->split, &src->split);
src->split.change = 0;
}
} break;
default: {
mpp_err("No correspond cmd found, and can not config!");

8
mpp/codec/inc/mpp_enc_impl.h
View file

@ -143,8 +143,12 @@ typedef struct MppEncImpl_t {
RK_U32 support_hw_deflicker;
EncRcTaskInfo rc_info_prev;
/* Encoder configure set */
MppEncCfgSet cfg;
/* encoder config object for external setup */
MppEncCfg set_obj;
MppEncCfgSet *set;
/* encoder config object for internal usage */
MppEncCfg cfg_obj;
MppEncCfgSet *cfg;
} MppEncImpl;
#ifdef __cplusplus

2
mpp/codec/mpp_enc_debug.h
View file

@ -21,6 +21,7 @@
#define MPP_ENC_DBG_FUNCTION (0x00000001)
#define MPP_ENC_DBG_CONTROL (0x00000002)
#define MPP_ENC_DBG_CFG (0x00000004)
#define MPP_ENC_DBG_STATUS (0x00000010)
#define MPP_ENC_DBG_DETAIL (0x00000020)
#define MPP_ENC_DBG_RESET (0x00000040)
@ -35,6 +36,7 @@
#define enc_dbg_func(fmt, ...) mpp_enc_dbg_f(MPP_ENC_DBG_FUNCTION, fmt, ## __VA_ARGS__)
#define enc_dbg_ctrl(fmt, ...) mpp_enc_dbg_f(MPP_ENC_DBG_CONTROL, fmt, ## __VA_ARGS__)
#define enc_dbg_cfg(fmt, ...) mpp_enc_dbg(MPP_ENC_DBG_CFG, fmt, ## __VA_ARGS__)
#define enc_dbg_status(fmt, ...) mpp_enc_dbg_f(MPP_ENC_DBG_STATUS, fmt, ## __VA_ARGS__)
#define enc_dbg_detail(fmt, ...) mpp_enc_dbg_f(MPP_ENC_DBG_DETAIL, fmt, ## __VA_ARGS__)
#define enc_dbg_notify(fmt, ...) mpp_enc_dbg_f(MPP_ENC_DBG_NOTIFY, fmt, ## __VA_ARGS__)

1516
mpp/codec/mpp_enc_impl.c
View file

File diff suppressed because it is too large Load diff

106
mpp/codec/mpp_enc_v2.c
View file

@ -19,8 +19,27 @@
#include "mpp_enc_impl.h"
#include "mpp_enc_cb_param.h"
#include "kmpp_obj.h"
RK_U32 mpp_enc_debug = 0;
static void copy_enc_cfg(KmppObj dst, KmppObj src)
{
MppEncCfgSet *_dst = (MppEncCfgSet *)kmpp_obj_to_entry(dst);
MppEncCfgSet *_src = (MppEncCfgSet *)kmpp_obj_to_entry(src);
memcpy(_dst, _src, sizeof(*_dst));
/* cleanup output change flag to avoid extra change flag bit when user resend the cfg */
{
void *p = kmpp_obj_to_flags(dst);
rk_s32 size = kmpp_obj_to_flags_size(dst);
if (p && size)
memset(p, 0, size);
}
}
MPP_RET mpp_enc_init_v2(MppEnc *enc, MppEncInitCfg *cfg)
{
MPP_RET ret;
@ -46,6 +65,17 @@ MPP_RET mpp_enc_init_v2(MppEnc *enc, MppEncInitCfg *cfg)
return MPP_ERR_MALLOC;
}
mpp_enc_cfg_get(&p->set_obj);
mpp_enc_cfg_get(&p->cfg_obj);
if (!p->set_obj || !p->cfg_obj) {
mpp_err_f("failed to get cfg set\n");
ret = MPP_ERR_MALLOC;
goto ERR_RET;
}
p->set = (MppEncCfgSet *)kmpp_obj_to_entry(p->set_obj);
p->cfg = (MppEncCfgSet *)kmpp_obj_to_entry(p->cfg_obj);
ret = mpp_enc_refs_init(&p->refs);
if (ret) {
mpp_err_f("could not init enc refs\n");
@ -59,7 +89,7 @@ MPP_RET mpp_enc_init_v2(MppEnc *enc, MppEncInitCfg *cfg)
// H.264 encoder use mpp_enc_hal path
// create hal first
enc_hal_cfg.coding = coding;
enc_hal_cfg.cfg = &p->cfg;
enc_hal_cfg.cfg = p->cfg;
enc_hal_cfg.output_cb = &p->output_cb;
enc_hal_cfg.task_cnt = cfg->task_cnt;
enc_hal_cfg.type = VPU_CLIENT_BUTT;
@ -68,7 +98,7 @@ MPP_RET mpp_enc_init_v2(MppEnc *enc, MppEncInitCfg *cfg)
ctrl_cfg.coding = coding;
ctrl_cfg.type = VPU_CLIENT_BUTT;
ctrl_cfg.cfg = &p->cfg;
ctrl_cfg.cfg = p->cfg;
ctrl_cfg.refs = p->refs;
ret = mpp_enc_hal_init(&enc_hal, &enc_hal_cfg);
@ -122,12 +152,17 @@ MPP_RET mpp_enc_init_v2(MppEnc *enc, MppEncInitCfg *cfg)
}
/* NOTE: setup configure coding for check */
p->cfg.base.coding = coding;
p->cfg.plt_cfg.plt = &p->cfg.plt_data;
mpp_enc_ref_cfg_init(&p->cfg.ref_cfg);
ret = mpp_enc_ref_cfg_copy(p->cfg.ref_cfg, mpp_enc_ref_default());
p->cfg->base.coding = coding;
p->cfg->plt_cfg.plt = &p->cfg->plt_data;
copy_enc_cfg(p->set_obj, p->cfg_obj);
mpp_enc_ref_cfg_init(&p->cfg->ref_cfg);
mpp_enc_ref_cfg_init(&p->set->ref_cfg);
ret = mpp_enc_ref_cfg_copy(p->cfg->ref_cfg, mpp_enc_ref_default());
ret = mpp_enc_ref_cfg_copy(p->set->ref_cfg, mpp_enc_ref_default());
ret = mpp_enc_refs_set_cfg(p->refs, mpp_enc_ref_default());
mpp_enc_refs_set_rc_igop(p->refs, p->cfg.rc.gop);
mpp_enc_refs_set_rc_igop(p->refs, p->cfg->rc.gop);
sem_init(&p->enc_reset, 0, 0);
sem_init(&p->cmd_start, 0, 0);
@ -172,9 +207,14 @@ MPP_RET mpp_enc_deinit_v2(MppEnc ctx)
MPP_FREE(enc->hdr_buf);
if (enc->cfg.ref_cfg) {
mpp_enc_ref_cfg_deinit(&enc->cfg.ref_cfg);
enc->cfg.ref_cfg = NULL;
if (enc->set->ref_cfg) {
mpp_enc_ref_cfg_deinit(&enc->set->ref_cfg);
enc->set->ref_cfg = NULL;
}
if (enc->cfg->ref_cfg) {
mpp_enc_ref_cfg_deinit(&enc->cfg->ref_cfg);
enc->cfg->ref_cfg = NULL;
}
if (enc->refs) {
@ -182,6 +222,16 @@ MPP_RET mpp_enc_deinit_v2(MppEnc ctx)
enc->refs = NULL;
}
if (enc->set_obj) {
kmpp_obj_put_f(enc->set_obj);
enc->set_obj = NULL;
}
if (enc->cfg_obj) {
kmpp_obj_put_f(enc->cfg_obj);
enc->cfg_obj = NULL;
}
if (enc->rc_ctx) {
rc_deinit(enc->rc_ctx);
enc->rc_ctx = NULL;
@ -334,30 +384,9 @@ MPP_RET mpp_enc_control_v2(MppEnc ctx, MpiCmd cmd, void *param)
switch (cmd) {
case MPP_ENC_GET_CFG : {
MppEncCfgImpl *impl = (MppEncCfgImpl *)param;
MppEncCfgSet *cfg;
if (impl->is_kobj) {
mpp_loge("can not MPP_ENC_GET_CFG by kobj %p\n", impl);
ret = MPP_NOK;
break;
}
cfg = impl->cfg;
enc_dbg_ctrl("get all config\n");
memcpy(cfg, &enc->cfg, sizeof(enc->cfg));
if (cfg->prep.rotation == MPP_ENC_ROT_90 ||
cfg->prep.rotation == MPP_ENC_ROT_270) {
MPP_SWAP(RK_S32, cfg->prep.width, cfg->prep.height);
}
/* cleanup output change flag to avoid extra change flag bit when user resend the cfg */
cfg->base.change = 0;
cfg->rc.change = 0;
cfg->prep.change = 0;
cfg->hw.change = 0;
cfg->split.change = 0;
cfg->tune.change = 0;
enc_dbg_ctrl("get enc config start\n");
copy_enc_cfg(param, enc->cfg_obj);
enc_dbg_ctrl("get enc config done\n");
} break;
case MPP_ENC_SET_PREP_CFG :
case MPP_ENC_GET_PREP_CFG :
@ -384,19 +413,18 @@ MPP_RET mpp_enc_control_v2(MppEnc ctx, MpiCmd cmd, void *param)
} break;
case MPP_ENC_GET_OSD_PLT_CFG : {
enc_dbg_ctrl("get osd plt cfg\n");
memcpy(param, &enc->cfg.plt_cfg, sizeof(enc->cfg.plt_cfg));
memcpy(param, &enc->cfg->plt_cfg, sizeof(enc->cfg->plt_cfg));
} break;
default : {
// Cmd which is not get configure will handle by enc_impl
if (cmd == MPP_ENC_SET_CFG) {
MppEncCfgImpl *impl = (MppEncCfgImpl *)param;
KmppObj obj = (KmppObj)param;
if (impl->is_kobj) {
mpp_loge("can not MPP_ENC_SET_CFG by kobj %p\n", impl);
if (kmpp_obj_is_kobj(obj)) {
mpp_loge("can not MPP_ENC_SET_CFG by kobj %p\n", obj);
ret = MPP_NOK;
break;
}
param = impl->cfg;
}
enc->cmd = cmd;

6
mpp/common/jpege_syntax.h
View file

@ -57,12 +57,14 @@ typedef struct JpegeSyntax_t {
RK_U32 offset_y;
/* For quantization table */
RK_U32 quality;
RK_S32 q_mode;
RK_S32 quant;
RK_S32 q_factor;
RK_S32 qf_min;
RK_S32 qf_max;
RK_U8 *qtable_y;
RK_U8 *qtable_c;
RK_U8 *qtable_u;
RK_U8 *qtable_v;
/*
* For color conversion

126
mpp/hal/common/jpeg/hal_jpege_hdr.c
View file

@ -14,6 +14,8 @@
* limitations under the License.
*/
#include <string.h>
#include "mpp_mem.h"
#include "mpp_debug.h"
#include "mpp_common.h"
@ -311,6 +313,31 @@ static const RK_U8 qtable_c[11][64] = {
}
};
/*
* from RFC435 spec.
*/
const RK_U8 jpege_luma_quantizer[QUANTIZE_TABLE_SIZE] = {
16, 11, 10, 16, 24, 40, 51, 61,
12, 12, 14, 19, 26, 58, 60, 55,
14, 13, 16, 24, 40, 57, 69, 56,
14, 17, 22, 29, 51, 87, 80, 62,
18, 22, 37, 56, 68, 109, 103, 77,
24, 35, 55, 64, 81, 104, 113, 92,
49, 64, 78, 87, 103, 121, 120, 101,
72, 92, 95, 98, 112, 100, 103, 99
};
const RK_U8 jpege_chroma_quantizer[QUANTIZE_TABLE_SIZE] = {
17, 18, 24, 47, 99, 99, 99, 99,
18, 21, 26, 66, 99, 99, 99, 99,
24, 26, 56, 99, 99, 99, 99, 99,
47, 66, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99
};
typedef struct {
RK_U32 Ci[MAX_NUMBER_OF_COMPONENTS];
RK_U32 Hi[MAX_NUMBER_OF_COMPONENTS];
@ -855,7 +882,7 @@ void write_jpeg_RestartInterval(JpegeBits *bits, JpegeSyntax *syntax)
}
}
MPP_RET write_jpeg_header(JpegeBits *bits, JpegeSyntax *syntax, const RK_U8 *qtables[2])
MPP_RET write_jpeg_header(JpegeBits *bits, JpegeSyntax *syntax, HalJpegeRc *hal_rc)
{
RK_U32 i = 0;
RK_U32 qtable_number = syntax->nb_components == 1 ? 1 : 2;
@ -864,23 +891,8 @@ MPP_RET write_jpeg_header(JpegeBits *bits, JpegeSyntax *syntax, const RK_U8 *qta
if (syntax->comment_length)
write_jpeg_comment_header(bits, syntax);
/* Quant header */
if (!qtables[0]) {
if (syntax->qtable_y)
qtables[0] = syntax->qtable_y;
else
qtables[0] = qtable_y[syntax->quality];
}
if (!qtables[1]) {
if (syntax->qtable_c)
qtables[1] = syntax->qtable_c;
else
qtables[1] = qtable_c[syntax->quality];
}
for (i = 0; i < qtable_number; i++)
write_jpeg_dqt_header(bits, qtables[i], i);
write_jpeg_dqt_header(bits, hal_rc->qtables[i], i);
/* Frame header */
write_jpeg_SOFO_header(bits, syntax);
@ -897,3 +909,83 @@ MPP_RET write_jpeg_header(JpegeBits *bits, JpegeSyntax *syntax, const RK_U8 *qta
jpege_bits_align_byte(bits);
return MPP_OK;
}
void hal_jpege_rc_init(HalJpegeRc *hal_rc)
{
/* default best quality qtable 10 */
hal_rc->q_mode = JPEG_QUANT;
hal_rc->quant = 10;
hal_rc->q_factor = -1;
memset(hal_rc->qtable_y, 1, QUANTIZE_TABLE_SIZE);
memset(hal_rc->qtable_u, 1, QUANTIZE_TABLE_SIZE);
memset(hal_rc->qtable_v, 1, QUANTIZE_TABLE_SIZE);
hal_rc->qtables[0] = qtable_y[hal_rc->quant];
hal_rc->qtables[1] = qtable_c[hal_rc->quant];
hal_rc->qtables[2] = qtable_c[hal_rc->quant];
}
static void qfactor_to_qf_table(RK_S32 qfactor, RK_U8 *hal_rc_qtable_y, RK_U8 *hal_rc_qtable_c)
{
RK_U32 q;
RK_U32 i;
if (qfactor < 50)
q = 5000 / qfactor;
else
q = 200 - (qfactor << 1);
for (i = 0; i < QUANTIZE_TABLE_SIZE; i++) {
RK_S16 lq = (jpege_luma_quantizer[i] * q + 50) / 100;
RK_S16 cq = (jpege_chroma_quantizer[i] * q + 50) / 100;
/* Limit the quantizers to 1 <= q <= 255 */
hal_rc_qtable_y[i] = MPP_CLIP3(1, 255, lq);
hal_rc_qtable_c[i] = MPP_CLIP3(1, 255, cq);
}
}
void hal_jpege_rc_update(HalJpegeRc *hal_rc, JpegeSyntax *syntax)
{
switch (syntax->q_mode) {
case JPEG_QUANT : {
RK_S32 quant = syntax->quant;
hal_rc->q_mode = JPEG_QUANT;
hal_rc->quant = quant;
hal_rc->qtables[0] = qtable_y[quant];
hal_rc->qtables[1] = qtable_c[quant];
hal_rc->qtables[2] = qtable_c[quant];
hal_rc->q_factor = -1;
} break;
case JPEG_QFACTOR : {
if (hal_rc->q_mode != JPEG_QFACTOR || hal_rc->q_factor != syntax->q_factor)
qfactor_to_qf_table(syntax->q_factor, hal_rc->qtable_y, hal_rc->qtable_u);
hal_rc->q_mode = JPEG_QFACTOR;
/* NOTE: qfactor mode uv use the same table */
hal_rc->qtables[0] = hal_rc->qtable_y;
hal_rc->qtables[1] = hal_rc->qtable_u;
hal_rc->qtables[2] = hal_rc->qtable_u;
hal_rc->q_factor = syntax->q_factor;
} break;
case JPEG_QTABLE : {
hal_rc->q_mode = JPEG_QTABLE;
memcpy(hal_rc->qtable_y, syntax->qtable_y, QUANTIZE_TABLE_SIZE);
memcpy(hal_rc->qtable_u, syntax->qtable_u, QUANTIZE_TABLE_SIZE);
memcpy(hal_rc->qtable_v, syntax->qtable_v, QUANTIZE_TABLE_SIZE);
hal_rc->qtables[0] = hal_rc->qtable_y;
hal_rc->qtables[1] = hal_rc->qtable_u;
hal_rc->qtables[2] = hal_rc->qtable_v;
hal_rc->q_factor = -1;
} break;
default : {
mpp_err_f("invalid q_mode %d use default best quanlity qtable\n", syntax->q_mode);
hal_rc->q_mode = JPEG_QUANT;
hal_rc->quant = 10;
hal_rc->qtables[0] = qtable_y[10];
hal_rc->qtables[1] = qtable_c[10];
hal_rc->qtables[2] = qtable_c[10];
hal_rc->q_factor = -1;
} break;
}
}

17
mpp/hal/common/jpeg/hal_jpege_hdr.h
View file

@ -25,6 +25,17 @@ typedef void *JpegeBits;
extern "C" {
#endif
#define QUANTIZE_TABLE_SIZE 64
typedef struct HalJpegeRc_t {
RK_S32 q_mode;
RK_S32 quant;
RK_S32 q_factor;
RK_U8 qtable_y[QUANTIZE_TABLE_SIZE];
RK_U8 qtable_u[QUANTIZE_TABLE_SIZE];
RK_U8 qtable_v[QUANTIZE_TABLE_SIZE];
const RK_U8 *qtables[3];
} HalJpegeRc;
void jpege_bits_init(JpegeBits *ctx);
void jpege_bits_deinit(JpegeBits ctx);
@ -36,8 +47,10 @@ RK_U8 *jpege_bits_get_buf(JpegeBits ctx);
RK_S32 jpege_bits_get_bitpos(JpegeBits ctx);
RK_S32 jpege_bits_get_bytepos(JpegeBits ctx);
MPP_RET write_jpeg_header(JpegeBits *bits, JpegeSyntax *syntax,
const RK_U8 *qtable[2]);
MPP_RET write_jpeg_header(JpegeBits *bits, JpegeSyntax *syntax, HalJpegeRc *rc);
void hal_jpege_rc_init(HalJpegeRc *hal_rc);
void hal_jpege_rc_update(HalJpegeRc *hal_rc, JpegeSyntax *syntax);
#ifdef __cplusplus
}

5
mpp/hal/rkenc/h264e/hal_h264e_vepu510.c
View file

@ -477,7 +477,7 @@ static MPP_RET hal_h264e_vepu510_prepare(void *hal)
hal_h264e_dbg_func("enter %p\n", hal);
if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
if (prep->change_res) {
RK_S32 i;
// pre-alloc required buffers to reduce first frame delay
@ -485,7 +485,7 @@ static MPP_RET hal_h264e_vepu510_prepare(void *hal)
for (i = 0; i < ctx->max_buf_cnt; i++)
hal_bufs_get_buf(ctx->hw_recn, i);
prep->change = 0;
prep->change_res = 0;
}
hal_h264e_dbg_func("leave %p\n", hal);
@ -1593,7 +1593,6 @@ static void setup_vepu510_split(HalVepu510RegSet *regs, MppEncCfgSet *enc_cfg)
mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
} break;
}
cfg->change = 0;
hal_h264e_dbg_func("leave\n");
}

5
mpp/hal/rkenc/h264e/hal_h264e_vepu511.c
View file

@ -476,7 +476,7 @@ static MPP_RET hal_h264e_vepu511_prepare(void *hal)
hal_h264e_dbg_func("enter %p\n", hal);
if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
if (prep->change_res) {
RK_S32 i;
// pre-alloc required buffers to reduce first frame delay
@ -484,7 +484,7 @@ static MPP_RET hal_h264e_vepu511_prepare(void *hal)
for (i = 0; i < ctx->max_buf_cnt; i++)
hal_bufs_get_buf(ctx->hw_recn, i);
prep->change = 0;
prep->change_res = 0;
}
hal_h264e_dbg_func("leave %p\n", hal);
@ -1593,7 +1593,6 @@ static void setup_vepu511_split(HalVepu511RegSet *regs, MppEncCfgSet *enc_cfg)
mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
} break;
}
cfg->change = 0;
hal_h264e_dbg_func("leave\n");
}

6
mpp/hal/rkenc/h264e/hal_h264e_vepu540c.c
View file

@ -283,7 +283,7 @@ static MPP_RET hal_h264e_vepu540c_prepare(void *hal)
hal_h264e_dbg_func("enter %p\n", hal);
if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
if (prep->change_res) {
RK_S32 i;
// pre-alloc required buffers to reduce first frame delay
@ -291,7 +291,7 @@ static MPP_RET hal_h264e_vepu540c_prepare(void *hal)
for (i = 0; i < ctx->max_buf_cnt; i++)
hal_bufs_get_buf(ctx->hw_recn, i);
prep->change = 0;
prep->change_res = 0;
}
hal_h264e_dbg_func("leave %p\n", hal);
@ -1154,8 +1154,6 @@ static void setup_vepu540c_split(HalVepu540cRegSet *regs, MppEncCfgSet *cfg)
} break;
}
cfg->split.change = 0;
hal_h264e_dbg_func("leave\n");
}

6
mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
View file

@ -276,7 +276,7 @@ static MPP_RET hal_h264e_vepu541_prepare(void *hal)
hal_h264e_dbg_func("enter %p\n", hal);
if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
if (prep->change_res) {
RK_S32 i;
// pre-alloc required buffers to reduce first frame delay
@ -284,7 +284,7 @@ static MPP_RET hal_h264e_vepu541_prepare(void *hal)
for (i = 0; i < ctx->max_buf_cnt; i++)
hal_bufs_get_buf(ctx->hw_recn, i);
prep->change = 0;
prep->change_res = 0;
}
hal_h264e_dbg_func("leave %p\n", hal);
@ -1213,8 +1213,6 @@ static void setup_vepu541_split(Vepu541H264eRegSet *regs, MppEncSliceSplit *cfg)
} break;
}
cfg->change = 0;
hal_h264e_dbg_func("leave\n");
}

6
mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
View file

@ -499,7 +499,7 @@ static MPP_RET hal_h264e_vepu580_prepare(void *hal)
hal_h264e_dbg_func("enter %p\n", hal);
if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
if (prep->change_res) {
RK_S32 i;
// pre-alloc required buffers to reduce first frame delay
@ -507,7 +507,7 @@ static MPP_RET hal_h264e_vepu580_prepare(void *hal)
for (i = 0; i < ctx->max_buf_cnt; i++)
hal_bufs_get_buf(ctx->hw_recn, i);
prep->change = 0;
prep->change_res = 0;
}
hal_h264e_dbg_func("leave %p\n", hal);
@ -1722,8 +1722,6 @@ static void setup_vepu580_split(HalVepu580RegSet *regs, MppEncCfgSet *enc_cfg)
} break;
}
cfg->change = 0;
hal_h264e_dbg_func("leave\n");
}

6
mpp/hal/rkenc/h265e/hal_h265e_vepu510.c
View file

@ -1186,7 +1186,7 @@ static MPP_RET hal_h265e_vepu510_prepare(void *hal)
hal_h265e_dbg_func("enter %p\n", hal);
if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
if (prep->change_res) {
RK_S32 i;
// pre-alloc required buffers to reduce first frame delay
@ -1194,7 +1194,7 @@ static MPP_RET hal_h265e_vepu510_prepare(void *hal)
for (i = 0; i < ctx->max_buf_cnt; i++)
hal_bufs_get_buf(ctx->dpb_bufs, i);
prep->change = 0;
prep->change_res = 0;
}
hal_h265e_dbg_func("leave %p\n", hal);
@ -1871,8 +1871,6 @@ static void setup_vepu510_split(H265eV510RegSet *regs, MppEncCfgSet *enc_cfg, RK
} break;
}
cfg->change = 0;
hal_h265e_dbg_func("leave\n");
}

6
mpp/hal/rkenc/h265e/hal_h265e_vepu511.c
View file

@ -581,7 +581,7 @@ static MPP_RET hal_h265e_vepu511_prepare(void *hal)
hal_h265e_dbg_func("enter %p\n", hal);
if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
if (prep->change_res) {
RK_S32 i;
// pre-alloc required buffers to reduce first frame delay
@ -589,7 +589,7 @@ static MPP_RET hal_h265e_vepu511_prepare(void *hal)
for (i = 0; i < ctx->max_buf_cnt; i++)
hal_bufs_get_buf(ctx->dpb_bufs, i);
prep->change = 0;
prep->change_res = 0;
}
hal_h265e_dbg_func("leave %p\n", hal);
@ -986,7 +986,7 @@ static void vepu511_h265_set_split(H265eV511RegSet *regs, MppEncCfgSet *enc_cfg)
mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
} break;
}
cfg->change = 0;
hal_h265e_dbg_func("leave\n");
}

6
mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c
View file

@ -590,7 +590,7 @@ static MPP_RET hal_h265e_vepu540c_prepare(void *hal)
hal_h265e_dbg_func("enter %p\n", hal);
if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
if (prep->change_res) {
RK_S32 i;
// pre-alloc required buffers to reduce first frame delay
@ -598,7 +598,7 @@ static MPP_RET hal_h265e_vepu540c_prepare(void *hal)
for (i = 0; i < ctx->max_buf_cnt; i++)
hal_bufs_get_buf(ctx->dpb_bufs, i);
prep->change = 0;
prep->change_res = 0;
}
hal_h265e_dbg_func("leave %p\n", hal);
@ -1186,8 +1186,6 @@ static void vepu540c_h265_set_split(H265eV540cRegSet *regs, MppEncCfgSet *enc_cf
} break;
}
cfg->change = 0;
hal_h265e_dbg_func("leave\n");
}

6
mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
View file

@ -705,7 +705,7 @@ static MPP_RET hal_h265e_vepu54x_prepare(void *hal)
hal_h265e_dbg_func("enter %p\n", hal);
if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
if (prep->change_res) {
RK_S32 i;
// pre-alloc required buffers to reduce first frame delay
@ -713,7 +713,7 @@ static MPP_RET hal_h265e_vepu54x_prepare(void *hal)
for (i = 0; i < ctx->max_buf_cnt; i++)
hal_bufs_get_buf(ctx->dpb_bufs, i);
prep->change = 0;
prep->change_res = 0;
}
hal_h265e_dbg_func("leave %p\n", hal);
@ -1495,8 +1495,6 @@ static void setup_vepu541_split(H265eV541RegSet *regs, MppEncSliceSplit *cfg)
} break;
}
cfg->change = 0;
hal_h265e_dbg_func("leave\n");
}

6
mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
View file

@ -1610,7 +1610,7 @@ static MPP_RET hal_h265e_vepu580_prepare(void *hal)
hal_h265e_dbg_func("enter %p\n", hal);
if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
if (prep->change_res) {
RK_S32 i;
// pre-alloc required buffers to reduce first frame delay
@ -1618,7 +1618,7 @@ static MPP_RET hal_h265e_vepu580_prepare(void *hal)
for (i = 0; i < ctx->max_buf_cnt; i++)
hal_bufs_get_buf(ctx->dpb_bufs, i);
prep->change = 0;
prep->change_res = 0;
}
hal_h265e_dbg_func("leave %p\n", hal);
@ -2667,8 +2667,6 @@ static void vepu580_setup_split(H265eV580RegSet *regs, MppEncCfgSet *enc_cfg, RK
} break;
}
cfg->change = 0;
hal_h265e_dbg_func("leave\n");
}

23
mpp/hal/rkenc/jpege/hal_jpege_vepu511.c
View file

@ -58,6 +58,7 @@ typedef struct JpegeV511HalContext_t {
JpegeBits bits;
JpegeSyntax syntax;
HalJpegeRc hal_rc;
} JpegeV511HalContext;
MPP_RET hal_jpege_vepu511_init(void *hal, MppEncHalCfg *cfg)
@ -84,6 +85,7 @@ MPP_RET hal_jpege_vepu511_init(void *hal, MppEncHalCfg *cfg)
ctx->dev = cfg->dev;
jpege_bits_init(&ctx->bits);
mpp_assert(ctx->bits);
hal_jpege_rc_init(&ctx->hal_rc);
hal_jpege_leave();
return ret;
@ -357,7 +359,6 @@ MPP_RET hal_jpege_vepu511_gen_regs(void *hal, HalEncTask *task)
Vepu511ControlCfg *reg_ctl = &regs->reg_ctl;
JpegVepu511Base *reg_base = &regs->reg_base;
JpegeBits bits = ctx->bits;
const RK_U8 *qtable[2] = {NULL};
size_t length = mpp_packet_get_length(task->packet);
RK_U8 *buf = mpp_buffer_get_ptr(task->output);
size_t size = mpp_buffer_get_size(task->output);
@ -374,12 +375,17 @@ MPP_RET hal_jpege_vepu511_gen_regs(void *hal, HalEncTask *task)
memset(regs, 0, sizeof(JpegV511RegSet));
if (syntax->q_mode == JPEG_QFACTOR) {
syntax->q_factor = 100 - task->rc_task->info.quality_target;
hal_jpege_rc_update(&ctx->hal_rc, syntax);
}
/* write header to output buffer */
jpege_bits_setup(bits, buf, (RK_U32)size);
/* seek length bytes data */
jpege_seek_bits(bits, length << 3);
/* NOTE: write header will update qtable */
write_jpeg_header(bits, syntax, qtable);
write_jpeg_header(bits, syntax, &ctx->hal_rc);
bitpos = jpege_bits_get_bitpos(bits);
task->length = (bitpos + 7) >> 3;
@ -434,19 +440,19 @@ MPP_RET hal_jpege_vepu511_gen_regs(void *hal, HalEncTask *task)
for ( i = 0; i < 8; i++) {
for ( j = 0; j < 8; j++) {
tbl[i * 8 + j] = 0x8000 / qtable[0][j * 8 + i];
tbl[i * 8 + j] = 0x8000 / ctx->hal_rc.qtables[0][j * 8 + i];
}
}
tbl += 64;
for ( i = 0; i < 8; i++) {
for ( j = 0; j < 8; j++) {
tbl[i * 8 + j] = 0x8000 / qtable[1][j * 8 + i];
tbl[i * 8 + j] = 0x8000 / ctx->hal_rc.qtables[1][j * 8 + i];
}
}
tbl += 64;
for ( i = 0; i < 8; i++) {
for ( j = 0; j < 8; j++) {
tbl[i * 8 + j] = 0x8000 / qtable[1][j * 8 + i];
tbl[i * 8 + j] = 0x8000 / ctx->hal_rc.qtables[1][j * 8 + i];
}
}
}
@ -621,6 +627,13 @@ MPP_RET hal_jpege_vepu511_get_task(void *hal, HalEncTask *task)
}
if (ctx->cfg->jpeg.update) {
hal_jpege_rc_update(&ctx->hal_rc, syntax);
ctx->cfg->jpeg.update = 0;
}
task->rc_task->frm.is_intra = 1;
hal_jpege_leave();
return MPP_OK;
}

22
mpp/hal/rkenc/jpege/hal_jpege_vepu540c.c
View file

@ -68,6 +68,7 @@ typedef struct jpegeV540cHalContext_t {
JpegeBits bits;
JpegeSyntax syntax;
HalJpegeRc hal_rc;
} jpegeV540cHalContext;
MPP_RET hal_jpege_v540c_init(void *hal, MppEncHalCfg *cfg)
@ -96,6 +97,7 @@ MPP_RET hal_jpege_v540c_init(void *hal, MppEncHalCfg *cfg)
ctx->dev = cfg->dev;
jpege_bits_init(&ctx->bits);
mpp_assert(ctx->bits);
hal_jpege_rc_init(&ctx->hal_rc);
hal_jpege_leave();
return ret;
@ -141,7 +143,6 @@ MPP_RET hal_jpege_v540c_gen_regs(void *hal, HalEncTask *task)
jpeg_vepu540c_control_cfg *reg_ctl = &regs->reg_ctl;
jpeg_vepu540c_base *reg_base = &regs->reg_base;
JpegeBits bits = ctx->bits;
const RK_U8 *qtable[2] = {NULL};
size_t length = mpp_packet_get_length(task->packet);
RK_U8 *buf = mpp_buffer_get_ptr(task->output);
size_t size = mpp_buffer_get_size(task->output);
@ -157,12 +158,17 @@ MPP_RET hal_jpege_v540c_gen_regs(void *hal, HalEncTask *task)
memset(regs, 0, sizeof(JpegV540cRegSet));
if (syntax->q_mode == JPEG_QFACTOR) {
syntax->q_factor = 100 - task->rc_task->info.quality_target;
hal_jpege_rc_update(&ctx->hal_rc, syntax);
}
/* write header to output buffer */
jpege_bits_setup(bits, buf, (RK_U32)size);
/* seek length bytes data */
jpege_seek_bits(bits, length << 3);
/* NOTE: write header will update qtable */
write_jpeg_header(bits, syntax, qtable);
write_jpeg_header(bits, syntax, &ctx->hal_rc);
bitpos = jpege_bits_get_bitpos(bits);
task->length = (bitpos + 7) >> 3;
@ -205,19 +211,19 @@ MPP_RET hal_jpege_v540c_gen_regs(void *hal, HalEncTask *task)
for ( i = 0; i < 8; i++) {
for ( j = 0; j < 8; j++) {
tbl[i * 8 + j] = 0x8000 / qtable[0][j * 8 + i];
tbl[i * 8 + j] = 0x8000 / ctx->hal_rc.qtables[0][j * 8 + i];
}
}
tbl += 64;
for ( i = 0; i < 8; i++) {
for ( j = 0; j < 8; j++) {
tbl[i * 8 + j] = 0x8000 / qtable[1][j * 8 + i];
tbl[i * 8 + j] = 0x8000 / ctx->hal_rc.qtables[1][j * 8 + i];
}
}
tbl += 64;
for ( i = 0; i < 8; i++) {
for ( j = 0; j < 8; j++) {
tbl[i * 8 + j] = 0x8000 / qtable[1][j * 8 + i];
tbl[i * 8 + j] = 0x8000 / ctx->hal_rc.qtables[1][j * 8 + i];
}
}
}
@ -374,6 +380,12 @@ MPP_RET hal_jpege_v540c_get_task(void *hal, HalEncTask *task)
mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
}
if (ctx->cfg->jpeg.update) {
hal_jpege_rc_update(&ctx->hal_rc, syntax);
ctx->cfg->jpeg.update = 0;
}
task->rc_task->frm.is_intra = 1;
hal_jpege_leave();
return MPP_OK;
}

22
mpp/hal/rkenc/jpege/hal_jpege_vpu720.c
View file

@ -109,6 +109,7 @@ typedef struct JpegeVpu720HalCtx_t {
MppBufferGroup group;
MppBuffer qtbl_buffer;
RK_U16 *qtbl_sw_buf;
HalJpegeRc hal_rc;
} JpegeVpu720HalCtx;
#define JPEGE_VPU720_QTABLE_SIZE (64 * 3)
@ -148,6 +149,7 @@ static MPP_RET hal_jpege_vpu720_init(void *hal, MppEncHalCfg *cfg)
ret = mpp_buffer_get(ctx->group, &ctx->qtbl_buffer, JPEGE_VPU720_QTABLE_SIZE * sizeof(RK_U16));
mpp_buffer_attach_dev(ctx->qtbl_buffer, ctx->dev);
ctx->qtbl_sw_buf = (RK_U16 *)mpp_calloc(RK_U16, JPEGE_VPU720_QTABLE_SIZE);
hal_jpege_rc_init(&ctx->hal_rc);
hal_jpege_leave();
return ret;
@ -373,7 +375,6 @@ MPP_RET hal_jpege_vpu720_gen_regs(void *hal, HalEncTask *task)
JpegeVpu720Reg *regs = ctx->regs;
JpegeVpu720BaseReg *reg_base = &regs->reg_base;
JpegeBits bits = ctx->bits;
const RK_U8 *qtable[2] = {NULL};
size_t length = mpp_packet_get_length(task->packet);
RK_U8 *buf = mpp_buffer_get_ptr(task->output);
size_t size = mpp_buffer_get_size(task->output);
@ -391,9 +392,15 @@ MPP_RET hal_jpege_vpu720_gen_regs(void *hal, HalEncTask *task)
memset(regs, 0, sizeof(JpegeVpu720Reg));
mpp_buffer_sync_begin(task->output);
if (syntax->q_mode == JPEG_QFACTOR) {
syntax->q_factor = 100 - task->rc_task->info.quality_target;
hal_jpege_rc_update(&ctx->hal_rc, syntax);
}
jpege_bits_setup(bits, buf, (RK_U32)size);
jpege_seek_bits(bits, length << 3);
write_jpeg_header(bits, syntax, qtable);
write_jpeg_header(bits, syntax, &ctx->hal_rc);
mpp_buffer_sync_end(task->output);
bitpos = jpege_bits_get_bitpos(bits);
@ -449,8 +456,8 @@ MPP_RET hal_jpege_vpu720_gen_regs(void *hal, HalEncTask *task)
for (i = 0; i < 8; i++) {
for (j = 0; j < 8; j++) {
ctx->qtbl_sw_buf[i * 8 + j] = 0x8000 / qtable[0][j * 8 + i];
ctx->qtbl_sw_buf[64 + i * 8 + j] = 0x8000 / qtable[1][j * 8 + i];
ctx->qtbl_sw_buf[i * 8 + j] = 0x8000 / ctx->hal_rc.qtables[0][j * 8 + i];
ctx->qtbl_sw_buf[64 + i * 8 + j] = 0x8000 / ctx->hal_rc.qtables[1][j * 8 + i];
}
}
@ -617,6 +624,13 @@ MPP_RET hal_jpege_vpu720_get_task(void *hal, HalEncTask *task)
hal_jpege_enter();
memcpy(&ctx->syntax, syntax, sizeof(ctx->syntax));
if (ctx->cfg->jpeg.update) {
hal_jpege_rc_update(&ctx->hal_rc, syntax);
ctx->cfg->jpeg.update = 0;
}
task->rc_task->frm.is_intra = 1;
// TODO config rc
hal_jpege_leave();
return MPP_OK;

1
mpp/hal/vpu/h264e/hal_h264e_vepu_v2.c
View file

@ -696,7 +696,6 @@ MPP_RET h264e_vepu_slice_split_cfg(H264eSlice *slice, HalH264eVepuMbRc *mbrc,
}
slice->is_multi_slice = (mbrc->slice_size_mb_rows > 0);
split->change = 0;
hal_h264e_dbg_func("leave\n");
return MPP_OK;

78
mpp/hal/vpu/jpege/hal_jpege_base.c
View file

@ -31,89 +31,11 @@ const RK_U32 qp_reorder_table[64] = {
6, 14, 22, 30, 7, 15, 23, 31, 38, 46, 54, 62, 39, 47, 55, 63
};
/*
* from RFC435 spec.
*/
const RK_U8 jpege_luma_quantizer[QUANTIZE_TABLE_SIZE] = {
16, 11, 10, 16, 24, 40, 51, 61,
12, 12, 14, 19, 26, 58, 60, 55,
14, 13, 16, 24, 40, 57, 69, 56,
14, 17, 22, 29, 51, 87, 80, 62,
18, 22, 37, 56, 68, 109, 103, 77,
24, 35, 55, 64, 81, 104, 113, 92,
49, 64, 78, 87, 103, 121, 120, 101,
72, 92, 95, 98, 112, 100, 103, 99
};
const RK_U8 jpege_chroma_quantizer[QUANTIZE_TABLE_SIZE] = {
17, 18, 24, 47, 99, 99, 99, 99,
18, 21, 26, 66, 99, 99, 99, 99,
24, 26, 56, 99, 99, 99, 99, 99,
47, 66, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99
};
const RK_U16 jpege_restart_marker[8] = {
0xFFD0, 0xFFD1, 0xFFD2, 0xFFD3,
0xFFD4, 0xFFD5, 0xFFD6, 0xFFD7,
};
MPP_RET hal_jpege_vepu_rc(HalJpegeCtx *ctx, HalEncTask *task)
{
HalJpegeRc *hal_rc = &ctx->hal_rc;
EncRcTaskInfo *rc_info = (EncRcTaskInfo *)&task->rc_task->info;
if (rc_info->quality_target != hal_rc->last_quality) {
RK_U32 i = 0;
RK_S32 q = 0;
hal_rc->q_factor = 100 - rc_info->quality_target;
hal_jpege_dbg_input("use qfactor=%d, rc_info->quality_target=%d\n", hal_rc->q_factor, rc_info->quality_target);
q = hal_rc->q_factor;
if (q < 50)
q = 5000 / q;
else
q = 200 - (q << 1);
for (i = 0; i < QUANTIZE_TABLE_SIZE; i++) {
RK_S16 lq = (jpege_luma_quantizer[i] * q + 50) / 100;
RK_S16 cq = (jpege_chroma_quantizer[i] * q + 50) / 100;
/* Limit the quantizers to 1 <= q <= 255 */
hal_rc->qtable_y[i] = MPP_CLIP3(1, 255, lq);
hal_rc->qtable_c[i] = MPP_CLIP3(1, 255, cq);
}
}
return MPP_OK;
}
MPP_RET hal_jpege_vepu_init_rc(HalJpegeRc *hal_rc)
{
memset(hal_rc, 0, sizeof(HalJpegeRc));
hal_rc->qtable_y = mpp_malloc(RK_U8, QUANTIZE_TABLE_SIZE);
hal_rc->qtable_c = mpp_malloc(RK_U8, QUANTIZE_TABLE_SIZE);
if (NULL == hal_rc->qtable_y || NULL == hal_rc->qtable_c) {
mpp_err_f("qtable is null, malloc err\n");
return MPP_ERR_MALLOC;
}
return MPP_OK;
}
MPP_RET hal_jpege_vepu_deinit_rc(HalJpegeRc *hal_rc)
{
MPP_FREE(hal_rc->qtable_y);
MPP_FREE(hal_rc->qtable_c);
return MPP_OK;
}
void get_msb_lsb_at_pos(RK_U32 *msb, RK_U32 *lsb, RK_U8 *buf, RK_U32 bytepos)
{
RK_U32 val32;

15
mpp/hal/vpu/jpege/hal_jpege_base.h
View file

@ -25,16 +25,6 @@
#include "jpege_syntax.h"
#include "hal_jpege_hdr.h"
#define QUANTIZE_TABLE_SIZE 64
typedef struct HalJpegeRc_t {
/* For quantization table */
RK_S32 q_factor;
RK_U8 *qtable_y;
RK_U8 *qtable_c;
RK_S32 last_quality;
} HalJpegeRc;
typedef struct hal_jpege_ctx_s {
MppDev dev;
MppClientType type;
@ -70,18 +60,13 @@ typedef struct hal_jpege_ctx_s {
} HalJpegeCtx;
extern const RK_U32 qp_reorder_table[QUANTIZE_TABLE_SIZE];
extern const RK_U8 jpege_luma_quantizer[QUANTIZE_TABLE_SIZE];
extern const RK_U8 jpege_chroma_quantizer[QUANTIZE_TABLE_SIZE];
extern const RK_U16 jpege_restart_marker[8];
#ifdef __cplusplus
extern "C" {
#endif
MPP_RET hal_jpege_vepu_rc(HalJpegeCtx *ctx, HalEncTask *task);
void get_msb_lsb_at_pos(RK_U32 *msb, RK_U32 *lsb, RK_U8 *buf, RK_U32 bytepos);
MPP_RET hal_jpege_vepu_init_rc(HalJpegeRc *hal_rc);
MPP_RET hal_jpege_vepu_deinit_rc(HalJpegeRc *hal_rc);
#ifdef __cplusplus
}

62
mpp/hal/vpu/jpege/hal_jpege_vepu1_v2.c
View file

@ -56,10 +56,6 @@ static MPP_RET hal_jpege_vepu1_init(void *hal, MppEncHalCfg *cfg)
jpege_bits_init(&ctx->bits);
mpp_assert(ctx->bits);
ret = hal_jpege_vepu_init_rc(&ctx->hal_rc);
if (ret)
return ret;
ctx->cfg = cfg->cfg;
ctx->reg_size = sizeof(RK_U32) * VEPU_JPEGE_VEPU1_NUM_REGS;
ctx->regs = mpp_calloc_size(void, ctx->reg_size + EXTRA_INFO_SIZE);
@ -74,6 +70,7 @@ static MPP_RET hal_jpege_vepu1_init(void *hal, MppEncHalCfg *cfg)
return MPP_NOK;
}
hal_jpege_rc_init(&ctx->hal_rc);
hal_jpege_dbg_func("leave hal %p\n", hal);
return MPP_OK;
}
@ -94,8 +91,6 @@ static MPP_RET hal_jpege_vepu1_deinit(void *hal)
ctx->dev = NULL;
}
hal_jpege_vepu_deinit_rc(&ctx->hal_rc);
MPP_FREE(ctx->regs);
MPP_FREE(ctx->regs_out);
hal_jpege_dbg_func("leave hal %p\n", hal);
@ -109,20 +104,7 @@ static MPP_RET hal_jpege_vepu1_get_task(void *hal, HalEncTask *task)
hal_jpege_dbg_func("enter hal %p\n", hal);
memcpy(&ctx->syntax, syntax, sizeof(ctx->syntax));
/* Set rc paramters */
hal_jpege_dbg_input("rc_mode %d\n", ctx->cfg->rc.rc_mode);
if (ctx->cfg->rc.rc_mode != MPP_ENC_RC_MODE_FIXQP) {
if (!ctx->hal_rc.q_factor) {
task->rc_task->info.quality_target = syntax->q_factor ? (100 - syntax->q_factor) : 80;
task->rc_task->info.quality_min = 100 - syntax->qf_max;
task->rc_task->info.quality_max = 100 - syntax->qf_min;
task->rc_task->frm.is_intra = 1;
} else {
task->rc_task->info.quality_target = ctx->hal_rc.last_quality;
task->rc_task->info.quality_min = 100 - syntax->qf_max;
task->rc_task->info.quality_max = 100 - syntax->qf_min;
}
}
ctx->hal_start_pos = mpp_packet_get_length(task->packet);
/* prepare for part encoding */
@ -135,6 +117,13 @@ static MPP_RET hal_jpege_vepu1_get_task(void *hal, HalEncTask *task)
task->part_first = 1;
task->part_last = 0;
if (ctx->cfg->jpeg.update) {
hal_jpege_rc_update(&ctx->hal_rc, syntax);
ctx->cfg->jpeg.update = 0;
}
task->rc_task->frm.is_intra = 1;
hal_jpege_dbg_func("leave hal %p\n", hal);
return MPP_OK;
@ -197,7 +186,6 @@ static MPP_RET hal_jpege_vepu1_gen_regs(void *hal, HalEncTask *task)
size_t length = mpp_packet_get_length(task->packet);
RK_U8 *buf = mpp_buffer_get_ptr(output);
size_t size = mpp_buffer_get_size(output);
const RK_U8 *qtable[2];
RK_S32 bitpos;
RK_S32 bytepos;
RK_U32 x_fill = 0;
@ -241,20 +229,16 @@ static MPP_RET hal_jpege_vepu1_gen_regs(void *hal, HalEncTask *task)
mpp_buffer_sync_begin(output);
if (syntax->q_mode == JPEG_QFACTOR) {
syntax->q_factor = 100 - task->rc_task->info.quality_target;
hal_jpege_rc_update(&ctx->hal_rc, syntax);
}
/* write header to output buffer */
jpege_bits_setup(bits, buf, (RK_U32)size);
/* seek length bytes data */
jpege_seek_bits(bits, length << 3);
/* NOTE: write header will update qtable */
if (ctx->cfg->rc.rc_mode != MPP_ENC_RC_MODE_FIXQP) {
hal_jpege_vepu_rc(ctx, task);
qtable[0] = ctx->hal_rc.qtable_y;
qtable[1] = ctx->hal_rc.qtable_c;
} else {
qtable[0] = NULL;
qtable[1] = NULL;
}
write_jpeg_header(bits, syntax, qtable);
write_jpeg_header(bits, syntax, &ctx->hal_rc);
memset(regs, 0, sizeof(RK_U32) * VEPU_JPEGE_VEPU1_NUM_REGS);
regs[11] = mpp_buffer_get_fd(input);
@ -376,17 +360,17 @@ static MPP_RET hal_jpege_vepu1_gen_regs(void *hal, HalEncTask *task)
for (i = 0; i < 16; i++) {
/* qtable need to reorder in particular order */
regs[i + 64] = qtable[0][qp_reorder_table[i * 4 + 0]] << 24 |
qtable[0][qp_reorder_table[i * 4 + 1]] << 16 |
qtable[0][qp_reorder_table[i * 4 + 2]] << 8 |
qtable[0][qp_reorder_table[i * 4 + 3]];
regs[i + 64] = ctx->hal_rc.qtables[0][qp_reorder_table[i * 4 + 0]] << 24 |
ctx->hal_rc.qtables[0][qp_reorder_table[i * 4 + 1]] << 16 |
ctx->hal_rc.qtables[0][qp_reorder_table[i * 4 + 2]] << 8 |
ctx->hal_rc.qtables[0][qp_reorder_table[i * 4 + 3]];
}
for (i = 0; i < 16; i++) {
/* qtable need to reorder in particular order */
regs[i + 80] = qtable[1][qp_reorder_table[i * 4 + 0]] << 24 |
qtable[1][qp_reorder_table[i * 4 + 1]] << 16 |
qtable[1][qp_reorder_table[i * 4 + 2]] << 8 |
qtable[1][qp_reorder_table[i * 4 + 3]];
regs[i + 80] = ctx->hal_rc.qtables[1][qp_reorder_table[i * 4 + 0]] << 24 |
ctx->hal_rc.qtables[1][qp_reorder_table[i * 4 + 1]] << 16 |
ctx->hal_rc.qtables[1][qp_reorder_table[i * 4 + 2]] << 8 |
ctx->hal_rc.qtables[1][qp_reorder_table[i * 4 + 3]];
}
}
@ -617,10 +601,10 @@ static MPP_RET hal_jpege_vepu1_ret_task(void *hal, HalEncTask *task)
{
HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
ctx->hal_rc.last_quality = task->rc_task->info.quality_target;
task->rc_task->info.bit_real = ctx->feedback.stream_length * 8;
task->hal_ret.data = &ctx->feedback;
task->hal_ret.number = 1;
task->rc_task->info.quality_real = task->rc_task->info.quality_target;
return MPP_OK;
}

72
mpp/hal/vpu/jpege/hal_jpege_vepu2_v2.c
View file

@ -85,9 +85,6 @@ MPP_RET hal_jpege_vepu2_init(void *hal, MppEncHalCfg *cfg)
jpege_bits_init(&ctx->bits);
mpp_assert(ctx->bits);
ret = hal_jpege_vepu_init_rc(&ctx->hal_rc);
if (ret)
return ret;
ctx->cfg = cfg->cfg;
ctx->reg_size = sizeof(RK_U32) * VEPU_JPEGE_VEPU2_NUM_REGS;
@ -103,6 +100,8 @@ MPP_RET hal_jpege_vepu2_init(void *hal, MppEncHalCfg *cfg)
return MPP_NOK;
}
hal_jpege_rc_init(&ctx->hal_rc);
hal_jpege_dbg_func("leave hal %p\n", hal);
return MPP_OK;
}
@ -123,8 +122,6 @@ MPP_RET hal_jpege_vepu2_deinit(void *hal)
ctx->dev = NULL;
}
hal_jpege_vepu_deinit_rc(&ctx->hal_rc);
if (ctx->ctx_ext) {
JpegeMultiCoreCtx *ctx_ext = ctx->ctx_ext;
RK_U32 i;
@ -164,20 +161,7 @@ MPP_RET hal_jpege_vepu2_get_task(void *hal, HalEncTask *task)
hal_jpege_dbg_func("enter hal %p\n", hal);
memcpy(&ctx->syntax, syntax, sizeof(ctx->syntax));
/* Set rc paramters */
hal_jpege_dbg_input("rc_mode %d\n", ctx->cfg->rc.rc_mode);
if (ctx->cfg->rc.rc_mode != MPP_ENC_RC_MODE_FIXQP) {
if (!ctx->hal_rc.q_factor) {
task->rc_task->info.quality_target = syntax->q_factor ? (100 - syntax->q_factor) : 80;
task->rc_task->info.quality_min = 100 - syntax->qf_max;
task->rc_task->info.quality_max = 100 - syntax->qf_min;
task->rc_task->frm.is_intra = 1;
} else {
task->rc_task->info.quality_target = ctx->hal_rc.last_quality;
task->rc_task->info.quality_min = 100 - syntax->qf_max;
task->rc_task->info.quality_max = 100 - syntax->qf_min;
}
}
ctx->hal_start_pos = mpp_packet_get_length(task->packet);
/* prepare for part encoding */
@ -337,6 +321,14 @@ MPP_RET hal_jpege_vepu2_get_task(void *hal, HalEncTask *task)
syntax->low_delay = 1;
ctx_ext->multi_core_enabled = 1;
}
if (ctx->cfg->jpeg.update) {
hal_jpege_rc_update(&ctx->hal_rc, syntax);
ctx->cfg->jpeg.update = 0;
}
task->rc_task->frm.is_intra = 1;
MULTI_CORE_SPLIT_DONE:
hal_jpege_dbg_func("leave hal %p\n", hal);
@ -389,7 +381,6 @@ MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalEncTask *task)
size_t length = mpp_packet_get_length(task->packet);
RK_U8 *buf = mpp_buffer_get_ptr(output);
size_t size = mpp_buffer_get_size(output);
const RK_U8 *qtable[2] = {NULL};
RK_S32 bitpos;
RK_S32 bytepos;
RK_U32 x_fill = 0;
@ -432,20 +423,17 @@ MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalEncTask *task)
mpp_buffer_sync_begin(output);
if (syntax->q_mode == JPEG_QFACTOR) {
syntax->q_factor = 100 - task->rc_task->info.quality_target;
hal_jpege_rc_update(&ctx->hal_rc, syntax);
}
/* write header to output buffer */
jpege_bits_setup(bits, buf, (RK_U32)size);
/* seek length bytes data */
jpege_seek_bits(bits, length << 3);
/* NOTE: write header will update qtable */
if (ctx->cfg->rc.rc_mode != MPP_ENC_RC_MODE_FIXQP) {
hal_jpege_vepu_rc(ctx, task);
qtable[0] = ctx->hal_rc.qtable_y;
qtable[1] = ctx->hal_rc.qtable_c;
} else {
qtable[0] = NULL;
qtable[1] = NULL;
}
write_jpeg_header(bits, syntax, qtable);
write_jpeg_header(bits, syntax, &ctx->hal_rc);
memset(regs, 0, sizeof(RK_U32) * VEPU_JPEGE_VEPU2_NUM_REGS);
// input address setup
@ -571,17 +559,17 @@ MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalEncTask *task)
for (i = 0; i < 16; i++) {
/* qtable need to reorder in particular order */
regs[i] = qtable[0][qp_reorder_table[i * 4 + 0]] << 24 |
qtable[0][qp_reorder_table[i * 4 + 1]] << 16 |
qtable[0][qp_reorder_table[i * 4 + 2]] << 8 |
qtable[0][qp_reorder_table[i * 4 + 3]];
regs[i] = ctx->hal_rc.qtables[0][qp_reorder_table[i * 4 + 0]] << 24 |
ctx->hal_rc.qtables[0][qp_reorder_table[i * 4 + 1]] << 16 |
ctx->hal_rc.qtables[0][qp_reorder_table[i * 4 + 2]] << 8 |
ctx->hal_rc.qtables[0][qp_reorder_table[i * 4 + 3]];
}
for (i = 0; i < 16; i++) {
/* qtable need to reorder in particular order */
regs[i + 16] = qtable[1][qp_reorder_table[i * 4 + 0]] << 24 |
qtable[1][qp_reorder_table[i * 4 + 1]] << 16 |
qtable[1][qp_reorder_table[i * 4 + 2]] << 8 |
qtable[1][qp_reorder_table[i * 4 + 3]];
regs[i + 16] = ctx->hal_rc.qtables[1][qp_reorder_table[i * 4 + 0]] << 24 |
ctx->hal_rc.qtables[1][qp_reorder_table[i * 4 + 1]] << 16 |
ctx->hal_rc.qtables[1][qp_reorder_table[i * 4 + 2]] << 8 |
ctx->hal_rc.qtables[1][qp_reorder_table[i * 4 + 3]];
}
}
@ -1050,19 +1038,11 @@ MPP_RET hal_jpege_vepu2_ret_task(void *hal, HalEncTask *task)
HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
EncRcTaskInfo *rc_info = &task->rc_task->info;
ctx->hal_rc.last_quality = task->rc_task->info.quality_target;
task->rc_task->info.bit_real = ctx->feedback.stream_length * 8;
task->hal_ret.data = &ctx->feedback;
task->hal_ret.number = 1;
if (ctx->cfg->rc.rc_mode != MPP_ENC_RC_MODE_FIXQP) {
if (!ctx->hal_rc.q_factor)
rc_info->quality_real = rc_info->quality_target;
else
rc_info->quality_real = ctx->hal_rc.q_factor;
} else {
rc_info->quality_real = ctx->cfg->jpeg.q_factor;
}
rc_info->quality_real = rc_info->quality_target;
return MPP_OK;
}

32
mpp/inc/mpp_enc_cfg.h
View file

@ -6,6 +6,7 @@
#ifndef __MPP_ENC_CFG_H__
#define __MPP_ENC_CFG_H__
#include "rk_venc_cfg.h"
#include "rk_venc_cmd.h"
#include "rk_venc_ref.h"
#include "mpp_rc_defs.h"
@ -19,8 +20,10 @@
*
* For normal user rc and prep config are enough.
*/
#define POS_TO_FLAG(p, pos) ((rk_u8*)(p) + ((rk_u32)(pos) & 0xffff))
#define POS_TO_ELEM(p, pos) ((rk_u8*)(p) + ((rk_u32)(pos) >> 16))
typedef struct MppEncCfgSet_t {
RK_S32 size;
MppEncBaseCfg base;
// esential config
@ -54,12 +57,25 @@ typedef struct MppEncCfgSet_t {
MppEncFineTuneCfg tune;
} MppEncCfgSet;
typedef struct MppEncCfgImpl_t {
RK_U32 is_kobj;
union {
MppEncCfgSet *cfg;
KmppObj obj;
};
} MppEncCfgImpl;
#ifdef __cplusplus
extern "C" {
#endif
rk_u32 *mpp_enc_cfg_prep_change(MppEncCfgSet *cfg);
rk_u32 *mpp_enc_cfg_rc_change(MppEncCfgSet *cfg);
rk_u32 *mpp_enc_cfg_hw_change(MppEncCfgSet *cfg);
rk_u32 *mpp_enc_cfg_tune_change(MppEncCfgSet *cfg);
rk_u32 *mpp_enc_cfg_h264_change(MppEncCfgSet *cfg);
rk_u32 *mpp_enc_cfg_h265_change(MppEncCfgSet *cfg);
rk_u32 *mpp_enc_cfg_jpeg_change(MppEncCfgSet *cfg);
rk_u32 *mpp_enc_cfg_vp8_change(MppEncCfgSet *cfg);
#define KMPP_OBJ_NAME mpp_enc_cfg
#define KMPP_OBJ_INTF_TYPE MppEncCfg
#include "kmpp_obj_func.h"
#ifdef __cplusplus
}
#endif
#endif /*__MPP_ENC_CFG_H__*/