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refactor[hal]: Update the reg offset setting method.

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Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Change-Id: If63cbfdae4150280b4d24698543990a454ed5f6f
This commit is contained in:
Hongjin Li 2024-12-27 11:54:55 +08:00
parent 8f8707fbb7
commit 8763144523
21 changed files with 118 additions and 389 deletions
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9
mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
View file

@ -657,19 +657,14 @@ MPP_RET hal_avs2d_rkv_gen_regs(void *hal, HalTaskInfo *task)
memcpy(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
regs->common.reg012.scanlist_addr_valid_en = 1;
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = 161;
trans_cfg.offset = reg_ctx->shph_offset;
regs->avs2d_addr.head_base = reg_ctx->bufs_fd;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 161, reg_ctx->shph_offset);
regs->avs2d_param.reg105.head_len = AVS2_RKV_SHPH_SIZE / 16;
regs->avs2d_param.reg105.head_len -= (regs->avs2d_param.reg105.head_len > 0) ? 1 : 0;
trans_cfg.reg_idx = 180;
trans_cfg.offset = reg_ctx->sclst_offset;
regs->avs2d_addr.scanlist_addr = reg_ctx->bufs_fd;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 180, reg_ctx->sclst_offset);
}
if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {

9
mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
View file

@ -724,19 +724,14 @@ MPP_RET hal_avs2d_vdpu382_gen_regs(void *hal, HalTaskInfo *task)
memcpy(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
regs->common.reg012.scanlist_addr_valid_en = 1;
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = 161;
trans_cfg.offset = reg_ctx->shph_offset;
regs->avs2d_addr.head_base = reg_ctx->bufs_fd;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 161, reg_ctx->shph_offset);
regs->avs2d_param.reg105.head_len = AVS2_RKV_SHPH_SIZE / 16;
regs->avs2d_param.reg105.head_len -= (regs->avs2d_param.reg105.head_len > 0) ? 1 : 0;
trans_cfg.reg_idx = 180;
trans_cfg.offset = reg_ctx->sclst_offset;
regs->avs2d_addr.scanlist_addr = reg_ctx->bufs_fd;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 180, reg_ctx->sclst_offset);
}
if (avs2d_hal_debug & AVS2D_HAL_DBG_IN) {

9
mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c
View file

@ -681,17 +681,12 @@ MPP_RET hal_avs2d_vdpu383_gen_regs(void *hal, HalTaskInfo *task)
memcpy(reg_ctx->bufs_ptr + reg_ctx->shph_offset, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat));
memcpy(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = 131;
trans_cfg.offset = reg_ctx->shph_offset;
regs->common_addr.reg131_gbl_base = reg_ctx->bufs_fd;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 131, reg_ctx->shph_offset);
regs->avs2d_paras.reg67_global_len = AVS2_383_SHPH_SIZE;
trans_cfg.reg_idx = 132;
trans_cfg.offset = reg_ctx->sclst_offset;
regs->common_addr.reg132_scanlist_addr = reg_ctx->bufs_fd;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 132, reg_ctx->sclst_offset);
}
// set rcb

13
mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
View file

@ -975,24 +975,17 @@ MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task)
}
regs->h264d_addr.pps_base = ctx->bufs_fd;
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = 161;
trans_cfg.offset = ctx->spspps_offset;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 161, ctx->spspps_offset);
memcpy((char *)ctx->bufs_ptr + ctx->rps_offset, (void *)ctx->rps, sizeof(ctx->rps));
regs->h264d_addr.rps_base = ctx->bufs_fd;
trans_cfg.reg_idx = 163;
trans_cfg.offset = ctx->rps_offset;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 163, ctx->rps_offset);
regs->common.reg012.scanlist_addr_valid_en = 1;
if (p_hal->pp->scaleing_list_enable_flag) {
memcpy((char *)ctx->bufs_ptr + ctx->sclst_offset, (void *)ctx->sclst, sizeof(ctx->sclst));
regs->h264d_addr.scanlist_addr = ctx->bufs_fd;
trans_cfg.reg_idx = 180;
trans_cfg.offset = ctx->sclst_offset;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 180, ctx->sclst_offset);
} else {
regs->h264d_addr.scanlist_addr = 0;
}

13
mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c
View file

@ -1003,24 +1003,17 @@ MPP_RET vdpu382_h264d_gen_regs(void *hal, HalTaskInfo *task)
}
regs->h264d_addr.pps_base = ctx->bufs_fd;
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = 161;
trans_cfg.offset = ctx->spspps_offset;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 161, ctx->spspps_offset);
memcpy((char *)ctx->bufs_ptr + ctx->rps_offset, (void *)ctx->rps, sizeof(ctx->rps));
regs->h264d_addr.rps_base = ctx->bufs_fd;
trans_cfg.reg_idx = 163;
trans_cfg.offset = ctx->rps_offset;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 163, ctx->rps_offset);
regs->common.reg012.scanlist_addr_valid_en = 1;
if (p_hal->pp->scaleing_list_enable_flag) {
memcpy((char *)ctx->bufs_ptr + ctx->sclst_offset, (void *)ctx->sclst, sizeof(ctx->sclst));
regs->h264d_addr.scanlist_addr = ctx->bufs_fd;
trans_cfg.reg_idx = 180;
trans_cfg.offset = ctx->sclst_offset;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 180, ctx->sclst_offset);
} else {
regs->h264d_addr.scanlist_addr = 0;
}

13
mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c
View file

@ -888,23 +888,16 @@ MPP_RET vdpu383_h264d_gen_regs(void *hal, HalTaskInfo *task)
regs->common_addr.reg131_gbl_base = ctx->bufs_fd;
regs->h264d_paras.reg67_global_len = VDPU383_SPS_PPS_LEN / 16; // 128 bit as unit
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = 131;
trans_cfg.offset = ctx->spspps_offset;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 131, ctx->spspps_offset);
memcpy((char *)ctx->bufs_ptr + ctx->rps_offset, (void *)ctx->rps, sizeof(ctx->rps));
regs->common_addr.reg129_rps_base = ctx->bufs_fd;
trans_cfg.reg_idx = 129;
trans_cfg.offset = ctx->rps_offset;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 129, ctx->rps_offset);
if (p_hal->pp->scaleing_list_enable_flag) {
memcpy((char *)ctx->bufs_ptr + ctx->sclst_offset, (void *)ctx->sclst, sizeof(ctx->sclst));
regs->common_addr.reg132_scanlist_addr = ctx->bufs_fd;
trans_cfg.reg_idx = 132;
trans_cfg.offset = ctx->sclst_offset;
mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(p_hal->dev, 132, ctx->sclst_offset);
} else {
regs->common_addr.reg132_scanlist_addr = 0;
}

14
mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
View file

@ -411,7 +411,6 @@ static RK_S32 hal_h265d_v345_output_pps_packet(void *hal, void *dxva)
}
if (dxva_cxt->pp.scaling_list_enabled_flag) {
MppDevRegOffsetCfg trans_cfg;
RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->sclst_offset;
if (dxva_cxt->pp.scaling_list_data_present_flag) {
@ -428,9 +427,7 @@ static RK_S32 hal_h265d_v345_output_pps_packet(void *hal, void *dxva)
hw_reg->common.reg012.scanlist_addr_valid_en = 1;
/* need to config addr */
trans_cfg.reg_idx = 180;
trans_cfg.offset = addr + reg_ctx->sclst_offset;
mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(reg_ctx->dev, 180, addr + reg_ctx->sclst_offset);
}
for (i = 0; i < 64; i++)
@ -1006,7 +1003,6 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
hal_h265d_slice_output_rps(syn->dec.syntax.data, rps_ptr);
}
MppDevRegOffsetCfg trans_cfg;
/* cabac table */
hw_regs->h265d_addr.reg197_cabactbl_base = reg_ctx->bufs_fd;
/* pps */
@ -1135,13 +1131,9 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
hal_h265d_output_pps_packet(hal, syn->dec.syntax.data);
}
trans_cfg.reg_idx = 161;
trans_cfg.offset = reg_ctx->spspps_offset;
mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(reg_ctx->dev, 161, reg_ctx->spspps_offset);
/* rps */
trans_cfg.reg_idx = 163;
trans_cfg.offset = reg_ctx->rps_offset;
mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(reg_ctx->dev, 163, reg_ctx->rps_offset);
hw_regs->common.reg013.timeout_mode = 1;
hw_regs->common.reg013.cur_pic_is_idr = dxva_cxt->pp.IdrPicFlag;//p_hal->slice_long->idr_flag;

14
mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
View file

@ -404,7 +404,6 @@ static RK_S32 hal_h265d_v382_output_pps_packet(void *hal, void *dxva)
}
if (dxva_cxt->pp.scaling_list_enabled_flag) {
MppDevRegOffsetCfg trans_cfg;
RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->sclst_offset;
if (dxva_cxt->pp.scaling_list_data_present_flag) {
@ -421,9 +420,7 @@ static RK_S32 hal_h265d_v382_output_pps_packet(void *hal, void *dxva)
hw_reg->common.reg012.scanlist_addr_valid_en = 1;
/* need to config addr */
trans_cfg.reg_idx = 180;
trans_cfg.offset = addr + reg_ctx->sclst_offset;
mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(reg_ctx->dev, 180, addr + reg_ctx->sclst_offset);
}
for (i = 0; i < 64; i++)
@ -790,7 +787,6 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal, HalTaskInfo *syn)
hal_h265d_slice_output_rps(syn->dec.syntax.data, rps_ptr);
#endif
MppDevRegOffsetCfg trans_cfg;
/* cabac table */
hw_regs->h265d_addr.reg197_cabactbl_base = reg_ctx->bufs_fd;
/* pps */
@ -911,13 +907,9 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal, HalTaskInfo *syn)
}
hal_h265d_v382_output_pps_packet(hal, syn->dec.syntax.data);
trans_cfg.reg_idx = 161;
trans_cfg.offset = reg_ctx->spspps_offset;
mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(reg_ctx->dev, 161, reg_ctx->spspps_offset);
/* rps */
trans_cfg.reg_idx = 163;
trans_cfg.offset = reg_ctx->rps_offset;
mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(reg_ctx->dev, 163, reg_ctx->rps_offset);
hw_regs->common.reg013.cur_pic_is_idr = dxva_cxt->pp.IdrPicFlag;//p_hal->slice_long->idr_flag;

11
mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
View file

@ -1145,21 +1145,14 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal, HalTaskInfo *syn)
return MPP_OK;
}
MppDevRegOffsetCfg trans_cfg;
/* pps */
hw_regs->common_addr.reg131_gbl_base = reg_ctx->bufs_fd;
hw_regs->h265d_paras.reg67_global_len = 0xc; //22 * 8;
trans_cfg.reg_idx = 131;
trans_cfg.offset = reg_ctx->spspps_offset;
mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(reg_ctx->dev, 131, reg_ctx->spspps_offset);
/* rps */
hw_regs->common_addr.reg129_rps_base = reg_ctx->bufs_fd;
trans_cfg.reg_idx = 129;
trans_cfg.offset = reg_ctx->rps_offset;
mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(reg_ctx->dev, 129, reg_ctx->rps_offset);
hal_h265d_v345_output_pps_packet(hal, syn->dec.syntax.data);

80
mpp/hal/rkdec/vdpu34x_com.c
View file

@ -74,7 +74,6 @@ RK_S32 vdpu34x_get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 heigh
void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info)
{
MppDevRegOffsetCfg trans_cfg;
RK_S32 fd = mpp_buffer_get_fd(buf);
reg->reg139_rcb_dblk_base = fd;
@ -88,65 +87,26 @@ void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdp
reg->reg138_rcb_inter_col_base = fd;
reg->reg142_rcb_filter_col_base = fd;
if (info[RCB_DBLK_ROW].offset) {
trans_cfg.reg_idx = 139;
trans_cfg.offset = info[RCB_DBLK_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_INTRA_ROW].offset) {
trans_cfg.reg_idx = 133;
trans_cfg.offset = info[RCB_INTRA_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_TRANSD_ROW].offset) {
trans_cfg.reg_idx = 134;
trans_cfg.offset = info[RCB_TRANSD_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_STRMD_ROW].offset) {
trans_cfg.reg_idx = 136;
trans_cfg.offset = info[RCB_STRMD_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_INTER_ROW].offset) {
trans_cfg.reg_idx = 137;
trans_cfg.offset = info[RCB_INTER_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_SAO_ROW].offset) {
trans_cfg.reg_idx = 140;
trans_cfg.offset = info[RCB_SAO_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_FBC_ROW].offset) {
trans_cfg.reg_idx = 141;
trans_cfg.offset = info[RCB_FBC_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_TRANSD_COL].offset) {
trans_cfg.reg_idx = 135;
trans_cfg.offset = info[RCB_TRANSD_COL].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_INTER_COL].offset) {
trans_cfg.reg_idx = 138;
trans_cfg.offset = info[RCB_INTER_COL].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_FILT_COL].offset) {
trans_cfg.reg_idx = 142;
trans_cfg.offset = info[RCB_FILT_COL].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_DBLK_ROW].offset)
mpp_dev_set_reg_offset(dev, 139, info[RCB_DBLK_ROW].offset);
if (info[RCB_INTRA_ROW].offset)
mpp_dev_set_reg_offset(dev, 133, info[RCB_INTRA_ROW].offset);
if (info[RCB_TRANSD_ROW].offset)
mpp_dev_set_reg_offset(dev, 134, info[RCB_TRANSD_ROW].offset);
if (info[RCB_STRMD_ROW].offset)
mpp_dev_set_reg_offset(dev, 136, info[RCB_STRMD_ROW].offset);
if (info[RCB_INTER_ROW].offset)
mpp_dev_set_reg_offset(dev, 137, info[RCB_INTER_ROW].offset);
if (info[RCB_SAO_ROW].offset)
mpp_dev_set_reg_offset(dev, 140, info[RCB_SAO_ROW].offset);
if (info[RCB_FBC_ROW].offset)
mpp_dev_set_reg_offset(dev, 141, info[RCB_FBC_ROW].offset);
if (info[RCB_TRANSD_COL].offset)
mpp_dev_set_reg_offset(dev, 135, info[RCB_TRANSD_COL].offset);
if (info[RCB_INTER_COL].offset)
mpp_dev_set_reg_offset(dev, 138, info[RCB_INTER_COL].offset);
if (info[RCB_FILT_COL].offset)
mpp_dev_set_reg_offset(dev, 142, info[RCB_FILT_COL].offset);
}
static RK_S32 vdpu34x_compare_rcb_size(const void *a, const void *b)

80
mpp/hal/rkdec/vdpu382_com.c
View file

@ -74,7 +74,6 @@ RK_S32 vdpu382_get_rcb_buf_size(Vdpu382RcbInfo *info, RK_S32 width, RK_S32 heigh
void vdpu382_setup_rcb(Vdpu382RegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu382RcbInfo *info)
{
MppDevRegOffsetCfg trans_cfg;
RK_S32 fd = mpp_buffer_get_fd(buf);
reg->reg139_rcb_dblk_base = fd;
@ -88,65 +87,26 @@ void vdpu382_setup_rcb(Vdpu382RegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdp
reg->reg138_rcb_inter_col_base = fd;
reg->reg142_rcb_filter_col_base = fd;
if (info[RCB_DBLK_ROW].offset) {
trans_cfg.reg_idx = 139;
trans_cfg.offset = info[RCB_DBLK_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_INTRA_ROW].offset) {
trans_cfg.reg_idx = 133;
trans_cfg.offset = info[RCB_INTRA_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_TRANSD_ROW].offset) {
trans_cfg.reg_idx = 134;
trans_cfg.offset = info[RCB_TRANSD_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_STRMD_ROW].offset) {
trans_cfg.reg_idx = 136;
trans_cfg.offset = info[RCB_STRMD_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_INTER_ROW].offset) {
trans_cfg.reg_idx = 137;
trans_cfg.offset = info[RCB_INTER_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_SAO_ROW].offset) {
trans_cfg.reg_idx = 140;
trans_cfg.offset = info[RCB_SAO_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_FBC_ROW].offset) {
trans_cfg.reg_idx = 141;
trans_cfg.offset = info[RCB_FBC_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_TRANSD_COL].offset) {
trans_cfg.reg_idx = 135;
trans_cfg.offset = info[RCB_TRANSD_COL].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_INTER_COL].offset) {
trans_cfg.reg_idx = 138;
trans_cfg.offset = info[RCB_INTER_COL].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_FILT_COL].offset) {
trans_cfg.reg_idx = 142;
trans_cfg.offset = info[RCB_FILT_COL].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_DBLK_ROW].offset)
mpp_dev_set_reg_offset(dev, 139, info[RCB_DBLK_ROW].offset);
if (info[RCB_INTRA_ROW].offset)
mpp_dev_set_reg_offset(dev, 133, info[RCB_INTRA_ROW].offset);
if (info[RCB_TRANSD_ROW].offset)
mpp_dev_set_reg_offset(dev, 134, info[RCB_TRANSD_ROW].offset);
if (info[RCB_STRMD_ROW].offset)
mpp_dev_set_reg_offset(dev, 136, info[RCB_STRMD_ROW].offset);
if (info[RCB_INTER_ROW].offset)
mpp_dev_set_reg_offset(dev, 137, info[RCB_INTER_ROW].offset);
if (info[RCB_SAO_ROW].offset)
mpp_dev_set_reg_offset(dev, 140, info[RCB_SAO_ROW].offset);
if (info[RCB_FBC_ROW].offset)
mpp_dev_set_reg_offset(dev, 141, info[RCB_FBC_ROW].offset);
if (info[RCB_TRANSD_COL].offset)
mpp_dev_set_reg_offset(dev, 135, info[RCB_TRANSD_COL].offset);
if (info[RCB_INTER_COL].offset)
mpp_dev_set_reg_offset(dev, 138, info[RCB_INTER_COL].offset);
if (info[RCB_FILT_COL].offset)
mpp_dev_set_reg_offset(dev, 142, info[RCB_FILT_COL].offset);
}
RK_S32 vdpu382_compare_rcb_size(const void *a, const void *b)

8
mpp/hal/rkdec/vdpu383_com.c
View file

@ -64,7 +64,6 @@ RK_S32 vdpu383_get_rcb_buf_size(Vdpu383RcbInfo *info, RK_S32 width, RK_S32 heigh
void vdpu383_setup_rcb(Vdpu383RegCommonAddr *reg, MppDev dev,
MppBuffer buf, Vdpu383RcbInfo *info)
{
MppDevRegOffsetCfg trans_cfg;
RK_U32 i;
reg->reg140_rcb_strmd_row_offset = mpp_buffer_get_fd(buf);
@ -92,11 +91,8 @@ void vdpu383_setup_rcb(Vdpu383RegCommonAddr *reg, MppDev dev,
reg->reg161_rcb_filterd_av1_upscale_tile_col_len = info[RCB_FILTERD_AV1_UP_TILE_COL].size;
for (i = 0; i < RCB_BUF_COUNT; i++) {
if (info[i].offset) {
trans_cfg.reg_idx = info[i].reg_idx;
trans_cfg.offset = info[i].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[i].offset)
mpp_dev_set_reg_offset(dev, info[i].reg_idx, info[i].offset);
}
}

18
mpp/hal/rkenc/common/vepu541_common.c
View file

@ -661,13 +661,8 @@ MPP_RET vepu541_set_osd(Vepu541OsdCfg *cfg)
}
regs->osd_addr[i] = fd;
if (tmp->buf_offset) {
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = VEPU541_OSD_ADDR_IDX_BASE + i;
trans_cfg.offset = tmp->buf_offset;
mpp_dev_ioctl(cfg->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (tmp->buf_offset)
mpp_dev_set_reg_offset(dev, VEPU541_OSD_ADDR_IDX_BASE + i, tmp->buf_offset);
/* There should be enough buffer and offset should be 16B aligned */
if (buf_size < tmp->buf_offset + blk_len ||
@ -867,13 +862,8 @@ MPP_RET vepu540_set_osd(Vepu541OsdCfg *cfg)
}
regs->osd_addr[k] = fd;
if (tmp->buf_offset) {
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = VEPU541_OSD_ADDR_IDX_BASE + k;
trans_cfg.offset = tmp->buf_offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (tmp->buf_offset)
mpp_dev_set_reg_offset(dev, VEPU541_OSD_ADDR_IDX_BASE + k, tmp->buf_offset);
/* There should be enough buffer and offset should be 16B aligned */
if (buf_size < tmp->buf_offset + blk_len ||

30
mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
View file

@ -964,23 +964,10 @@ static void setup_vepu541_io_buf(Vepu541H264eRegSet *regs, MppDev dev,
}
}
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = 71;
trans_cfg.offset = off_in[0];
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
trans_cfg.reg_idx = 72;
trans_cfg.offset = off_in[1];
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
trans_cfg.reg_idx = 83;
trans_cfg.offset = siz_out;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
trans_cfg.reg_idx = 86;
trans_cfg.offset = off_out;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(dev, 71, off_in[0]);
mpp_dev_set_reg_offset(dev, 72, off_in[1]);
mpp_dev_set_reg_offset(dev, 83, siz_out);
mpp_dev_set_reg_offset(dev, 86, off_out);
hal_h264e_dbg_func("leave\n");
}
@ -1144,7 +1131,6 @@ static void setup_vepu541_recn_refr(Vepu541H264eRegSet *regs, MppDev dev,
{
HalBuf *curr = hal_bufs_get_buf(bufs, frms->curr_idx);
HalBuf *refr = hal_bufs_get_buf(bufs, frms->refr_idx);
MppDevRegOffsetCfg trans_cfg;
hal_h264e_dbg_func("enter\n");
@ -1160,9 +1146,7 @@ static void setup_vepu541_recn_refr(Vepu541H264eRegSet *regs, MppDev dev,
regs->reg075.rfpw_b_addr = fd;
regs->reg080.dspw_addr = mpp_buffer_get_fd(buf_thumb);
trans_cfg.reg_idx = 75;
trans_cfg.offset = fbc_hdr_size;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(dev, 75, fbc_hdr_size);
}
if (refr && refr->cnt) {
@ -1177,9 +1161,7 @@ static void setup_vepu541_recn_refr(Vepu541H264eRegSet *regs, MppDev dev,
regs->reg077.rfpr_b_addr = fd;
regs->reg081.dspr_addr = mpp_buffer_get_fd(buf_thumb);
trans_cfg.reg_idx = 77;
trans_cfg.offset = fbc_hdr_size;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(dev, 77, fbc_hdr_size);
}
hal_h264e_dbg_func("leave\n");

9
mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c
View file

@ -615,7 +615,6 @@ static MPP_RET hal_h265e_vepu540c_prepare(void *hal)
static MPP_RET
vepu540c_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, Vepu541Fmt input_fmt, HalEncTask *task)
{
MppDevRegOffsetCfg cfg_fd;
RK_U32 hor_stride = syn->pp.hor_stride;
RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
RK_U32 frame_size = hor_stride * ver_stride;
@ -664,18 +663,14 @@ vepu540c_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, Vepu541Fmt input_
/* input cb addr */
if (u_offset) {
cfg_fd.reg_idx = 161;
cfg_fd.offset = u_offset;
ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
ret = mpp_dev_set_reg_offset(dev, 161, u_offset);
if (ret)
mpp_err_f("set input cb addr offset failed %d\n", ret);
}
/* input cr addr */
if (v_offset) {
cfg_fd.reg_idx = 162;
cfg_fd.offset = v_offset;
ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
ret = mpp_dev_set_reg_offset(dev, 162, v_offset);
if (ret)
mpp_err_f("set input cr addr offset failed %d\n", ret);
}

41
mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
View file

@ -730,7 +730,6 @@ static MPP_RET hal_h265e_vepu54x_prepare(void *hal)
static MPP_RET
vepu541_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, Vepu541Fmt input_fmt, HalEncTask *task)
{
MppDevRegOffsetCfg cfg_fd;
RK_U32 hor_stride = syn->pp.hor_stride;
RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
RK_U32 frame_size = hor_stride * ver_stride;
@ -776,25 +775,19 @@ vepu541_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, Vepu541Fmt input_f
/* input cb addr */
if (u_offset) {
cfg_fd.reg_idx = 71;
cfg_fd.offset = u_offset;
ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
mpp_dev_set_reg_offset(dev, 71, u_offset);
if (ret)
mpp_err_f("set input cb addr offset failed %d\n", ret);
}
/* input cr addr */
if (v_offset) {
cfg_fd.reg_idx = 72;
cfg_fd.offset = v_offset;
ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
mpp_dev_set_reg_offset(dev, 72, v_offset);
if (ret)
mpp_err_f("set input cr addr offset failed %d\n", ret);
}
cfg_fd.reg_idx = 83;
cfg_fd.offset = mpp_buffer_get_size(task->output);
ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
mpp_dev_set_reg_offset(dev, 83, mpp_buffer_get_size(task->output));
if (ret)
mpp_err_f("set output max addr offset failed %d\n", ret);
@ -1398,7 +1391,6 @@ void vepu54x_h265_set_hw_address(H265eV541HalContext *ctx, H265eV541RegSet *regs
HalBuf *recon_buf, *ref_buf;
MppBuffer md_info_buf = enc_task->md_info;
H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
MppDevRegOffsetCfg cfg_fd;
hal_h265e_enter();
@ -1412,9 +1404,7 @@ void vepu54x_h265_set_hw_address(H265eV541HalContext *ctx, H265eV541RegSet *regs
regs->rfpw_h_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[0]);
regs->rfpw_b_addr_hevc = regs->rfpw_h_addr_hevc;
cfg_fd.reg_idx = 75;
cfg_fd.offset = ctx->fbc_header_len;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
mpp_dev_set_reg_offset(ctx->dev, 75, ctx->fbc_header_len);
}
regs->dspw_addr_hevc = mpp_buffer_get_fd(recon_buf->buf[1]);
@ -1424,9 +1414,7 @@ void vepu54x_h265_set_hw_address(H265eV541HalContext *ctx, H265eV541RegSet *regs
regs->dspr_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[1]);
regs->cmvr_addr_hevc = mpp_buffer_get_fd(ref_buf->buf[2]);
cfg_fd.reg_idx = 77;
cfg_fd.offset = ctx->fbc_header_len;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
mpp_dev_set_reg_offset(ctx->dev, 77, ctx->fbc_header_len);
if (syn->pp.tiles_enabled_flag) {
if (NULL == ctx->tile_grp)
@ -1460,9 +1448,7 @@ void vepu54x_h265_set_hw_address(H265eV541HalContext *ctx, H265eV541RegSet *regs
regs->bsbr_addr_hevc = regs->bsbb_addr_hevc;
regs->bsbw_addr_hevc = regs->bsbb_addr_hevc;
cfg_fd.reg_idx = 86;
cfg_fd.offset = mpp_packet_get_length(task->packet);
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
mpp_dev_set_reg_offset(ctx->dev, 86, mpp_packet_get_length(task->packet));
regs->pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
regs->pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
@ -1723,23 +1709,14 @@ MPP_RET hal_h265e_v540_start(void *hal, HalEncTask *enc_task)
if (title_num > 1)
hal_h265e_v540_set_uniform_tile(hw_regs, syn, k, tile_start_x);
if (k > 0) {
MppDevRegOffsetCfg cfg_fd;
RK_U32 offset = mpp_packet_get_length(enc_task->packet);
offset += stream_len;
hw_regs->bsbb_addr_hevc = mpp_buffer_get_fd(enc_task->output);
hw_regs->bsbw_addr_hevc = hw_regs->bsbb_addr_hevc;
cfg_fd.reg_idx = 86;
cfg_fd.offset = offset;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
cfg_fd.reg_idx = 75;
cfg_fd.offset = ctx->fbc_header_len;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
cfg_fd.reg_idx = 77;
cfg_fd.offset = ctx->fbc_header_len;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &cfg_fd);
mpp_dev_set_reg_offset(ctx->dev, 86, offset);
mpp_dev_set_reg_offset(ctx->dev, 75, ctx->fbc_header_len);
mpp_dev_set_reg_offset(ctx->dev, 77, ctx->fbc_header_len);
}
cfg.reg = ctx->regs;

20
mpp/hal/rkenc/jpege/hal_jpege_vpu720.c
View file

@ -499,22 +499,10 @@ MPP_RET hal_jpege_vpu720_gen_regs(void *hal, HalEncTask *task)
memcpy(qtbl_base, ctx->qtbl_sw_buf, JPEGE_VPU720_QTABLE_SIZE * sizeof(RK_U16));
mpp_buffer_sync_end(ctx->qtbl_buffer);
MppDevRegOffsetCfg trans_cfg_offset;
MppDevRegOffsetCfg trans_cfg_size;
MppDevRegOffsetCfg trans_cfg_chroma;
trans_cfg_offset.reg_idx = 20;
trans_cfg_offset.offset = mpp_packet_get_length(task->packet);
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg_offset);
trans_cfg_size.reg_idx = 17;
trans_cfg_size.offset = mpp_buffer_get_size(task->output);
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, & trans_cfg_size);
trans_cfg_chroma.reg_idx = 23;
trans_cfg_chroma.offset = ctx->fmt_cfg.u_offset;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg_chroma);
trans_cfg_chroma.reg_idx = 24;
trans_cfg_chroma.offset = ctx->fmt_cfg.v_offset;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg_chroma);
mpp_dev_set_reg_offset(ctx->dev, 20, mpp_packet_get_length(task->packet));
mpp_dev_set_reg_offset(ctx->dev, 17, mpp_buffer_get_size(task->output));
mpp_dev_set_reg_offset(ctx->dev, 23, ctx->fmt_cfg.u_offset);
mpp_dev_set_reg_offset(ctx->dev, 24, ctx->fmt_cfg.v_offset);
ctx->frame_num++;

18
mpp/hal/vpu/jpegd/hal_jpegd_rkv.c
View file

@ -545,21 +545,9 @@ static MPP_RET jpegd_gen_regs(JpegdHalCtx *ctx, JpegdSyntax *syntax)
regs->reg13_dec_out_base = ctx->frame_fd;
regs->reg12_strm_base = ctx->pkt_fd;
MppDevRegOffsetCfg trans_cfg_10;
MppDevRegOffsetCfg trans_cfg_11;
MppDevRegOffsetCfg trans_cfg_12;
trans_cfg_12.reg_idx = 12;
trans_cfg_12.offset = hw_strm_offset;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg_12);
trans_cfg_10.reg_idx = 10;
trans_cfg_10.offset = RKD_HUFFMAN_MINCODE_TBL_OFFSET;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg_10);
trans_cfg_11.reg_idx = 11;
trans_cfg_11.offset = RKD_HUFFMAN_VALUE_TBL_OFFSET;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg_11);
mpp_dev_set_reg_offset(ctx->dev, 12, hw_strm_offset);
mpp_dev_set_reg_offset(ctx->dev, 10, RKD_HUFFMAN_MINCODE_TBL_OFFSET);
mpp_dev_set_reg_offset(ctx->dev, 11, RKD_HUFFMAN_VALUE_TBL_OFFSET);
regs->reg14_strm_error.error_prc_mode = 1;
regs->reg14_strm_error.strm_ffff_err_mode = 2;

17
mpp/hal/vpu/jpege/hal_jpege_vepu1_v2.c
View file

@ -147,7 +147,6 @@ static MPP_RET hal_jpege_vepu1_set_extra_info(MppDev dev, JpegeSyntax *syntax,
RK_U32 hor_stride = syntax->hor_stride;
RK_U32 ver_stride = syntax->ver_stride;
RK_U32 offset = 0;
MppDevRegOffsetCfg trans_cfg;
switch (fmt) {
case MPP_FMT_YUV420SP :
@ -155,33 +154,25 @@ static MPP_RET hal_jpege_vepu1_set_extra_info(MppDev dev, JpegeSyntax *syntax,
if (start_mbrow) {
offset = 16 * start_mbrow * hor_stride;
trans_cfg.reg_idx = 11;
trans_cfg.offset = offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(dev, 11, offset);
}
offset = hor_stride * ver_stride + hor_stride * start_mbrow * 16 / 2;
if (fmt == MPP_FMT_YUV420P)
offset = hor_stride * start_mbrow * 16 / 4 + hor_stride * ver_stride;
trans_cfg.reg_idx = 12;
trans_cfg.offset = offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(dev, 12, offset);
if (fmt == MPP_FMT_YUV420P)
offset = hor_stride * start_mbrow * 16 / 4 + hor_stride * ver_stride * 5 / 4;
trans_cfg.reg_idx = 13;
trans_cfg.offset = offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(dev, 13, offset);
} break;
default : {
if (start_mbrow) {
offset = start_mbrow * hor_stride;
trans_cfg.reg_idx = 11;
trans_cfg.offset = offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(dev, 11, offset);
}
} break;
}

25
mpp/hal/vpu/jpege/hal_jpege_vepu2_v2.c
View file

@ -348,7 +348,6 @@ static MPP_RET hal_jpege_vepu2_set_extra_info(MppDev dev, JpegeSyntax *syntax,
RK_U32 start_mbrow)
{
VepuOffsetCfg cfg;
MppDevRegOffsetCfg trans_cfg;
cfg.fmt = syntax->format;
cfg.width = syntax->width;
@ -360,26 +359,14 @@ static MPP_RET hal_jpege_vepu2_set_extra_info(MppDev dev, JpegeSyntax *syntax,
get_vepu_offset_cfg(&cfg);
if (cfg.offset_byte[0]) {
trans_cfg.reg_idx = VEPU2_REG_INPUT_Y;
trans_cfg.offset = cfg.offset_byte[0];
if (cfg.offset_byte[0])
mpp_dev_set_reg_offset(dev, VEPU2_REG_INPUT_Y, cfg.offset_byte[0]);
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (cfg.offset_byte[1])
mpp_dev_set_reg_offset(dev, VEPU2_REG_INPUT_U, cfg.offset_byte[1]);
if (cfg.offset_byte[1]) {
trans_cfg.reg_idx = VEPU2_REG_INPUT_U;
trans_cfg.offset = cfg.offset_byte[1];
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (cfg.offset_byte[2]) {
trans_cfg.reg_idx = VEPU2_REG_INPUT_V;
trans_cfg.offset = cfg.offset_byte[2];
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (cfg.offset_byte[2])
mpp_dev_set_reg_offset(dev, VEPU2_REG_INPUT_V, cfg.offset_byte[2]);
return MPP_OK;
}

56
mpp/hal/vpu/vp8d/hal_vp8d_vdpu2.c
View file

@ -266,13 +266,8 @@ static MPP_RET hal_vp8d_dct_partition_cfg(VP8DHalContext_t *ctx,
mpp_buf_slot_get_prop(ctx->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);
fd = mpp_buffer_get_fd(streambuf);
regs->reg145_bitpl_ctrl_base = fd;
if (pic_param->stream_start_offset) {
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = 145;
trans_cfg.offset = pic_param->stream_start_offset;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (pic_param->stream_start_offset)
mpp_dev_set_reg_offset(ctx->dev, 145, pic_param->stream_start_offset);
regs->reg122.sw_strm1_start_bit = pic_param->stream_start_bit;
@ -294,33 +289,22 @@ static MPP_RET hal_vp8d_dct_partition_cfg(VP8DHalContext_t *ctx,
regs->reg124.sw_coeffs_part_am =
(1 << pic_param->log2_nbr_of_dct_partitions) - 1;
for (i = 0; i < (RK_U32)(1 << pic_param->log2_nbr_of_dct_partitions); i++) {
MppDevRegOffsetCfg trans_cfg;
addr = extraBytesPacked + pic_param->dctPartitionOffsets[i];
byte_offset = addr & 0x7;
addr = addr & 0xFFFFFFF8;
if (i == 0) {
regs->reg64_input_stream_base = fd;
if (addr) {
trans_cfg.reg_idx = 64;
trans_cfg.offset = addr;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (addr)
mpp_dev_set_reg_offset(ctx->dev, 64, addr);
} else if (i <= 5) {
regs->reg_dct_strm_base[i - 1] = fd;
if (addr) {
trans_cfg.reg_idx = 139 + i;
trans_cfg.offset = addr;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (addr)
mpp_dev_set_reg_offset(ctx->dev, 139 + i, addr);
} else {
regs->reg_dct_strm1_base[i - 6] = fd;
if (addr) {
trans_cfg.reg_idx = 140 + i;
trans_cfg.offset = addr;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (addr)
mpp_dev_set_reg_offset(ctx->dev, 140 + i, addr);
}
switch (i) {
@ -461,7 +445,6 @@ MPP_RET hal_vp8d_vdpu2_gen_regs(void* hal, HalTaskInfo *task)
MppBuffer framebuf = NULL;
RK_U8 *segmap_ptr = NULL;
RK_U8 *probe_ptr = NULL;
MppDevRegOffsetCfg trans_cfg;
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
VP8DRegSet_t *regs = (VP8DRegSet_t *)ctx->regs;
DXVA_PicParams_VP8 *pic_param = (DXVA_PicParams_VP8 *)task->dec.syntax.data;
@ -494,9 +477,7 @@ MPP_RET hal_vp8d_vdpu2_gen_regs(void* hal, HalTaskInfo *task)
regs->reg131_ref0_base = regs->reg63_cur_pic_base;
trans_cfg.reg_idx = 131;
trans_cfg.offset = mb_width * mb_height;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(ctx->dev, 131, mb_width * mb_height);
} else if (pic_param->lst_fb_idx.Index7Bits < 0x7f) { //config ref0 base
mpp_buf_slot_get_prop(ctx->frame_slots, pic_param->lst_fb_idx.Index7Bits, SLOT_BUFFER, &framebuf);
regs->reg131_ref0_base = mpp_buffer_get_fd(framebuf);
@ -514,9 +495,7 @@ MPP_RET hal_vp8d_vdpu2_gen_regs(void* hal, HalTaskInfo *task)
regs->reg136_golden_ref_base = regs->reg136_golden_ref_base;
if (pic_param->ref_frame_sign_bias_golden) {
trans_cfg.reg_idx = 136;
trans_cfg.offset = pic_param->ref_frame_sign_bias_golden;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
mpp_dev_set_reg_offset(ctx->dev, 136, pic_param->ref_frame_sign_bias_golden);
}
/* alternate reference */
@ -528,18 +507,13 @@ MPP_RET hal_vp8d_vdpu2_gen_regs(void* hal, HalTaskInfo *task)
}
regs->reg137.alternate_ref_base = regs->reg137.alternate_ref_base;
if (pic_param->ref_frame_sign_bias_altref) {
trans_cfg.reg_idx = 137;
trans_cfg.offset = pic_param->ref_frame_sign_bias_altref;
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (pic_param->ref_frame_sign_bias_altref)
mpp_dev_set_reg_offset(ctx->dev, 137, pic_param->ref_frame_sign_bias_altref);
regs->reg149_segment_map_base = regs->reg149_segment_map_base;
if (pic_param->stVP8Segments.segmentation_enabled + (pic_param->stVP8Segments.update_mb_segmentation_map << 1)) {
trans_cfg.reg_idx = 149;
trans_cfg.offset = pic_param->stVP8Segments.segmentation_enabled + (pic_param->stVP8Segments.update_mb_segmentation_map << 1);
mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (pic_param->stVP8Segments.segmentation_enabled + (pic_param->stVP8Segments.update_mb_segmentation_map << 1))
mpp_dev_set_reg_offset(ctx->dev, 149, pic_param->stVP8Segments.segmentation_enabled
+ (pic_param->stVP8Segments.update_mb_segmentation_map << 1));
regs->reg57_enable_ctrl.sw_pic_inter_e = pic_param->frame_type;
regs->reg50_dec_ctrl.sw_skip_mode = !pic_param->mb_no_coeff_skip;