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fix[vepu_540c]: Reduce print hw_status when irq ret

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Change-Id: I2a0f48bb21fd31513e7e9a1f390dde1d0ec5f720
Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
This commit is contained in:
Yanjun Liao 2025-05-16 11:24:36 +08:00
parent 161345e67f
commit 6fc495af49
5 changed files with 58 additions and 48 deletions
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24
mpp/hal/rkenc/common/vepu540c_common.h
View file

@ -36,6 +36,30 @@
#define VEPU540C_MAX_ROI_NUM 8
#define VEPU540C_SLICE_FIFO_LEN 8
typedef union {
struct {
RK_U32 enc_done_sta : 1;
RK_U32 lkt_node_done_sta : 1;
RK_U32 sclr_done_sta : 1;
RK_U32 vslc_done_sta : 1;
RK_U32 vbsf_oflw_sta : 1;
RK_U32 vbuf_lens_sta : 1;
RK_U32 enc_err_sta : 1;
RK_U32 dvbm_fcfg_sta : 1;
RK_U32 wdg_sta : 1;
RK_U32 lkt_err_int_sta : 1;
RK_U32 lkt_err_stop_sta : 1;
RK_U32 lkt_force_stop_sta : 1;
RK_U32 jslc_done_sta : 1;
RK_U32 jbsf_oflw_sta : 1;
RK_U32 jbuf_lens_sta : 1;
RK_U32 dvbm_dcnt_sta : 1;
RK_U32 reserved : 16;
} int_sta;
RK_U32 val;
} vepu540c_hw_status;
typedef struct Vepu540cOnline_t {
/* 0x00000270 reg156 */
RK_U32 reg0156_adr_vsy_t;

44
mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c
View file

@ -47,7 +47,7 @@
} while (0)
typedef struct vepu540c_h265_fbk_t {
RK_U32 hw_status; /* 0:corret, 1:error */
vepu540c_hw_status hw_status;
RK_U32 qp_sum;
RK_U32 out_strm_size;
RK_U32 out_hw_strm_size;
@ -1475,7 +1475,7 @@ static MPP_RET vepu540c_h265_set_feedback(H265eV540cHalContext *ctx, HalEncTask
RK_S32 mb8_num = (mb64_num << 6);
RK_S32 mb4_num = (mb8_num << 2);
H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out[0];
RK_U32 hw_status = elem->hw_status;
vepu540c_hw_status hw_status = elem->hw_status;
hal_h265e_enter();
@ -1487,33 +1487,33 @@ static MPP_RET vepu540c_h265_set_feedback(H265eV540cHalContext *ctx, HalEncTask
(elem->st.st_sse_bsl.sse_l16 & 0xffff) ;
fb->hw_status = hw_status;
hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH");
hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status.val);
if (hw_status.int_sta.enc_done_sta)
hal_h265e_dbg_detail("RKV_ENC_INT_ENC_DONE");
if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
if (hw_status.int_sta.lkt_node_done_sta)
hal_h265e_dbg_detail("RKV_ENC_INT_LKT_NODE_DONE");
if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
hal_h265e_err("RKV_ENC_INT_ONE_SLICE_FINISH");
if (hw_status.int_sta.sclr_done_sta)
hal_h265e_dbg_detail("RKV_ENC_INT_SCLR_DONE");
if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH");
if (hw_status.int_sta.vslc_done_sta)
hal_h265e_dbg_detail("RKV_ENC_INT_VSLC_DONE");
if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
if (hw_status.int_sta.vbsf_oflw_sta)
hal_h265e_err("RKV_ENC_INT_VBSF_OFLOW");
if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
if (hw_status.int_sta.vbuf_lens_sta)
hal_h265e_err("RKV_ENC_INT_VBUF_LENS");
if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
if (hw_status.int_sta.enc_err_sta)
hal_h265e_err("RKV_ENC_INT_ENC_ERR");
if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
if (hw_status.int_sta.dvbm_fcfg_sta)
hal_h265e_err("RKV_ENC_INT_DVBM_FCFG");
if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
if (hw_status.int_sta.wdg_sta)
hal_h265e_err("RKV_ENC_INT_WDG_TIMEOUT");
// fb->st_madi += elem->st.madi;
//fb->st_madp += elem->st.madp;
@ -1640,7 +1640,7 @@ MPP_RET hal_h265e_v540c_wait(void *hal, HalEncTask *task)
frm_num++;
#endif
if (ret)
mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);
mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status.val);
hal_h265e_leave();
return ret;

2
mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h
View file

@ -1078,7 +1078,7 @@ typedef struct H265eV540cRegSet_t {
} H265eV540cRegSet;
typedef struct H265eV540cStatusElem_t {
RK_U32 hw_status;
vepu540c_hw_status hw_status;
vepu540c_status st;
} H265eV540cStatusElem;

34
mpp/hal/rkenc/jpege/hal_jpege_vepu540c.c
View file

@ -307,35 +307,21 @@ static MPP_RET hal_jpege_vepu540c_status_check(void *hal)
jpegeV540cHalContext *ctx = (jpegeV540cHalContext *)hal;
JpegV540cStatus *elem = (JpegV540cStatus *)ctx->reg_out;
RK_U32 hw_status = elem->hw_status;
vepu540c_hw_status hw_status = elem->hw_status;
mpp_err_f("hw_status: 0x%08x", hw_status);
if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
mpp_err_f("RKV_ENC_INT_LINKTABLE_FINISH");
hal_jpege_dbg_detail("hw_status: 0x%08x", hw_status.val);
if (hw_status.int_sta.enc_done_sta)
hal_jpege_dbg_detail("RKV_ENC_INT_ENC_DONE");
if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
mpp_err_f("RKV_ENC_INT_ONE_FRAME_FINISH");
if (hw_status.int_sta.wdg_sta)
mpp_err_f("RKV_ENC_INT_WDG_TIMEOUT");
if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
mpp_err_f("RKV_ENC_INT_ONE_SLICE_FINISH");
if (hw_status.int_sta.jslc_done_sta)
hal_jpege_dbg_detail("RKV_ENC_INT_JSL_DONE");
if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
mpp_err_f("RKV_ENC_INT_SAFE_CLEAR_FINISH");
if (hw_status.int_sta.jbsf_oflw_sta)
mpp_err_f("RKV_ENC_INT_JBSF_OFLOW");
if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
mpp_err_f("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
mpp_err_f("RKV_ENC_INT_BUS_WRITE_FULL");
if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
mpp_err_f("RKV_ENC_INT_BUS_WRITE_ERROR");
if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
mpp_err_f("RKV_ENC_INT_BUS_READ_ERROR");
if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
mpp_err_f("RKV_ENC_INT_TIMEOUT_ERROR");
return MPP_OK;
}

2
mpp/hal/rkenc/jpege/hal_jpege_vepu540c_reg.h
View file

@ -851,7 +851,7 @@ typedef struct JpegV540cRegSet_t {
} JpegV540cRegSet;
typedef struct JpegV540cStatus_t {
RK_U32 hw_status;
vepu540c_hw_status hw_status;
vepu540c_status st;
} JpegV540cStatus;