diff --git a/mpp/hal/rkenc/common/vepu510_common.h b/mpp/hal/rkenc/common/vepu510_common.h index 6173f820..335802ec 100644 --- a/mpp/hal/rkenc/common/vepu510_common.h +++ b/mpp/hal/rkenc/common/vepu510_common.h @@ -12,10 +12,10 @@ #define VEPU510_FRAME_OFFSET (156 * sizeof(RK_U32)) /* 0x00000270 reg156 - 0x000003f4 reg253 */ #define VEPU510_RC_ROI_OFFSET (1024 * sizeof(RK_U32)) /* 0x00001000 reg1024 - 0x0000110c reg1091 */ #define VEPU510_PARAM_OFFSET (1472 * sizeof(RK_U32)) /* 0x00001700 reg1472 - 0x000019cc reg1651 */ -#define VEPU510_SQI_OFFSET (2048 * sizeof(RK_U32)) /* 0x00002000 reg2048 - 0x000020fc reg2111 */ +#define VEPU510_SQI_OFFSET (2048 * sizeof(RK_U32)) /* 0x00002000 reg2048 - 0x0000212c reg2123 */ #define VEPU510_SCL_OFFSET (2176 * sizeof(RK_U32)) /* 0x00002200 reg2176 - 0x00002584 reg2401 */ #define VEPU510_STATUS_OFFSET (4096 * sizeof(RK_U32)) /* 0x00004000 reg4096 - 0x0000424c reg4243 */ -#define VEPU510_DBG_OFFSET (5120 * sizeof(RK_U32)) /* 0x00005000 reg5120 - 0x00005354 reg5333 */ +#define VEPU510_DBG_OFFSET (5120 * sizeof(RK_U32)) /* 0x00005000 reg5120 - 0x00005230 reg5260 */ #define VEPU510_REG_BASE_HW_STATUS (0x2c) #define VEPU510_MAX_ROI_NUM 8 @@ -45,46 +45,6 @@ typedef struct Vepu510Online_t { } adr_vsc_b; } vepu510_online; -typedef struct PreCstPar_t { - struct { - RK_U32 madi_thd0 : 8; - RK_U32 madi_thd1 : 8; - RK_U32 madi_thd2 : 8; - RK_U32 madi_thd3 : 8; - } cst_madi_thd0; - - /* 0x000020c4 reg2097 */ - struct { - RK_U32 madi_thd4 : 8; - RK_U32 madi_thd5 : 8; - RK_U32 reserved : 16; - } cst_madi_thd1; - - /* 0x000020c8 reg2098 */ - struct { - RK_U32 wgt0 : 8; - RK_U32 wgt1 : 8; - RK_U32 wgt2 : 8; - RK_U32 wgt3 : 8; - } cst_wgt0; - - /* 0x000020cc reg2099 */ - struct { - RK_U32 wgt4 : 8; - RK_U32 wgt5 : 8; - RK_U32 wgt6 : 8; - RK_U32 wgt7 : 8; - } cst_wgt1; - - /* 0x000020d0 reg2100 */ - struct { - RK_U32 wgt8 : 8; - RK_U32 wgt9 : 8; - RK_U32 mode_th : 3; - RK_U32 reserved : 13; - } cst_wgt2; -} pre_cst_par; - typedef struct RdoSkipPar_t { struct { RK_U32 madp_thd0 : 12; @@ -127,8 +87,10 @@ typedef struct RdoNoSkipPar_t { /* 0x00002084 reg2081 */ struct { - RK_U32 madp_thd2 : 12; - RK_U32 reserved : 20; + RK_U32 madp_thd2 : 12; + RK_U32 reserved : 4; + RK_U32 atf_bypass_pri_flag : 1; + RK_U32 reserved1 : 15; } ratf_thd1; /* 0x00002088 reg2082 */ @@ -140,436 +102,7 @@ typedef struct RdoNoSkipPar_t { } atf_wgt; } rdo_noskip_par; -/* class: rdo/q_i */ -/* 0x00002000 reg2048 - 0x000020fc reg2111 */ -typedef struct Vepu510SqiCfg_t { - - /* 0x2000 - 0x200c */ - RK_U32 reserved2048_2051[4]; - - /* 0x00002010 reg2052 */ - struct { - RK_U32 rdo_segment_multi : 8; - RK_U32 rdo_segment_en : 1; - RK_U32 reserved : 7; - RK_U32 rdo_smear_lvl4_multi : 8; - RK_U32 rdo_smear_lvl8_multi : 8; - } rdo_segment_cfg; - - /* 0x00002014 reg2053 */ - struct { - RK_U32 rdo_smear_lvl16_multi : 8; - RK_U32 rdo_smear_dlt_qp : 4; - RK_U32 rdo_smear_order_state : 1; - RK_U32 stated_mode : 2; - RK_U32 rdo_smear_en : 1; - RK_U32 online_en : 1; - RK_U32 reserved : 3; - RK_U32 smear_stride : 12; - } rdo_smear_cfg_comb; - - /* 0x00002018 reg2054 */ - struct { - RK_U32 rdo_smear_madp_cur_thd0 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_cur_thd1 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd0_comb; - - /* 0x0000201c reg2055 */ - struct { - RK_U32 rdo_smear_madp_cur_thd2 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_cur_thd3 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd1_comb; - - /* 0x00002020 reg2056 */ - struct { - RK_U32 rdo_smear_madp_around_thd0 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_around_thd1 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd2_comb; - - /* 0x00002024 reg2057 */ - struct { - RK_U32 rdo_smear_madp_around_thd2 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_around_thd3 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd3_comb; - - /* 0x00002028 reg2058 */ - struct { - RK_U32 rdo_smear_madp_around_thd4 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_around_thd5 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd4_comb; - - /* 0x0000202c reg2059 */ - struct { - RK_U32 rdo_smear_madp_ref_thd0 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_ref_thd1 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd5_comb; - - /* 0x00002030 reg2060 */ - struct { - RK_U32 rdo_smear_cnt_cur_thd0 : 4; - RK_U32 reserved : 4; - RK_U32 rdo_smear_cnt_cur_thd1 : 4; - RK_U32 reserved1 : 4; - RK_U32 rdo_smear_cnt_cur_thd2 : 4; - RK_U32 reserved2 : 4; - RK_U32 rdo_smear_cnt_cur_thd3 : 4; - RK_U32 reserved3 : 4; - } rdo_smear_cnt_thd0_comb; - - /* 0x00002034 reg2061 */ - struct { - RK_U32 rdo_smear_cnt_around_thd0 : 4; - RK_U32 reserved : 4; - RK_U32 rdo_smear_cnt_around_thd1 : 4; - RK_U32 reserved1 : 4; - RK_U32 rdo_smear_cnt_around_thd2 : 4; - RK_U32 reserved2 : 4; - RK_U32 rdo_smear_cnt_around_thd3 : 4; - RK_U32 reserved3 : 4; - } rdo_smear_cnt_thd1_comb; - - /* 0x00002038 reg2062 */ - struct { - RK_U32 rdo_smear_cnt_around_thd4 : 4; - RK_U32 reserved : 4; - RK_U32 rdo_smear_cnt_around_thd5 : 4; - RK_U32 reserved1 : 4; - RK_U32 rdo_smear_cnt_around_thd6 : 4; - RK_U32 reserved2 : 4; - RK_U32 rdo_smear_cnt_around_thd7 : 4; - RK_U32 reserved3 : 4; - } rdo_smear_cnt_thd2_comb; - - /* 0x0000203c reg2063 */ - struct { - RK_U32 rdo_smear_cnt_ref_thd0 : 4; - RK_U32 reserved : 4; - RK_U32 rdo_smear_cnt_ref_thd1 : 4; - RK_U32 reserved1 : 20; - } rdo_smear_cnt_thd3_comb; - - /* 0x00002040 reg2064 */ - struct { - RK_U32 rdo_smear_resi_small_cur_th0 : 6; - RK_U32 reserved : 2; - RK_U32 rdo_smear_resi_big_cur_th0 : 6; - RK_U32 reserved1 : 2; - RK_U32 rdo_smear_resi_small_cur_th1 : 6; - RK_U32 reserved2 : 2; - RK_U32 rdo_smear_resi_big_cur_th1 : 6; - RK_U32 reserved3 : 2; - } rdo_smear_resi_thd0_comb; - - /* 0x00002044 reg2065 */ - struct { - RK_U32 rdo_smear_resi_small_around_th0 : 6; - RK_U32 reserved : 2; - RK_U32 rdo_smear_resi_big_around_th0 : 6; - RK_U32 reserved1 : 2; - RK_U32 rdo_smear_resi_small_around_th1 : 6; - RK_U32 reserved2 : 2; - RK_U32 rdo_smear_resi_big_around_th1 : 6; - RK_U32 reserved3 : 2; - } rdo_smear_resi_thd1_comb; - - /* 0x00002048 reg2066 */ - struct { - RK_U32 rdo_smear_resi_small_around_th2 : 6; - RK_U32 reserved : 2; - RK_U32 rdo_smear_resi_big_around_th2 : 6; - RK_U32 reserved1 : 2; - RK_U32 rdo_smear_resi_small_around_th3 : 6; - RK_U32 reserved2 : 2; - RK_U32 rdo_smear_resi_big_around_th3 : 6; - RK_U32 reserved3 : 2; - } rdo_smear_resi_thd2_comb; - - /* 0x0000204c reg2067 */ - struct { - RK_U32 rdo_smear_resi_small_ref_th0 : 6; - RK_U32 reserved : 2; - RK_U32 rdo_smear_resi_big_ref_th0 : 6; - RK_U32 reserved1 : 18; - } rdo_smear_resi_thd3_comb; - - /* 0x00002050 reg2068 */ - struct { - RK_U32 rdo_smear_resi_th0 : 8; - RK_U32 reserved : 8; - RK_U32 rdo_smear_resi_th1 : 8; - RK_U32 reserved1 : 8; - } rdo_smear_st_thd0_comb; - - /* 0x00002054 reg2069 */ - struct { - RK_U32 rdo_smear_madp_cnt_th0 : 4; - RK_U32 rdo_smear_madp_cnt_th1 : 4; - RK_U32 rdo_smear_madp_cnt_th2 : 4; - RK_U32 rdo_smear_madp_cnt_th3 : 4; - RK_U32 rdo_smear_madp_cnt_th4 : 4; - RK_U32 rdo_smear_madp_cnt_th5 : 4; - RK_U32 reserved : 8; - } rdo_smear_st_thd1_comb; - - /* 0x2058 - 0x205c */ - RK_U32 reserved2070_2071[2]; - - /* 0x00002060 reg2072 - 0x0000206c reg2075 */ - rdo_skip_par rdo_b32_skip; - - /* 0x00002070 reg2076 - 0x0000207c reg2079*/ - rdo_skip_par rdo_b16_skip; - - /* 0x00002080 reg2080 - 0x00002088 reg2082 */ - rdo_noskip_par rdo_b32_inter; - - /* 0x0000208c reg2083 - 0x00002094 reg2085 */ - rdo_noskip_par rdo_b16_inter; - - /* 0x00002098 reg2086 - 0x000020a4 reg2088 */ - rdo_noskip_par rdo_b32_intra; - - /* 0x000020a8 reg2089 - 0x000020ac reg2091 */ - rdo_noskip_par rdo_b16_intra; - - /* 0x000020b0 reg2092 */ - struct { - RK_U32 thd0 : 6; - RK_U32 reserved : 2; - RK_U32 thd1 : 6; - RK_U32 reserved1 : 2; - RK_U32 thd2 : 6; - RK_U32 reserved2 : 2; - RK_U32 thd3 : 6; - RK_U32 reserved3 : 2; - } rdo_b32_intra_atf_cnt_thd; - - /* 0x000020b4 reg2093 */ - struct { - RK_U32 thd0 : 4; - RK_U32 reserved : 4; - RK_U32 thd1 : 4; - RK_U32 reserved1 : 4; - RK_U32 thd2 : 4; - RK_U32 reserved2 : 4; - RK_U32 thd3 : 4; - RK_U32 reserved3 : 4; - } rdo_b16_intra_atf_cnt_thd_comb; - - /* 0x000020b8 reg2094 */ - struct { - RK_U32 big_th0 : 6; - RK_U32 reserved : 2; - RK_U32 big_th1 : 6; - RK_U32 reserved1 : 2; - RK_U32 small_th0 : 6; - RK_U32 reserved2 : 2; - RK_U32 small_th1 : 6; - RK_U32 reserved3 : 2; - } rdo_atf_resi_thd_comb; - - /* 0x20bc */ - RK_U32 reserved_2095; - - /* 0x000020c0 reg2096 - 0x000020d0 reg2100 */ - pre_cst_par preintra32_cst; - - /* 0x000020d4 reg2101 - 0x000020e4 reg2105 */ - pre_cst_par preintra16_cst; - - /* 0x20e8 - 0x20ec */ - RK_U32 reserved2106_2107[2]; - - /* 0x000020f0 reg2108 */ - struct { - RK_U32 pre_intra_qp_thd : 6; - RK_U32 reserved : 2; - RK_U32 pre_intra4_lambda_mv_bit : 3; - RK_U32 reserved1 : 1; - RK_U32 pre_intra8_lambda_mv_bit : 3; - RK_U32 reserved2 : 1; - RK_U32 pre_intra16_lambda_mv_bit : 3; - RK_U32 reserved3 : 1; - RK_U32 pre_intra32_lambda_mv_bit : 3; - RK_U32 reserved4 : 9; - } preintra_sqi_cfg; - - /* 0x000020f4 reg2109 */ - struct { - RK_U32 i_cu32_madi_thd0 : 8; - RK_U32 i_cu32_madi_thd1 : 8; - RK_U32 i_cu32_madi_thd2 : 8; - RK_U32 reserved : 8; - } rdo_atr_i_cu32_madi_cfg0; - - /* 0x000020f8 reg2110 */ - struct { - RK_U32 i_cu32_madi_cnt_thd3 : 5; - RK_U32 reserved : 3; - RK_U32 i_cu32_madi_thd4 : 8; - RK_U32 i_cu32_madi_cost_multi : 8; - RK_U32 reserved1 : 8; - } rdo_atr_i_cu32_madi_cfg1; - - /* 0x000020fc reg2111 */ - struct { - RK_U32 i_cu16_madi_thd0 : 8; - RK_U32 i_cu16_madi_thd1 : 8; - RK_U32 i_cu16_madi_cost_multi : 8; - RK_U32 reserved : 8; - } rdo_atr_i_cu16_madi_cfg0; - - /* 0x00002100 reg2112 */ - struct { - RK_U32 base_thre_rough_mad32_intra : 4; - RK_U32 delta0_thre_rough_mad32_intra : 4; - RK_U32 delta1_thre_rough_mad32_intra : 6; - RK_U32 delta2_thre_rough_mad32_intra : 6; - RK_U32 delta3_thre_rough_mad32_intra : 7; - RK_U32 delta4_thre_rough_mad32_intra_low5 : 5; - } cudecis_thd0; - - /* 0x00002104 reg2113 */ - struct { - RK_U32 delta4_thre_rough_mad32_intra_high2 : 2; - RK_U32 delta5_thre_rough_mad32_intra : 7; - RK_U32 delta6_thre_rough_mad32_intra : 7; - RK_U32 base_thre_fine_mad32_intra : 4; - RK_U32 delta0_thre_fine_mad32_intra : 4; - RK_U32 delta1_thre_fine_mad32_intra : 5; - RK_U32 delta2_thre_fine_mad32_intra_low3 : 3; - } cudecis_thd1; - - /* 0x00002108 reg2114 */ - struct { - RK_U32 delta2_thre_fine_mad32_intra_high2 : 2; - RK_U32 delta3_thre_fine_mad32_intra : 5; - RK_U32 delta4_thre_fine_mad32_intra : 5; - RK_U32 delta5_thre_fine_mad32_intra : 6; - RK_U32 delta6_thre_fine_mad32_intra : 6; - RK_U32 base_thre_str_edge_mad32_intra : 3; - RK_U32 delta0_thre_str_edge_mad32_intra : 2; - RK_U32 delta1_thre_str_edge_mad32_intra : 3; - } cudecis_thd2; - - /* 0x0000210c reg2115 */ - struct { - RK_U32 delta2_thre_str_edge_mad32_intra : 3; - RK_U32 delta3_thre_str_edge_mad32_intra : 4; - RK_U32 base_thre_str_edge_bgrad32_intra : 5; - RK_U32 delta0_thre_str_edge_bgrad32_intra : 2; - RK_U32 delta1_thre_str_edge_bgrad32_intra : 3; - RK_U32 delta2_thre_str_edge_bgrad32_intra : 4; - RK_U32 delta3_thre_str_edge_bgrad32_intra : 5; - RK_U32 base_thre_mad16_intra : 3; - RK_U32 delta0_thre_mad16_intra : 3; - } cudecis_thd3; - - /* 0x00002110 reg2116 */ - struct { - RK_U32 delta1_thre_mad16_intra : 3; - RK_U32 delta2_thre_mad16_intra : 4; - RK_U32 delta3_thre_mad16_intra : 5; - RK_U32 delta4_thre_mad16_intra : 5; - RK_U32 delta5_thre_mad16_intra : 6; - RK_U32 delta6_thre_mad16_intra : 6; - RK_U32 delta0_thre_mad16_ratio_intra : 3; - } cudecis_thd4; - - /* 0x00002114 reg2117 */ - struct { - RK_U32 delta1_thre_mad16_ratio_intra : 3; - RK_U32 delta2_thre_mad16_ratio_intra : 3; - RK_U32 delta3_thre_mad16_ratio_intra : 3; - RK_U32 delta4_thre_mad16_ratio_intra : 3; - RK_U32 delta5_thre_mad16_ratio_intra : 3; - RK_U32 delta6_thre_mad16_ratio_intra : 3; - RK_U32 delta7_thre_mad16_ratio_intra : 3; - RK_U32 delta0_thre_rough_bgrad32_intra : 3; - RK_U32 delta1_thre_rough_bgrad32_intra : 4; - RK_U32 delta2_thre_rough_bgrad32_intra_low4 : 4; - } cudecis_thd5; - - /* 0x00002118 reg2118 */ - struct { - RK_U32 delta2_thre_rough_bgrad32_intra_high2 : 2; - RK_U32 delta3_thre_rough_bgrad32_intra : 10; - RK_U32 delta4_thre_rough_bgrad32_intra : 10; - RK_U32 delta5_thre_rough_bgrad32_intra_low10 : 10; - } cudecis_thd6; - - /* 0x0000211c reg2119 */ - struct { - RK_U32 delta5_thre_rough_bgrad32_intra_high1 : 1; - RK_U32 delta6_thre_rough_bgrad32_intra : 12; - RK_U32 delta7_thre_rough_bgrad32_intra : 13; - RK_U32 delta0_thre_bgrad16_ratio_intra : 4; - RK_U32 delta1_thre_bgrad16_ratio_intra_low2 : 2; - } cudecis_thd7; - - /* 0x00002120 reg2120 */ - struct { - RK_U32 delta1_thre_bgrad16_ratio_intra_high2 : 2; - RK_U32 delta2_thre_bgrad16_ratio_intra : 4; - RK_U32 delta3_thre_bgrad16_ratio_intra : 4; - RK_U32 delta4_thre_bgrad16_ratio_intra : 4; - RK_U32 delta5_thre_bgrad16_ratio_intra : 4; - RK_U32 delta6_thre_bgrad16_ratio_intra : 4; - RK_U32 delta7_thre_bgrad16_ratio_intra : 4; - RK_U32 delta0_thre_fme_ratio_inter : 3; - RK_U32 delta1_thre_fme_ratio_inter : 3; - } cudecis_thdt8; - - /* 0x00002124 reg2121 */ - struct { - RK_U32 delta2_thre_fme_ratio_inter : 3; - RK_U32 delta3_thre_fme_ratio_inter : 3; - RK_U32 delta4_thre_fme_ratio_inter : 3; - RK_U32 delta5_thre_fme_ratio_inter : 3; - RK_U32 delta6_thre_fme_ratio_inter : 3; - RK_U32 delta7_thre_fme_ratio_inter : 3; - RK_U32 base_thre_fme32_inter : 3; - RK_U32 delta0_thre_fme32_inter : 3; - RK_U32 delta1_thre_fme32_inter : 4; - RK_U32 delta2_thre_fme32_inter : 4; - } cudecis_thd9; - - /* 0x00002128 reg2122 */ - struct { - RK_U32 delta3_thre_fme32_inter : 5; - RK_U32 delta4_thre_fme32_inter : 6; - RK_U32 delta5_thre_fme32_inter : 7; - RK_U32 delta6_thre_fme32_inter : 8; - RK_U32 thre_cme32_inter : 6; - } cudecis_thd10; - - /* 0x0000212c reg2123 */ - struct { - RK_U32 delta0_thre_mad_fme_ratio_inter : 4; - RK_U32 delta1_thre_mad_fme_ratio_inter : 4; - RK_U32 delta2_thre_mad_fme_ratio_inter : 4; - RK_U32 delta3_thre_mad_fme_ratio_inter : 4; - RK_U32 delta4_thre_mad_fme_ratio_inter : 4; - RK_U32 delta5_thre_mad_fme_ratio_inter : 4; - RK_U32 delta6_thre_mad_fme_ratio_inter : 4; - RK_U32 delta7_thre_mad_fme_ratio_inter : 4; - } cudecis_thd11; -} Vepu510Sqi; - typedef struct Vepu510RoiRegion_t { - struct { RK_U32 roi_lt_x : 10; RK_U32 reserved : 6; @@ -591,6 +124,7 @@ typedef struct Vepu510RoiRegion_t { RK_U32 roi_en : 1; RK_U32 reserved : 18; } roi_base; + struct { RK_U32 roi_mdc_inter16 : 4; RK_U32 roi_mdc_skip16 : 4; @@ -640,6 +174,736 @@ typedef struct Vepu510RoiCfg_t { Vepu510RoiRegion regions[8]; } Vepu510RoiCfg; +/* class: control/link */ +/* 0x00000000 reg0 - 0x00000120 reg72 */ +typedef struct Vepu510ControlCfg_t { + /* 0x00000000 reg0 */ + struct { + RK_U32 sub_ver : 8; + RK_U32 h264_cap : 1; + RK_U32 hevc_cap : 1; + RK_U32 reserved : 2; + RK_U32 res_cap : 4; + RK_U32 osd_cap : 2; + RK_U32 filtr_cap : 2; + RK_U32 bfrm_cap : 1; + RK_U32 fbc_cap : 2; + RK_U32 reserved1 : 1; + RK_U32 ip_id : 8; + } version; + + /* 0x00000004 - 0x0000000c */ + RK_U32 reserved1_3[3]; + + /* 0x00000010 reg4 */ + struct { + RK_U32 lkt_num : 8; + RK_U32 vepu_cmd : 3; + RK_U32 reserved : 21; + } enc_strt; + + /* 0x00000014 reg5 */ + struct { + RK_U32 safe_clr : 1; + RK_U32 force_clr : 1; + RK_U32 reserved : 30; + } enc_clr; + + /* 0x00000018 reg6 */ + struct { + RK_U32 vswm_lcnt_soft : 14; + RK_U32 vswm_fcnt_soft : 8; + RK_U32 reserved : 2; + RK_U32 dvbm_ack_soft : 1; + RK_U32 dvbm_ack_sel : 1; + RK_U32 dvbm_inf_sel : 1; + RK_U32 reserved1 : 5; + } vs_ldly; + + /* 0x0000001c */ + RK_U32 reserved_7; + + /* 0x00000020 reg8 */ + struct { + RK_U32 enc_done_en : 1; + RK_U32 lkt_node_done_en : 1; + RK_U32 sclr_done_en : 1; + RK_U32 vslc_done_en : 1; + RK_U32 vbsf_oflw_en : 1; + RK_U32 vbuf_lens_en : 1; + RK_U32 enc_err_en : 1; + RK_U32 vsrc_err_en : 1; + RK_U32 wdg_en : 1; + RK_U32 lkt_err_int_en : 1; + RK_U32 lkt_err_stop_en : 1; + RK_U32 lkt_force_stop_en : 1; + RK_U32 jslc_done_en : 1; + RK_U32 jbsf_oflw_en : 1; + RK_U32 jbuf_lens_en : 1; + RK_U32 dvbm_err_en : 1; + RK_U32 reserved : 16; + } int_en; + + /* 0x00000024 reg9 */ + struct { + RK_U32 enc_done_msk : 1; + RK_U32 lkt_node_done_msk : 1; + RK_U32 sclr_done_msk : 1; + RK_U32 vslc_done_msk : 1; + RK_U32 vbsf_oflw_msk : 1; + RK_U32 vbuf_lens_msk : 1; + RK_U32 enc_err_msk : 1; + RK_U32 vsrc_err_msk : 1; + RK_U32 wdg_msk : 1; + RK_U32 lkt_err_int_msk : 1; + RK_U32 lkt_err_stop_msk : 1; + RK_U32 lkt_force_stop_msk : 1; + RK_U32 jslc_done_msk : 1; + RK_U32 jbsf_oflw_msk : 1; + RK_U32 jbuf_lens_msk : 1; + RK_U32 dvbm_err_msk : 1; + RK_U32 reserved : 16; + } int_msk; + + /* 0x00000028 reg10 */ + struct { + RK_U32 enc_done_clr : 1; + RK_U32 lkt_node_done_clr : 1; + RK_U32 sclr_done_clr : 1; + RK_U32 vslc_done_clr : 1; + RK_U32 vbsf_oflw_clr : 1; + RK_U32 vbuf_lens_clr : 1; + RK_U32 enc_err_clr : 1; + RK_U32 vsrc_err_clr : 1; + RK_U32 wdg_clr : 1; + RK_U32 lkt_err_int_clr : 1; + RK_U32 lkt_err_stop_clr : 1; + RK_U32 lkt_force_stop_clr : 1; + RK_U32 jslc_done_clr : 1; + RK_U32 jbsf_oflw_clr : 1; + RK_U32 jbuf_lens_clr : 1; + RK_U32 dvbm_err_clr : 1; + RK_U32 reserved : 16; + } int_clr; + + /* 0x0000002c reg11 */ + struct { + RK_U32 enc_done_sta : 1; + RK_U32 lkt_node_done_sta : 1; + RK_U32 sclr_done_sta : 1; + RK_U32 vslc_done_sta : 1; + RK_U32 vbsf_oflw_sta : 1; + RK_U32 vbuf_lens_sta : 1; + RK_U32 enc_err_sta : 1; + RK_U32 vsrc_err_sta : 1; + RK_U32 wdg_sta : 1; + RK_U32 lkt_err_int_sta : 1; + RK_U32 lkt_err_stop_sta : 1; + RK_U32 lkt_force_stop_sta : 1; + RK_U32 jslc_done_sta : 1; + RK_U32 jbsf_oflw_sta : 1; + RK_U32 jbuf_lens_sta : 1; + RK_U32 dvbm_err_sta : 1; + RK_U32 reserved : 16; + } int_sta; + + /* 0x00000030 reg12 */ + struct { + RK_U32 jpeg_bus_edin : 4; + RK_U32 src_bus_edin : 4; + RK_U32 meiw_bus_edin : 4; + RK_U32 bsw_bus_edin : 4; + RK_U32 reserved : 8; + RK_U32 lktw_bus_edin : 4; + RK_U32 rec_nfbc_bus_edin : 4; + } dtrns_map; + + /* 0x00000034 reg13 */ + struct { + RK_U32 reserved : 16; + RK_U32 axi_brsp_cke : 10; + RK_U32 reserved1 : 6; + } dtrns_cfg; + + /* 0x00000038 reg14 */ + struct { + RK_U32 vs_load_thd : 24; + RK_U32 reserved : 8; + } enc_wdg; + + /* 0x0000003c - 0x0000004c */ + RK_U32 reserved15_19[5]; + + /* 0x00000050 reg20 */ + struct { + RK_U32 idle_en_core : 1; + RK_U32 idle_en_axi : 1; + RK_U32 idle_en_ahb : 1; + RK_U32 reserved : 29; + } enc_idle_en; + + /* 0x00000054 reg21 */ + struct { + RK_U32 cke : 1; + RK_U32 resetn_hw_en : 1; + RK_U32 rfpr_err_e : 1; + RK_U32 sram_ckg_en : 1; + RK_U32 link_err_stop : 1; + RK_U32 reserved : 27; + } opt_strg; + + /* 0x00000058 reg22 */ + union { + struct { + RK_U32 tq8_ckg : 1; + RK_U32 tq4_ckg : 1; + RK_U32 bits_ckg_8x8 : 1; + RK_U32 bits_ckg_4x4_1 : 1; + RK_U32 bits_ckg_4x4_0 : 1; + RK_U32 inter_mode_ckg : 1; + RK_U32 inter_ctrl_ckg : 1; + RK_U32 inter_pred_ckg : 1; + RK_U32 intra8_ckg : 1; + RK_U32 intra4_ckg : 1; + RK_U32 reserved : 22; + } h264; + struct { + RK_U32 recon32_ckg : 1; + RK_U32 iqit32_ckg : 1; + RK_U32 q32_ckg : 1; + RK_U32 t32_ckg : 1; + RK_U32 cabac32_ckg : 1; + RK_U32 recon16_ckg : 1; + RK_U32 iqit16_ckg : 1; + RK_U32 q16_ckg : 1; + RK_U32 t16_ckg : 1; + RK_U32 cabac16_ckg : 1; + RK_U32 recon8_ckg : 1; + RK_U32 iqit8_ckg : 1; + RK_U32 q8_ckg : 1; + RK_U32 t8_ckg : 1; + RK_U32 cabac8_ckg : 1; + RK_U32 recon4_ckg : 1; + RK_U32 iqit4_ckg : 1; + RK_U32 q4_ckg : 1; + RK_U32 t4_ckg : 1; + RK_U32 cabac4_ckg : 1; + RK_U32 intra32_ckg : 1; + RK_U32 intra16_ckg : 1; + RK_U32 intra8_ckg : 1; + RK_U32 intra4_ckg : 1; + RK_U32 inter_pred_ckg : 1; + RK_U32 reserved : 7; + } hevc; + } rdo_ckg; + + /* 0x0000005c reg23 */ + struct { + RK_U32 core_id : 2; + RK_U32 reserved : 30; + } core_id; +} Vepu510ControlCfg; + +/* 0x00000270 reg156 - 0x0000039c reg231 */ +typedef struct Vepu510FrmCommon_t { + /* 0x00000270 reg156 - 0x0000027c reg159 */ + vepu510_online online_addr; + + /* 0x00000280 reg160 */ + RK_U32 adr_src0; + + /* 0x00000284 reg161 */ + RK_U32 adr_src1; + + /* 0x00000288 reg162 */ + RK_U32 adr_src2; + + /* 0x0000028c reg163 */ + RK_U32 rfpw_h_addr; + + /* 0x00000290 reg164 */ + RK_U32 rfpw_b_addr; + + /* 0x00000294 reg165 */ + RK_U32 rfpr_h_addr; + + /* 0x00000298 reg166 */ + RK_U32 rfpr_b_addr; + + /* 0x0000029c reg167 */ + RK_U32 colmvw_addr; + + /* 0x000002a0 reg168 */ + RK_U32 colmvr_addr; + + /* 0x000002a4 reg169 */ + RK_U32 dspw_addr; + + /* 0x000002a8 reg170 */ + RK_U32 dspr_addr; + + /* 0x000002ac reg171 */ + RK_U32 meiw_addr; + + /* 0x000002b0 reg172 */ + RK_U32 bsbt_addr; + + /* 0x000002b4 reg173 */ + RK_U32 bsbb_addr; + + /* 0x000002b8 reg174 */ + RK_U32 adr_bsbs; + + /* 0x000002bc reg175 */ + RK_U32 bsbr_addr; + + /* 0x000002c0 reg176 */ + RK_U32 lpfw_addr; + + /* 0x000002c4 reg177 */ + RK_U32 lpfr_addr; + + /* 0x000002c8 reg178 */ + RK_U32 ebuft_addr; + + /* 0x000002cc reg179 */ + RK_U32 ebufb_addr; + + /* 0x000002d0 reg180 */ + RK_U32 rfpt_h_addr; + + /* 0x000002d4 reg181 */ + RK_U32 rfpb_h_addr; + + /* 0x000002d8 reg182 */ + RK_U32 rfpt_b_addr; + + /* 0x000002dc reg183 */ + RK_U32 adr_rfpb_b; + + /* 0x000002e0 reg184 */ + RK_U32 adr_smear_rd; + + /* 0x000002e4 reg185 */ + RK_U32 adr_smear_wr; + + /* 0x000002e8 reg186 */ + RK_U32 adr_roir; + + /* 0x2ec - 0x2fc */ + RK_U32 reserved187_191[5]; + + /* 0x00000300 reg192 */ + struct { + RK_U32 enc_stnd : 2; + RK_U32 cur_frm_ref : 1; + RK_U32 mei_stor : 1; + RK_U32 bs_scp : 1; + RK_U32 reserved : 3; + RK_U32 pic_qp : 6; + RK_U32 num_pic_tot_cur_hevc : 5; + RK_U32 log2_ctu_num_hevc : 5; + RK_U32 reserved1 : 6; + RK_U32 slen_fifo : 1; + RK_U32 rec_fbc_dis : 1; + } enc_pic; + + /* 0x00000304 reg193 */ + struct { + RK_U32 dchs_txid : 2; + RK_U32 dchs_rxid : 2; + RK_U32 dchs_txe : 1; + RK_U32 dchs_rxe : 1; + RK_U32 reserved : 2; + RK_U32 dchs_dly : 8; + RK_U32 dchs_ofst : 10; + RK_U32 reserved1 : 6; + } dual_core; + + /* 0x00000308 reg194 */ + struct { + RK_U32 frame_id : 8; + RK_U32 frm_id_match : 1; + RK_U32 reserved : 7; + RK_U32 ch_id : 2; + RK_U32 vrsp_rtn_en : 1; + RK_U32 vinf_req_en : 1; + RK_U32 reserved1 : 12; + } enc_id; + + /* 0x0000030c reg195 */ + RK_U32 bsp_size; + + /* 0x00000310 reg196 */ + struct { + RK_U32 pic_wd8_m1 : 11; + RK_U32 reserved : 5; + RK_U32 pic_hd8_m1 : 11; + RK_U32 reserved1 : 5; + } enc_rsl; + + /* 0x00000314 reg197 */ + struct { + RK_U32 pic_wfill : 6; + RK_U32 reserved : 10; + RK_U32 pic_hfill : 6; + RK_U32 reserved1 : 10; + } src_fill; + + /* 0x00000318 reg198 */ + struct { + RK_U32 alpha_swap : 1; + RK_U32 rbuv_swap : 1; + RK_U32 src_cfmt : 4; + RK_U32 src_rcne : 1; + RK_U32 out_fmt : 1; + RK_U32 src_range_trns_en : 1; + RK_U32 src_range_trns_sel : 1; + RK_U32 chroma_ds_mode : 1; + RK_U32 reserved : 21; + } src_fmt; + + /* 0x0000031c reg199 */ + struct { + RK_U32 csc_wgt_b2y : 9; + RK_U32 csc_wgt_g2y : 9; + RK_U32 csc_wgt_r2y : 9; + RK_U32 reserved : 5; + } src_udfy; + + /* 0x00000320 reg200 */ + struct { + RK_U32 csc_wgt_b2u : 9; + RK_U32 csc_wgt_g2u : 9; + RK_U32 csc_wgt_r2u : 9; + RK_U32 reserved : 5; + } src_udfu; + + /* 0x00000324 reg201 */ + struct { + RK_U32 csc_wgt_b2v : 9; + RK_U32 csc_wgt_g2v : 9; + RK_U32 csc_wgt_r2v : 9; + RK_U32 reserved : 5; + } src_udfv; + + /* 0x00000328 reg202 */ + struct { + RK_U32 csc_ofst_v : 8; + RK_U32 csc_ofst_u : 8; + RK_U32 csc_ofst_y : 5; + RK_U32 reserved : 11; + } src_udfo; + + /* 0x0000032c reg203 */ + struct { + RK_U32 cr_force_value : 8; + RK_U32 cb_force_value : 8; + RK_U32 chroma_force_en : 1; + RK_U32 reserved : 9; + RK_U32 src_mirr : 1; + RK_U32 src_rot : 2; + RK_U32 tile4x4_en : 1; + RK_U32 reserved1 : 2; + } src_proc; + + /* 0x00000330 reg204 */ + struct { + RK_U32 pic_ofst_x : 14; + RK_U32 reserved : 2; + RK_U32 pic_ofst_y : 14; + RK_U32 reserved1 : 2; + } pic_ofst; + + /* 0x00000334 reg205 */ + struct { + RK_U32 src_strd0 : 21; + RK_U32 reserved : 11; + } src_strd0; + + /* 0x00000338 reg206 */ + struct { + RK_U32 src_strd1 : 16; + RK_U32 reserved : 16; + } src_strd1; + + /* 0x33c - 0x34c */ + RK_U32 reserved207_211[5]; + + /* 0x00000350 reg212 */ + struct { + RK_U32 rc_en : 1; + RK_U32 aq_en : 1; + RK_U32 reserved : 10; + RK_U32 rc_ctu_num : 20; + } rc_cfg; + + /* 0x00000354 reg213 */ + struct { + RK_U32 reserved : 16; + RK_U32 rc_qp_range : 4; + RK_U32 rc_max_qp : 6; + RK_U32 rc_min_qp : 6; + } rc_qp; + + /* 0x00000358 reg214 */ + struct { + RK_U32 ctu_ebit : 20; + RK_U32 reserved : 12; + } rc_tgt; + + /* 0x35c */ + RK_U32 reserved_215; + + /* 0x00000360 reg216 */ + struct { + RK_U32 sli_splt : 1; + RK_U32 sli_splt_mode : 1; + RK_U32 sli_splt_cpst : 1; + RK_U32 reserved : 12; + RK_U32 sli_flsh : 1; + RK_U32 sli_max_num_m1 : 15; + RK_U32 reserved1 : 1; + } sli_splt; + + /* 0x00000364 reg217 */ + struct { + RK_U32 sli_splt_byte : 20; + RK_U32 reserved : 12; + } sli_byte; + + /* 0x00000368 reg218 */ + struct { + RK_U32 sli_splt_cnum_m1 : 20; + RK_U32 reserved : 12; + } sli_cnum; + + /* 0x0000036c reg219 */ + struct { + RK_U32 uvc_partition0_len : 12; + RK_U32 uvc_partition_len : 12; + RK_U32 uvc_skip_len : 6; + RK_U32 reserved : 2; + } vbs_pad; + + /* 0x00000370 reg220 */ + struct { + RK_U32 cime_srch_dwnh : 4; + RK_U32 cime_srch_uph : 4; + RK_U32 cime_srch_rgtw : 4; + RK_U32 cime_srch_lftw : 4; + RK_U32 dlt_frm_num : 16; + } me_rnge; + + /* 0x00000374 reg221 */ + struct { + RK_U32 srgn_max_num : 7; + RK_U32 cime_dist_thre : 13; + RK_U32 rme_srch_h : 2; + RK_U32 rme_srch_v : 2; + RK_U32 rme_dis : 3; + RK_U32 reserved : 1; + RK_U32 fme_dis : 3; + RK_U32 reserved1 : 1; + } me_cfg; + + /* 0x00000378 reg222 */ + struct { + RK_U32 cime_zero_thre : 13; + RK_U32 reserved : 15; + RK_U32 fme_prefsu_en : 2; + RK_U32 colmv_stor_hevc : 1; + RK_U32 colmv_load_hevc : 1; + } me_cach; + + /* 0x37c - 0x39c */ + RK_U32 reserved223_231[9]; +} Vepu510FrmCommon; + +/* class: rc/roi/aq/klut */ +/* 0x00001000 reg1024 - 0x0000110c reg1091 */ +typedef struct Vepu510RcRoi_t { + /* 0x00001000 reg1024 */ + struct { + RK_U32 qp_adj0 : 5; + RK_U32 qp_adj1 : 5; + RK_U32 qp_adj2 : 5; + RK_U32 qp_adj3 : 5; + RK_U32 qp_adj4 : 5; + RK_U32 reserved : 7; + } rc_adj0; + + /* 0x00001004 reg1025 */ + struct { + RK_U32 qp_adj5 : 5; + RK_U32 qp_adj6 : 5; + RK_U32 qp_adj7 : 5; + RK_U32 qp_adj8 : 5; + RK_U32 reserved : 12; + } rc_adj1; + + /* 0x00001008 reg1026 - 0x00001028 reg1034 */ + RK_U32 rc_dthd_0_8[9]; + + /* 0x102c */ + RK_U32 reserved_1035; + + /* 0x00001030 reg1036 */ + struct { + RK_U32 qpmin_area0 : 6; + RK_U32 qpmax_area0 : 6; + RK_U32 qpmin_area1 : 6; + RK_U32 qpmax_area1 : 6; + RK_U32 qpmin_area2 : 6; + RK_U32 reserved : 2; + } roi_qthd0; + + /* 0x00001034 reg1037 */ + struct { + RK_U32 qpmax_area2 : 6; + RK_U32 qpmin_area3 : 6; + RK_U32 qpmax_area3 : 6; + RK_U32 qpmin_area4 : 6; + RK_U32 qpmax_area4 : 6; + RK_U32 reserved : 2; + } roi_qthd1; + + /* 0x00001038 reg1038 */ + struct { + RK_U32 qpmin_area5 : 6; + RK_U32 qpmax_area5 : 6; + RK_U32 qpmin_area6 : 6; + RK_U32 qpmax_area6 : 6; + RK_U32 qpmin_area7 : 6; + RK_U32 reserved : 2; + } roi_qthd2; + + /* 0x0000103c reg1039 */ + struct { + RK_U32 qpmax_area7 : 6; + RK_U32 reserved : 24; + RK_U32 qpmap_mode : 2; + } roi_qthd3; + + /* 0x00001040 reg1040 */ + RK_U32 reserved_1040; + + /* 0x00001044 reg1041 */ + struct { + RK_U32 aq_tthd0 : 8; + RK_U32 aq_tthd1 : 8; + RK_U32 aq_tthd2 : 8; + RK_U32 aq_tthd3 : 8; + } aq_tthd0; + + /* 0x00001048 reg1042 */ + struct { + RK_U32 aq_tthd4 : 8; + RK_U32 aq_tthd5 : 8; + RK_U32 aq_tthd6 : 8; + RK_U32 aq_tthd7 : 8; + } aq_tthd1; + + /* 0x0000104c reg1043 */ + struct { + RK_U32 aq_tthd8 : 8; + RK_U32 aq_tthd9 : 8; + RK_U32 aq_tthd10 : 8; + RK_U32 aq_tthd11 : 8; + } aq_tthd2; + + /* 0x00001050 reg1044 */ + struct { + RK_U32 aq_tthd12 : 8; + RK_U32 aq_tthd13 : 8; + RK_U32 aq_tthd14 : 8; + RK_U32 aq_tthd15 : 8; + } aq_tthd3; + + /* 0x00001054 reg1045 */ + struct { + RK_U32 aq_stp_s0 : 5; + RK_U32 aq_stp_0t1 : 5; + RK_U32 aq_stp_1t2 : 5; + RK_U32 aq_stp_2t3 : 5; + RK_U32 aq_stp_3t4 : 5; + RK_U32 aq_stp_4t5 : 5; + RK_U32 reserved : 2; + } aq_stp0; + + /* 0x00001058 reg1046 */ + struct { + RK_U32 aq_stp_5t6 : 5; + RK_U32 aq_stp_6t7 : 5; + RK_U32 aq_stp_7t8 : 5; + RK_U32 aq_stp_8t9 : 5; + RK_U32 aq_stp_9t10 : 5; + RK_U32 aq_stp_10t11 : 5; + RK_U32 reserved : 2; + } aq_stp1; + + /* 0x0000105c reg1047 */ + struct { + RK_U32 aq_stp_11t12 : 5; + RK_U32 aq_stp_12t13 : 5; + RK_U32 aq_stp_13t14 : 5; + RK_U32 aq_stp_14t15 : 5; + RK_U32 aq_stp_b15 : 5; + RK_U32 reserved : 7; + } aq_stp2; + + /* 0x00001060 reg1048 */ + struct { + RK_U32 aq16_rnge : 4; + RK_U32 aq32_rnge : 4; + RK_U32 aq8_rnge : 5; + RK_U32 aq16_dif0 : 5; + RK_U32 aq16_dif1 : 5; + RK_U32 reserved : 1; + RK_U32 aq_cme_en : 1; + RK_U32 aq_subj_cme_en : 1; + RK_U32 aq_rme_en : 1; + RK_U32 aq_subj_rme_en : 1; + RK_U32 reserved1 : 4; + } aq_clip; + + /* 0x00001064 reg1049 */ + struct { + RK_U32 madi_th0 : 8; + RK_U32 madi_th1 : 8; + RK_U32 madi_th2 : 8; + RK_U32 reserved : 8; + } madi_st_thd; + + /* 0x00001068 reg1050 */ + struct { + RK_U32 madp_th0 : 12; + RK_U32 reserved : 4; + RK_U32 madp_th1 : 12; + RK_U32 reserved1 : 4; + } madp_st_thd0; + + /* 0x0000106c reg1051 */ + struct { + RK_U32 madp_th2 : 12; + RK_U32 reserved : 20; + } madp_st_thd1; + + /* 0x1070 - 0x1078 */ + RK_U32 reserved1052_1054[3]; + + /* 0x0000107c reg1055 */ + struct { + RK_U32 chrm_klut_ofst : 4; + RK_U32 reserved : 4; + RK_U32 inter_chrm_dist_multi : 6; + RK_U32 reserved1 : 18; + } klut_ofst; + + /*0x00001080 reg1056 - 0x0000110c reg1091 */ + Vepu510RoiCfg roi_cfg; +} Vepu510RcRoi; + /* class: st */ /* 0x00004000 reg4096 - 0x0000424c reg4243*/ typedef struct Vepu510Status_t { @@ -745,7 +1009,7 @@ typedef struct Vepu510Status_t { RK_U32 sli_lst : 1; } st_slen; - /* 0x403c - 0x40fc */ + /* 0x403c - reg4111 */ struct { RK_U32 task_id_proc : 12; RK_U32 task_id_done : 12; @@ -757,6 +1021,7 @@ typedef struct Vepu510Status_t { /* 0x4040 - 0x405c */ RK_U32 reserved4111_4119[8]; + /* 0x00004060 reg4120 */ struct { RK_U32 sli_len_jpeg : 31; RK_U32 sli_lst_jpeg : 1; @@ -845,7 +1110,7 @@ typedef struct Vepu510Status_t { } st_smear_cnt; /* 0x000040a8 reg4138 */ - RK_U32 madi_sum; + RK_U32 madi16_sum; /* 0x000040ac reg4139 */ RK_U32 madi32_sum; @@ -1065,64 +1330,45 @@ typedef struct Vepu510Status_t { } Vepu510Status; /* class: dbg/st/axipn */ -/* 0x00005000 reg5120 - 0x00005354 reg5333*/ +/* 0x00005000 reg5120 - 0x0000230 reg5260*/ //TODO: typedef struct Vepu510Dbg_t { - struct { - RK_U32 pp0_tout : 1; - RK_U32 pp1_out : 1; - RK_U32 cme_tout : 1; - RK_U32 swn_tout : 1; - RK_U32 rfme_tout : 1; - RK_U32 pren_tout : 1; - RK_U32 rdo_tout : 1; - RK_U32 lpf_tout : 1; - RK_U32 etpy_tout : 1; - RK_U32 jpeg_tout : 1; - RK_U32 frm_tout : 1; - RK_U32 reserved : 21; - } st_wdg; - - /* 0x00005004 reg5121 */ - struct { - RK_U32 pp0_wrk : 1; - RK_U32 pp1_wrk : 1; - RK_U32 cme_wrk : 1; - RK_U32 swn_wrk : 1; - RK_U32 rfme_wrk : 1; - RK_U32 pren_wrk : 1; - RK_U32 rdo_wrk : 1; - RK_U32 lpf_wrk : 1; - RK_U32 etpy_wrk : 1; - RK_U32 jpeg_wrk : 1; - RK_U32 frm_wrk : 1; - RK_U32 reserved : 21; - } st_ppl; - - /* 0x00005008 reg5122 */ + /* 0x00005000 reg5120 */ struct { RK_U32 vsp0_pos_x : 16; RK_U32 vsp0_pos_y : 16; } st_ppl_pos_vsp0; - /* 0x0000500c reg5123 */ + /* 0x00005004 reg5121 */ struct { RK_U32 vsp1_pos_x : 16; RK_U32 vsp1_pos_y : 16; } st_ppl_pos_vsp1; - /* 0x00005010 reg5124 */ + /* 0x00005008 reg5122 */ struct { RK_U32 cme_pos_x : 16; RK_U32 cme_pos_y : 16; } st_ppl_pos_cme; - /* 0x00005014 reg5125 */ + /* 0x0000500c reg5123 */ + struct { + RK_U32 swin_cmd_x : 16; + RK_U32 swin_cmd_y : 16; + } st_ppl_cmd_swin; + + /* 0x00005010 reg5124 */ struct { RK_U32 swin_pos_x : 16; RK_U32 swin_pos_y : 16; } st_ppl_pos_swin; + /* 0x00005014 reg5125 */ + struct { + RK_U32 pren_pos_x : 16; + RK_U32 pren_pos_y : 16; + } st_ppl_pos_pren; + /* 0x00005018 reg5126 */ struct { RK_U32 rfme_pos_x : 16; @@ -1130,58 +1376,251 @@ typedef struct Vepu510Dbg_t { } st_ppl_pos_rfme; /* 0x0000501c reg5127 */ - struct { - RK_U32 pren_pos_x : 16; - RK_U32 pren_pos_y : 16; - } st_ppl_pos_pren; - - /* 0x00005020 reg5128 */ struct { RK_U32 rdo_pos_x : 16; RK_U32 rdo_pos_y : 16; } st_ppl_pos_rdo; - /* 0x00005024 reg5129 */ + /* 0x00005020 reg5128 */ struct { RK_U32 lpf_pos_x : 16; RK_U32 lpf_pos_y : 16; } st_ppl_pos_lpf; - /* 0x00005028 reg5130 */ + /* 0x00005024 reg5129 */ struct { RK_U32 etpy_pos_x : 16; RK_U32 etpy_pos_y : 16; } st_ppl_pos_etpy; - /* 0x0000502c reg5131 */ + /* 0x00005028 reg5130 */ struct { RK_U32 vsp0_pos_x : 16; RK_U32 vsp0_pos_y : 16; } st_ppl_pos_jsp0; - /* 0x00005030 reg5132 */ + /* 0x0000502c reg5131 */ struct { RK_U32 vsp1_pos_x : 16; RK_U32 vsp1_pos_y : 16; } st_ppl_pos_jsp1; - /* 0x00005034 reg5133 */ + /* 0x00005030 reg5132 */ struct { RK_U32 jpeg_pos_x : 16; RK_U32 jpeg_pos_y : 16; } st_ppl_pos_jpeg; - /* 0x5038 - 0x503c */ - RK_U32 reserved5134_5135[2]; - + /* 0x5034 - 0x503c */ + RK_U32 reserved5133_5135[3]; /* 0x00005040 reg5136 */ + struct { + RK_U32 vsp0_org_err : 1; + RK_U32 vsp0_vsld_err : 1; + RK_U32 pp0_pp1_err : 1; + RK_U32 vsp0_cmd_err : 1; + RK_U32 reserved : 24; + RK_U32 vsp0_wrk : 1; + RK_U32 vsp0_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_vsp0; + + /* 0x00005044 reg5137 */ + struct { + RK_U32 vsp1_org_err : 1; + RK_U32 vsp1_rdo_err : 1; + RK_U32 reserved : 26; + RK_U32 vsp1_wrk : 1; + RK_U32 vsp1_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_vsp1; + + /* 0x00005048 reg5138 */ + struct { + RK_U32 cme_org_err : 1; + RK_U32 cme_roi_err : 1; + RK_U32 cme_win_err : 1; + RK_U32 cme_cmmv_err : 1; + RK_U32 cme_smvp_err : 1; + RK_U32 cme_meiw_err : 1; + RK_U32 cme_dist_err : 1; + RK_U32 cme_rdo_err : 1; + RK_U32 cme_madp_err : 1; + RK_U32 cme_mv_err : 1; + RK_U32 reserved : 18; + RK_U32 cme_wrk : 1; + RK_U32 cme_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_cme; + + /* 0x0000504c reg5139 */ + struct { + RK_U32 swin_org_err : 1; + RK_U32 swin_ref_err : 1; + RK_U32 swin_cmd_err : 1; + RK_U32 reserved : 25; + RK_U32 swin_wrk : 1; + RK_U32 swin_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_swin; + + /* 0x00005050 reg5140 */ + struct { + RK_U32 swin_buff_ptr : 2; + RK_U32 swin_buff_num0 : 2; + RK_U32 swin_buff_num1 : 2; + RK_U32 swin_buff_num2 : 2; + RK_U32 reserved : 24; + } dbg_ppl_swin; + + /* 0x00005054 reg5141 */ + struct { + RK_U32 pnra_org_err : 1; + RK_U32 pnra_dist_err : 1; + RK_U32 pnra_olm_err : 1; + RK_U32 reserved : 25; + RK_U32 pnra_wrk : 1; + RK_U32 pnra_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_pren; + + /* 0x00005058 reg5142 */ + struct { + RK_U32 rfme_org_err : 1; + RK_U32 rfme_ref_err : 1; + RK_U32 rfme_cmmv_err : 1; + RK_U32 rfme_rfmv_err : 1; + RK_U32 rfme_tmvp_err : 1; + RK_U32 reserved : 23; + RK_U32 rfme_wrk : 1; + RK_U32 rfme_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_rfme; + + /* 0x0000505c reg5143 */ + struct { + RK_U32 rdo_org_err : 1; + RK_U32 rdo_ref_err : 1; + RK_U32 rdo_inf_err : 1; + RK_U32 rdo_roi_err : 1; + RK_U32 rdo_rfmv_err : 1; + RK_U32 rdo_lbfr_err : 1; + RK_U32 rdo_lbfw_err : 1; + RK_U32 rdo_tmvp_rd_err : 1; + RK_U32 rdo_tmvp_wr_err : 1; + RK_U32 rdo_st_err : 1; + RK_U32 rdo_pnra_err : 1; + RK_U32 rdo_lpf_err : 1; + RK_U32 rdo_ent_err : 1; + RK_U32 reserved : 15; + RK_U32 rdo_wrk : 1; + RK_U32 rdo_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_rdo; + + /* 0x00005060 reg5144 */ + struct { + RK_U32 lpf_org_err : 1; + RK_U32 lpf_lbfr_err : 1; + RK_U32 lpf_lbfw_err : 1; + RK_U32 lpf_rcol_err : 1; + RK_U32 reserved : 24; + RK_U32 lpf_wrk : 1; + RK_U32 lpf_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_lpf; + + /* 0x00005064 reg5145 */ + struct { + RK_U32 etpy_bsw_err : 1; + RK_U32 reserved : 27; + RK_U32 etpy_wrk : 1; + RK_U32 etpy_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_etpy; + + /* 0x00005068 reg5146 */ + struct { + RK_U32 jsp0_org_err : 1; + RK_U32 jsp0_vsld_err : 1; + RK_U32 pp0_pp1_err : 1; + RK_U32 jsp0_cmd_err : 1; + RK_U32 reserved : 24; + RK_U32 jsp0_wrk : 1; + RK_U32 jsp0_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_jsp0; + + /* 0x0000506c reg5147 */ + struct { + RK_U32 jsp1_org_err : 1; + RK_U32 jsp1_madi_err : 1; + RK_U32 reserved : 26; + RK_U32 jsp1_wrk : 1; + RK_U32 jsp1_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_jsp1; + + /* 0x00005070 reg5148 */ + struct { + RK_U32 jpeg_org_err : 1; + RK_U32 reserved : 27; + RK_U32 jpeg_wrk : 1; + RK_U32 jpeg_tout : 1; + RK_U32 reserved1 : 2; + } dbg_ctrl_jpeg; + + /* 0x00005074 reg5149 */ + struct { + RK_U32 dma_brsp_idle : 1; + RK_U32 jpeg_frm_done : 1; + RK_U32 rdo_frm_done : 1; + RK_U32 lpf_frm_done : 1; + RK_U32 ent_frm_done : 1; + RK_U32 ppl_ctrl_done : 1; + RK_U32 criw_frm_done : 1; + RK_U32 meiw_frm_done : 1; + RK_U32 smiw_frm_done : 1; + RK_U32 strg_rsrc_done : 1; + RK_U32 reserved : 18; + RK_U32 frm_wrk : 1; + RK_U32 frm_tout : 1; + RK_U32 reserved1 : 2; + } dbg_tctrl0; + + /* 0x00005078 reg5150 */ + struct { + RK_U32 pp0_cmd_vld : 1; + RK_U32 pp0_cmd_rdy : 1; + RK_U32 pp0_cmd_eid : 1; + RK_U32 cme_madp_vld : 1; + RK_U32 cme_madp_rdy0 : 1; + RK_U32 cmd_madp_rdy1 : 1; + RK_U32 cme_mv16_vld : 1; + RK_U32 cmd_mv16_rdy : 1; + RK_U32 swin_cmd_vld : 1; + RK_U32 swin_cmd_rdy : 1; + RK_U32 pnra_olm_vld : 1; + RK_U32 pnra_olm_rdy : 1; + RK_U32 lpf_rcol_vld : 1; + RK_U32 lpf_rcol_rdy : 1; + RK_U32 bsw_dat_vld : 1; + RK_U32 bsw_dat_rdy : 1; + RK_U32 slc_fifo_full : 1; + RK_U32 reserved : 15; + } dbg_tctrl1; + + /* 0x507c */ + RK_U32 reserved_5151; + + /* 0x00005080 reg5152 */ struct { RK_U32 sli_num : 15; RK_U32 reserved : 17; } st_sli_num; - /* 0x5044 - 0x50fc */ - RK_U32 reserved5137_5183[47]; + /* 0x5084 - 0x50fc */ + RK_U32 reserved5153_5183[31]; /* 0x00005100 reg5184 */ struct { @@ -1282,8 +1721,8 @@ typedef struct Vepu510Dbg_t { RK_U32 vld_lwreq : 1; } dbg_fbd_hhit0; - /* 0x5110 */ - RK_U32 reserved_5188; + /* 0x00005110 reg5188 */ + RK_U32 rfme_dbg_inf; /* 0x00005114 reg5189 */ struct { @@ -1298,10 +1737,10 @@ typedef struct Vepu510Dbg_t { RK_U32 l2_mis; /* 0x00005120 reg5192 */ - RK_U32 rdo_st; + RK_U32 rdo_dbg0; /* 0x00005124 reg5193 */ - RK_U32 rdo_if; + RK_U32 rdo_dbg1; /* 0x00005128 reg5194 */ struct { @@ -1314,81 +1753,105 @@ typedef struct Vepu510Dbg_t { /* 0x0000512c reg5195 */ struct { - RK_U32 crdy_ppr : 1; - RK_U32 cvld_ppr : 1; - RK_U32 drdy_ppw : 1; - RK_U32 dvld_ppw : 1; - RK_U32 crdy_ppw : 1; - RK_U32 cvld_ppw : 1; - RK_U32 reserved : 26; - } dbg_dma_pp; + RK_U32 chl_aw_vld : 10; + RK_U32 chl_aw_rdy : 10; + RK_U32 aw_vld_arb : 1; + RK_U32 aw_rdy_arb : 1; + RK_U32 aw_vld_crosclk : 1; + RK_U32 aw_rdy_crosclk : 1; + RK_U32 aw_rdy_mmu : 1; + RK_U32 aw_vld_mmu : 1; + RK_U32 aw_rdy_axi : 1; + RK_U32 aw_vld_axi : 1; + RK_U32 reserved : 4; + } dbg_dma_aw; /* 0x00005130 reg5196 */ struct { - RK_U32 axi_wrdy : 8; - RK_U32 axi_wvld : 8; - RK_U32 axi_awrdy : 8; - RK_U32 axi_awvld : 8; + RK_U32 chl_w_vld : 10; + RK_U32 chl_w_rdy : 10; + RK_U32 w_vld_arb : 1; + RK_U32 w_rdy_arb : 1; + RK_U32 w_vld_crosclk : 1; + RK_U32 w_rdy_crosclk : 1; + RK_U32 w_rdy_mmu : 1; + RK_U32 w_vld_mmu : 1; + RK_U32 w_rdy_axi : 1; + RK_U32 w_vld_axi : 1; + RK_U32 reserved : 4; } dbg_dma_w; /* 0x00005134 reg5197 */ struct { - RK_U32 axi_otsd_read : 16; - RK_U32 axi_arrdy : 7; - RK_U32 reserved : 1; - RK_U32 axi_arvld : 7; - RK_U32 reserved1 : 1; + RK_U32 chl_ar_vld : 9; + RK_U32 chl_ar_rdy : 9; + RK_U32 reserved : 2; + RK_U32 ar_vld_arb : 1; + RK_U32 ar_rdy_arb : 1; + RK_U32 ar_vld_crosclk : 1; + RK_U32 ar_rdy_crosclk : 1; + RK_U32 ar_rdy_mmu : 1; + RK_U32 ar_vld_mmu : 1; + RK_U32 ar_rdy_axi : 1; + RK_U32 ar_vld_axi : 1; + RK_U32 reserved1 : 4; } dbg_dma_ar; /* 0x00005138 reg5198 */ struct { - RK_U32 dfifo0_lvl : 4; - RK_U32 dfifo1_lvl : 4; - RK_U32 dfifo2_lvl : 4; - RK_U32 dfifo3_lvl : 4; - RK_U32 dfifo4_lvl : 4; - RK_U32 dfifo5_lvl : 4; - RK_U32 reserved : 6; - RK_U32 cmd_vld : 1; - RK_U32 reserved1 : 1; + RK_U32 chl_r_vld : 9; + RK_U32 chl_r_rdy : 9; + RK_U32 reserved : 2; + RK_U32 r_vld_arb : 1; + RK_U32 r_rdy_arb : 1; + RK_U32 r_vld_crosclk : 1; + RK_U32 r_rdy_crosclk : 1; + RK_U32 r_rdy_mmu : 1; + RK_U32 r_vld_mmu : 1; + RK_U32 r_rdy_axi : 1; + RK_U32 r_vld_axi : 1; + RK_U32 b_rdy_mmu : 1; + RK_U32 b_vld_mmu : 1; + RK_U32 b_rdy_axi : 1; + RK_U32 b_vld_axi : 1; } dbg_dma_r; - /* 0x0000513c reg5199 */ - struct { - RK_U32 meiw_busy : 1; - RK_U32 dspw_busy : 1; - RK_U32 bsw_rdy : 1; - RK_U32 bsw_flsh : 1; - RK_U32 bsw_busy : 1; - RK_U32 crpw_busy : 1; - RK_U32 lktw_busy : 1; - RK_U32 lpfw_busy : 1; - RK_U32 roir_busy : 1; - RK_U32 dspr_crdy : 1; - RK_U32 dspr_cvld : 1; - RK_U32 lktr_busy : 1; - RK_U32 lpfr_otsd : 4; - RK_U32 rfpr_otsd : 12; - RK_U32 dspr_otsd : 4; - } dbg_dma_dbg0; + /* 0x513c */ + RK_U32 reserved_5199; /* 0x00005140 reg5200 */ struct { - RK_U32 cpip_st : 2; - RK_U32 mvp_st : 3; - RK_U32 qpd6_st : 2; - RK_U32 cmd_st : 2; - RK_U32 reserved : 23; + RK_U32 bsw_fsm_stus : 4; + RK_U32 bsw_aw_full : 1; + RK_U32 bsw_rdy_ent : 1; + RK_U32 bsw_vld_ent : 1; + RK_U32 jpg_bsw_stus : 4; + RK_U32 jpg_aw_full : 1; + RK_U32 jpg_bsw_rdy : 1; + RK_U32 jpg_bsw_vld : 1; + RK_U32 crpw_fsm_stus : 3; + RK_U32 hdwr_rdy : 1; + RK_U32 hdwr_vld : 1; + RK_U32 bdwr_rdy : 1; + RK_U32 bdwr_vld : 1; + RK_U32 nfbc_rdy : 1; + RK_U32 nfbc_vld : 1; + RK_U32 dsp_fsm_stus : 2; + RK_U32 dsp_wr_flg : 1; + RK_U32 dsp_rsy : 1; + RK_U32 dsp_vld : 1; + RK_U32 lpfw_fsm_stus : 3; + RK_U32 reserved : 1; } dbg_dma_dbg1; - /* 0x00005144 reg5201 */ - struct { - RK_U32 cme_byps : 3; - RK_U32 reserved : 29; - } dbg_tctrl; + /* 0x5144 */ + RK_U32 reserved_5201; - /* 0x5148 */ - RK_U32 reserved_5202; + /* 0x00005148 reg5202 */ + struct { + RK_U32 rdo_st : 20; + RK_U32 reserved : 12; + } dbg_rdo_st; /* 0x0000514c reg5203 */ struct { @@ -1407,8 +1870,8 @@ typedef struct Vepu510Dbg_t { RK_U32 reserved1 : 3; } dbg_lpf; - /* 0x00005150 reg5204 */ - RK_U32 dbg_topc_lpfr; + /* 0x5150 */ + RK_U32 reserved_5204; /* 0x00005154 reg5205 */ RK_U32 dbg0_cache; @@ -1463,83 +1926,226 @@ typedef struct Vepu510Dbg_t { /* 0x00005168 reg5210 */ struct { - RK_U32 vinf_lcnt_dvbm : 14; - RK_U32 vinf_fcnt_dvbm : 8; - RK_U32 vinf_rdy_dvbm : 1; - RK_U32 vinf_vld_dvbm : 1; - RK_U32 st_cur_vinf : 3; - RK_U32 st_cur_vrsp : 2; - RK_U32 vcnt_req_sync : 1; - RK_U32 vcnt_ack_dvbm : 1; - RK_U32 vcnt_req_dvbm : 1; - } dbg_dvbm0; + RK_U32 dbg_isp_fcnt : 8; + RK_U32 dbg_isp_fcyc : 24; + } dbg_dvbm_isp0; /* 0x0000516c reg5211 */ struct { - RK_U32 vrsp_lcnt_dvbm : 14; - RK_U32 vrsp_fcnt_dvbm : 8; - RK_U32 vrsp_tgl_dvbm : 1; - RK_U32 reserved : 9; - } dbg_dvbm1; + RK_U32 dbg_isp_lcnt : 14; + RK_U32 reserved : 1; + RK_U32 dbg_isp_ltgl : 1; + RK_U32 dbg_isp_fcnt : 8; + RK_U32 dbg_isp_oflw : 1; + RK_U32 dbg_isp_ftgl : 1; + RK_U32 dbg_isp_full : 1; + RK_U32 dbg_isp_work : 1; + RK_U32 dbg_isp_lvld : 1; + RK_U32 dbg_isp_lrdy : 1; + RK_U32 dbg_isp_fvld : 1; + RK_U32 dbg_isp_frdy : 1; + } dbg_dvbm_isp1; /* 0x00005170 reg5212 */ struct { - RK_U32 dvbm_src_lcnt : 12; - RK_U32 jbuf_dvbm_rdy : 1; - RK_U32 vbuf_dvbm_rdy : 1; - RK_U32 work_dvbm_rdy : 1; - RK_U32 fmch_dvbm_rdy : 1; - RK_U32 vrsp_lcnt_vsld : 14; - RK_U32 vrsp_rdy_vsld : 1; - RK_U32 vrsp_vld_vsld : 1; - } dbg_dvbm2; + RK_U32 dbg_bf0_isp_lcnt : 14; + RK_U32 dbg_bf0_isp_llst : 1; + RK_U32 dbg_bf0_isp_sofw : 1; + RK_U32 dbg_bf0_isp_fcnt : 8; + RK_U32 dbg_bf0_isp_pnt : 1; + RK_U32 reserved : 3; + RK_U32 dbg_bf0_vpu_pnt : 1; + RK_U32 reserved1 : 3; + } dbg_dvbm_buf0_inf0; /* 0x00005174 reg5213 */ struct { - RK_U32 vsp_ctu_flag : 4; - RK_U32 reserved : 4; - RK_U32 cime_ctu_flag : 8; - RK_U32 swin_ctu_flag : 2; - RK_U32 rfme_ctu_flag : 6; - RK_U32 pnra_ctu_flag : 1; - RK_U32 rdo_ctu_flg0 : 7; - } dbg_tctrl0; + RK_U32 dbg_bf0_src_lcnt : 14; + RK_U32 dbg_bf0_src_llst : 1; + RK_U32 reserved : 1; + RK_U32 dbg_bf0_vpu_lcnt : 14; + RK_U32 dbg_bf0_vpu_llst : 1; + RK_U32 dbg_bf0_vpu_vofw : 1; + } dbg_dvbm_buf0_inf1; /* 0x00005178 reg5214 */ struct { - RK_U32 rdo_ctu_flg1 : 8; - RK_U32 jpeg_ctu_flag : 3; - RK_U32 lpf_ctu_flag : 1; - RK_U32 reserved : 4; - RK_U32 dma_brsp_idle : 1; - RK_U32 jpeg_frm_done : 1; - RK_U32 rdo_frm_done : 1; - RK_U32 lpf_frm_done : 1; - RK_U32 ent_frm_done : 1; - RK_U32 ppl_ctrl_done : 1; - RK_U32 reserved1 : 10; - } dbg_tctrl1; + RK_U32 dbg_bf1_isp_lcnt : 14; + RK_U32 dbg_bf1_isp_llst : 1; + RK_U32 dbg_bf1_isp_sofw : 1; + RK_U32 dbg_bf1_isp_fcnt : 1; + RK_U32 reserved : 7; + RK_U32 dbg_bf1_isp_pnt : 1; + RK_U32 reserved1 : 3; + RK_U32 dbg_bf1_vpu_pnt : 1; + RK_U32 reserved2 : 3; + } dbg_dvbm_buf1_inf0; /* 0x0000517c reg5215 */ struct { - RK_U32 criw_frm_done : 1; - RK_U32 meiw_frm_done : 1; - RK_U32 smiw_frm_done : 1; - RK_U32 strg_rsrc_done : 1; - RK_U32 reserved : 28; - } dbg_tctrl2; + RK_U32 dbg_bf1_src_lcnt : 14; + RK_U32 dbg_bf1_src_llst : 1; + RK_U32 reserved : 1; + RK_U32 dbg_bf1_vpu_lcnt : 14; + RK_U32 dbg_bf1_vpu_llst : 1; + RK_U32 dbg_bf1_vpu_vofw : 1; + } dbg_dvbm_buf1_inf1; - /* 0x5180 - 0x51fc */ - RK_U32 reserved5216_5247[32]; + /* 0x00005180 reg5216 */ + struct { + RK_U32 dbg_bf2_isp_lcnt : 14; + RK_U32 dbg_bf2_isp_llst : 1; + RK_U32 dbg_bf2_isp_sofw : 1; + RK_U32 dbg_bf2_isp_fcnt : 1; + RK_U32 reserved : 7; + RK_U32 dbg_bf2_isp_pnt : 1; + RK_U32 reserved1 : 3; + RK_U32 dbg_bf2_vpu_pnt : 1; + RK_U32 reserved2 : 3; + } dbg_dvbm_buf2_inf0; + + /* 0x00005184 reg5217 */ + struct { + RK_U32 dbg_bf2_src_lcnt : 14; + RK_U32 dbg_bf2_src_llst : 1; + RK_U32 reserved : 1; + RK_U32 dbg_bf2_vpu_lcnt : 14; + RK_U32 dbg_bf2_vpu_llst : 1; + RK_U32 dbg_bf2_vpu_vofw : 1; + } dbg_dvbm_buf2_inf1; + + /* 0x00005188 reg5218 */ + struct { + RK_U32 dbg_bf3_isp_lcnt : 14; + RK_U32 dbg_bf3_isp_llst : 1; + RK_U32 dbg_bf3_isp_sofw : 1; + RK_U32 dbg_bf3_isp_fcnt : 1; + RK_U32 reserved : 7; + RK_U32 dbg_bf3_isp_pnt : 1; + RK_U32 reserved1 : 3; + RK_U32 dbg_bf3_vpu_pnt : 1; + RK_U32 reserved2 : 3; + } dbg_dvbm_buf3_inf0; + + /* 0x0000518c reg5219 */ + struct { + RK_U32 dbg_bf3_src_lcnt : 14; + RK_U32 dbg_bf3_src_llst : 1; + RK_U32 reserved : 1; + RK_U32 dbg_bf3_vpu_lcnt : 14; + RK_U32 dbg_bf3_vpu_llst : 1; + RK_U32 dbg_bf3_vpu_vofw : 1; + } dbg_dvbm_buf3_inf1; + + /* 0x00005190 reg5220 */ + struct { + RK_U32 dbg_isp_fptr : 3; + RK_U32 dbg_isp_full : 1; + RK_U32 dbg_src_fptr : 3; + RK_U32 reserved : 1; + RK_U32 dbg_vpu_fptr : 3; + RK_U32 dbg_vpu_empt : 1; + RK_U32 dbg_vpu_lvld : 1; + RK_U32 dbg_vpu_lrdy : 1; + RK_U32 dbg_vpu_fvld : 1; + RK_U32 dbg_vpu_frdy : 1; + RK_U32 dbg_fcnt_misp : 4; + RK_U32 dbg_fcnt_mvpu : 4; + RK_U32 dbg_fcnt_sofw : 4; + RK_U32 dbg_fcnt_vofw : 4; + } dbg_dvbm_ctrl; + + /* 0x5194 - 0x519c */ + RK_U32 reserved5221_5223[3]; + + /* 0x000051a0 reg5224 */ + RK_U32 dbg_dvbm_buf0_yadr; + + /* 0x000051a4 reg5225 */ + RK_U32 dbg_dvbm_buf0_cadr; + + /* 0x000051a8 reg5226 */ + RK_U32 dbg_dvbm_buf1_yadr; + + /* 0x000051ac reg5227 */ + RK_U32 dbg_dvbm_buf1_cadr; + + /* 0x000051b0 reg5228 */ + RK_U32 dbg_dvbm_buf2_yadr; + + /* 0x000051b4 reg5229 */ + RK_U32 dbg_dvbm_buf2_cadr; + + /* 0x000051b8 reg5230 */ + RK_U32 dbg_dvbm_buf3_yadr; + + /* 0x000051bc reg5231 */ + RK_U32 dbg_dvbm_buf3_cadr; + + /* 0x000051c0 reg5232 */ + struct { + RK_U32 dchs_rx_cnt : 11; + RK_U32 dchs_rx_id : 2; + RK_U32 dchs_rx_en : 1; + RK_U32 dchs_rx_ack : 1; + RK_U32 dchs_rx_req : 1; + RK_U32 dchs_tx_cnt : 11; + RK_U32 dchs_tx_id : 2; + RK_U32 dchs_tx_en : 1; + RK_U32 dchs_tx_ack : 1; + RK_U32 dchs_tx_req : 1; + } dbg_dchs_intfc; + + /* 0x000051c4 reg5233 */ + struct { + RK_U32 lpfw_tx_cnt : 11; + RK_U32 lpfw_tx_en : 1; + RK_U32 crpw_tx_cnt : 11; + RK_U32 crpw_tx_en : 1; + RK_U32 dual_err_updt : 1; + RK_U32 dlyc_fifo_oflw : 1; + RK_U32 dlyc_tx_vld : 1; + RK_U32 dlyc_tx_rdy : 1; + RK_U32 dlyc_tx_empty : 1; + RK_U32 dchs_tx_idle : 1; + RK_U32 dchs_tx_asy : 1; + RK_U32 dchs_tx_syn : 1; + } dbg_dchs_tx_inf0; + + /* 0x000051c8 reg5234 */ + struct { + RK_U32 criw_tx_cnt : 11; + RK_U32 criw_tx_en : 1; + RK_U32 smrw_tx_cnt : 11; + RK_U32 smrw_tx_en : 1; + RK_U32 reserved : 8; + } dbg_dchs_tx_inf1; + + /* 0x000051cc reg5235 */ + struct { + RK_U32 dual_rx_cnt : 11; + RK_U32 dual_rx_id : 2; + RK_U32 dual_rx_en : 1; + RK_U32 dual_rx_syn : 1; + RK_U32 dual_rx_lock : 1; + RK_U32 dual_lpfr_dule : 1; + RK_U32 dual_cime_dule : 1; + RK_U32 dual_clomv_dule : 1; + RK_U32 dual_smear_dule : 1; + RK_U32 reserved : 12; + } dbg_dchs_rx_inf0; + + /* 0x51d0 - 0x51fc */ + RK_U32 reserved5236_5247[12]; /* 0x00005200 reg5248 */ RK_U32 frame_cyc; /* 0x00005204 reg5249 */ - RK_U32 pp0_fcyc; + RK_U32 vsp0_fcyc; /* 0x00005208 reg5250 */ - RK_U32 pp1_fcyc; + RK_U32 vsp1_fcyc; /* 0x0000520c reg5251 */ RK_U32 cme_fcyc; @@ -1563,109 +2169,13 @@ typedef struct Vepu510Dbg_t { RK_U32 etpy_fcyc; /* 0x00005228 reg5258 */ + RK_U32 jsp0_fcyc; + + /* 0x0000522c reg5259 */ + RK_U32 jsp1_fcyc; + + /* 0x00005230 reg5260 */ RK_U32 jpeg_fcyc; - - /* 0x522c - 0x52fc */ - RK_U32 reserved5259_5311[53]; - - /* 0x00005300 reg5312 */ - struct { - RK_U32 axip_e : 1; - RK_U32 axip_clr : 1; - RK_U32 axip_mod : 1; - RK_U32 reserved : 29; - } axip0_cmd; - - /* 0x00005304 reg5313 */ - struct { - RK_U32 axip_ltcy_id : 4; - RK_U32 axip_ltcy_thd : 12; - RK_U32 reserved : 16; - } axip0_ltcy; - - /* 0x00005308 reg5314 */ - struct { - RK_U32 axip_cnt_typ : 1; - RK_U32 axip_cnt_ddr : 2; - RK_U32 axip_cnt_rid : 5; - RK_U32 axip_cnt_wid : 5; - RK_U32 reserved : 19; - } axip0_cnt; - - /* 0x530c */ - RK_U32 reserved_5315; - - /* 0x00005310 reg5316 */ - struct { - RK_U32 axip_e : 1; - RK_U32 axip_clr : 1; - RK_U32 axip_mod : 1; - RK_U32 reserved : 29; - } axip1_cmd; - - /* 0x00005314 reg5317 */ - struct { - RK_U32 axip_ltcy_id : 4; - RK_U32 axip_ltcy_thd : 12; - RK_U32 reserved : 16; - } axip1_ltcy; - - /* 0x00005318 reg5318 */ - struct { - RK_U32 axip_cnt_typ : 1; - RK_U32 axip_cnt_ddr : 2; - RK_U32 axip_cnt_rid : 5; - RK_U32 axip_cnt_wid : 5; - RK_U32 reserved : 19; - } axip1_cnt; - - /* 0x531c */ - RK_U32 reserved_5319; - - /* 0x00005320 reg5320 */ - struct { - RK_U32 axip_max_ltcy : 16; - RK_U32 reserved : 16; - } st_axip0_maxl; - - /* 0x00005324 reg5321 */ - RK_U32 axip_num_ltcy; - - /* 0x00005328 reg5322 */ - RK_U32 axip_sum_ltcy; - - /* 0x0000532c reg5323 */ - RK_U32 axip_rbyt; - - /* 0x00005330 reg5324 */ - RK_U32 axip_wbyt; - - /* 0x00005334 reg5325 */ - RK_U32 axip_wrk_cyc; - - /* 0x5338 - 0x533c */ - RK_U32 reserved5326_5327[2]; - - /* 0x00005340 reg5328 */ - struct { - RK_U32 axip_max_ltcy : 16; - RK_U32 reserved : 16; - } st_axip1_maxl; - - /* 0x00005344 reg5329 */ - RK_U32 axip1_num_ltcy; - - /* 0x00005348 reg5330 */ - RK_U32 axip1_sum_ltcy; - - /* 0x0000534c reg5331 */ - RK_U32 axip1_rbyt; - - /* 0x00005350 reg5332 */ - RK_U32 axip1_wbyt; - - /* 0x00005354 reg5333 */ - RK_U32 axip1_wrk_cyc; } Vepu510Dbg; #ifdef __cplusplus diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c index 88555516..a2efbba2 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c +++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c @@ -565,8 +565,8 @@ static void setup_vepu510_normal(HalVepu510RegSet *regs) regs->reg_ctl.enc_strt.lkt_num = 0; regs->reg_ctl.enc_strt.vepu_cmd = 1; - regs->reg_ctl.func_en.cke = 1; - regs->reg_ctl.func_en.resetn_hw_en = 1; + regs->reg_ctl.opt_strg.cke = 1; + regs->reg_ctl.opt_strg.resetn_hw_en = 1; /* reg002 ENC_CLR */ regs->reg_ctl.enc_clr.safe_clr = 0; @@ -630,6 +630,7 @@ static void setup_vepu510_normal(HalVepu510RegSet *regs) static MPP_RET setup_vepu510_prep(HalVepu510RegSet *regs, MppEncPrepCfg *prep) { + H264eVepu510Frame *reg_frm = ®s->reg_frm; VepuFmtCfg cfg; MppFrameFormat fmt = prep->format; MPP_RET ret = vepu541_set_fmt(&cfg, fmt); @@ -643,17 +644,17 @@ static MPP_RET setup_vepu510_prep(HalVepu510RegSet *regs, MppEncPrepCfg *prep) if (ret) return ret; - regs->reg_frm.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; - regs->reg_frm.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; - regs->reg_frm.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; - regs->reg_frm.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; + reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; + reg_frm->common.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; + reg_frm->common.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; + reg_frm->common.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; regs->reg_ctl.dtrns_map.src_bus_edin = cfg.src_endian; - regs->reg_frm.src_fmt.src_cfmt = hw_fmt; - regs->reg_frm.src_fmt.alpha_swap = cfg.alpha_swap; - regs->reg_frm.src_fmt.rbuv_swap = cfg.rbuv_swap; - regs->reg_frm.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); + reg_frm->common.src_fmt.src_cfmt = hw_fmt; + reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap; + reg_frm->common.src_fmt.rbuv_swap = cfg.rbuv_swap; + reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); if (MPP_FRAME_FMT_IS_FBC(fmt)) { mpp_err("Unsupported FBC format input.\n"); @@ -717,57 +718,57 @@ static MPP_RET setup_vepu510_prep(HalVepu510RegSet *regs, MppEncPrepCfg *prep) hal_h264e_dbg_flow("input color range %d colorspace %d", prep->range, prep->color); - regs->reg_frm.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; - regs->reg_frm.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; - regs->reg_frm.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; + reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; + reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; + reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; - regs->reg_frm.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; - regs->reg_frm.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; - regs->reg_frm.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; + reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; + reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; + reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; - regs->reg_frm.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; - regs->reg_frm.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; - regs->reg_frm.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; + reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; + reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; + reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; - regs->reg_frm.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; - regs->reg_frm.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; - regs->reg_frm.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; + reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; + reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; + reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; hal_h264e_dbg_flow("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color); } else { - regs->reg_frm.src_udfy.csc_wgt_b2y = cfg.weight[0]; - regs->reg_frm.src_udfy.csc_wgt_g2y = cfg.weight[1]; - regs->reg_frm.src_udfy.csc_wgt_r2y = cfg.weight[2]; + reg_frm->common.src_udfy.csc_wgt_b2y = cfg.weight[0]; + reg_frm->common.src_udfy.csc_wgt_g2y = cfg.weight[1]; + reg_frm->common.src_udfy.csc_wgt_r2y = cfg.weight[2]; - regs->reg_frm.src_udfu.csc_wgt_b2u = cfg.weight[3]; - regs->reg_frm.src_udfu.csc_wgt_g2u = cfg.weight[4]; - regs->reg_frm.src_udfu.csc_wgt_r2u = cfg.weight[5]; + reg_frm->common.src_udfu.csc_wgt_b2u = cfg.weight[3]; + reg_frm->common.src_udfu.csc_wgt_g2u = cfg.weight[4]; + reg_frm->common.src_udfu.csc_wgt_r2u = cfg.weight[5]; - regs->reg_frm.src_udfv.csc_wgt_b2v = cfg.weight[6]; - regs->reg_frm.src_udfv.csc_wgt_g2v = cfg.weight[7]; - regs->reg_frm.src_udfv.csc_wgt_r2v = cfg.weight[8]; + reg_frm->common.src_udfv.csc_wgt_b2v = cfg.weight[6]; + reg_frm->common.src_udfv.csc_wgt_g2v = cfg.weight[7]; + reg_frm->common.src_udfv.csc_wgt_r2v = cfg.weight[8]; - regs->reg_frm.src_udfo.csc_ofst_y = cfg.offset[0]; - regs->reg_frm.src_udfo.csc_ofst_u = cfg.offset[1]; - regs->reg_frm.src_udfo.csc_ofst_v = cfg.offset[2]; + reg_frm->common.src_udfo.csc_ofst_y = cfg.offset[0]; + reg_frm->common.src_udfo.csc_ofst_u = cfg.offset[1]; + reg_frm->common.src_udfo.csc_ofst_v = cfg.offset[2]; } - regs->reg_frm.src_strd0.src_strd0 = y_stride; - regs->reg_frm.src_strd1.src_strd1 = c_stride; + reg_frm->common.src_strd0.src_strd0 = y_stride; + reg_frm->common.src_strd1.src_strd1 = c_stride; - regs->reg_frm.src_proc.src_mirr = prep->mirroring > 0; - regs->reg_frm.src_proc.src_rot = prep->rotation; + reg_frm->common.src_proc.src_mirr = prep->mirroring > 0; + reg_frm->common.src_proc.src_rot = prep->rotation; if (MPP_FRAME_FMT_IS_TILE(fmt)) - regs->reg_frm.src_proc.tile4x4_en = 1; + reg_frm->common.src_proc.tile4x4_en = 1; else - regs->reg_frm.src_proc.tile4x4_en = 0; + reg_frm->common.src_proc.tile4x4_en = 0; - regs->reg_frm.sli_cfg.mv_v_lmt_thd = 0; - regs->reg_frm.sli_cfg.mv_v_lmt_en = 0; + reg_frm->sli_cfg.mv_v_lmt_thd = 0; + reg_frm->sli_cfg.mv_v_lmt_en = 0; - regs->reg_frm.pic_ofst.pic_ofst_y = 0; - regs->reg_frm.pic_ofst.pic_ofst_x = 0; + reg_frm->common.pic_ofst.pic_ofst_y = 0; + reg_frm->common.pic_ofst.pic_ofst_x = 0; hal_h264e_dbg_func("leave\n"); @@ -776,6 +777,7 @@ static MPP_RET setup_vepu510_prep(HalVepu510RegSet *regs, MppEncPrepCfg *prep) static MPP_RET vepu510_h264e_save_pass1_patch(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx) { + H264eVepu510Frame *reg_frm = ®s->reg_frm; RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16); RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16); @@ -787,16 +789,16 @@ static MPP_RET vepu510_h264e_save_pass1_patch(HalVepu510RegSet *regs, HalH264eVe } } - regs->reg_frm.enc_pic.cur_frm_ref = 1; - regs->reg_frm.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); - regs->reg_frm.rfpw_b_addr = regs->reg_frm.rfpw_h_addr; - regs->reg_frm.enc_pic.rec_fbc_dis = 1; + reg_frm->common.enc_pic.cur_frm_ref = 1; + reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); + reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr; + reg_frm->common.enc_pic.rec_fbc_dis = 1; mpp_dev_multi_offset_update(ctx->offsets, 164, 0); /* NOTE: disable split to avoid lowdelay slice output */ - regs->reg_frm.sli_splt.sli_splt = 0; - regs->reg_frm.enc_pic.slen_fifo = 0; + reg_frm->common.sli_splt.sli_splt = 0; + reg_frm->common.enc_pic.slen_fifo = 0; return MPP_OK; } @@ -804,33 +806,34 @@ static MPP_RET vepu510_h264e_save_pass1_patch(HalVepu510RegSet *regs, HalH264eVe static MPP_RET vepu510_h264e_use_pass1_patch(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx) { MppEncPrepCfg *prep = &ctx->cfg->prep; + H264eVepu510Frame *reg_frm = ®s->reg_frm; RK_S32 fd_in = mpp_buffer_get_fd(ctx->buf_pass1); RK_S32 y_stride; RK_S32 c_stride; hal_h264e_dbg_func("enter\n"); - regs->reg_frm.src_fmt.src_cfmt = VEPU541_FMT_YUV420SP; - regs->reg_frm.src_fmt.alpha_swap = 0; - regs->reg_frm.src_fmt.rbuv_swap = 0; - regs->reg_frm.src_fmt.out_fmt = 1; - regs->reg_frm.src_fmt.src_rcne = 1; + reg_frm->common.src_fmt.src_cfmt = VEPU541_FMT_YUV420SP; + reg_frm->common.src_fmt.alpha_swap = 0; + reg_frm->common.src_fmt.rbuv_swap = 0; + reg_frm->common.src_fmt.out_fmt = 1; + reg_frm->common.src_fmt.src_rcne = 1; y_stride = MPP_ALIGN(prep->width, 16); c_stride = y_stride; - regs->reg_frm.src_strd0.src_strd0 = y_stride; - regs->reg_frm.src_strd1.src_strd1 = 3 * c_stride; + reg_frm->common.src_strd0.src_strd0 = y_stride; + reg_frm->common.src_strd1.src_strd1 = 3 * c_stride; - regs->reg_frm.src_proc.src_mirr = 0; - regs->reg_frm.src_proc.src_rot = 0; + reg_frm->common.src_proc.src_mirr = 0; + reg_frm->common.src_proc.src_rot = 0; - regs->reg_frm.pic_ofst.pic_ofst_y = 0; - regs->reg_frm.pic_ofst.pic_ofst_x = 0; + reg_frm->common.pic_ofst.pic_ofst_y = 0; + reg_frm->common.pic_ofst.pic_ofst_x = 0; - regs->reg_frm.adr_src0 = fd_in; - regs->reg_frm.adr_src1 = fd_in; - regs->reg_frm.adr_src2 = fd_in; + reg_frm->common.adr_src0 = fd_in; + reg_frm->common.adr_src1 = fd_in; + reg_frm->common.adr_src2 = fd_in; mpp_dev_multi_offset_update(ctx->offsets, 161, 2 * y_stride); @@ -841,42 +844,44 @@ static MPP_RET vepu510_h264e_use_pass1_patch(HalVepu510RegSet *regs, HalH264eVep static void setup_vepu510_codec(HalVepu510RegSet *regs, H264eSps *sps, H264ePps *pps, H264eSlice *slice) { + H264eVepu510Frame *reg_frm = ®s->reg_frm; + hal_h264e_dbg_func("enter\n"); - regs->reg_frm.enc_pic.enc_stnd = 0; - regs->reg_frm.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0; - regs->reg_frm.enc_pic.bs_scp = 1; + reg_frm->common.enc_pic.enc_stnd = 0; + reg_frm->common.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0; + reg_frm->common.enc_pic.bs_scp = 1; - regs->reg_frm.synt_nal.nal_ref_idc = slice->nal_reference_idc; - regs->reg_frm.synt_nal.nal_unit_type = slice->nalu_type; + reg_frm->synt_nal.nal_ref_idc = slice->nal_reference_idc; + reg_frm->synt_nal.nal_unit_type = slice->nalu_type; - regs->reg_frm.synt_sps.max_fnum = sps->log2_max_frame_num_minus4; - regs->reg_frm.synt_sps.drct_8x8 = sps->direct8x8_inference; - regs->reg_frm.synt_sps.mpoc_lm4 = sps->log2_max_poc_lsb_minus4; + reg_frm->synt_sps.max_fnum = sps->log2_max_frame_num_minus4; + reg_frm->synt_sps.drct_8x8 = sps->direct8x8_inference; + reg_frm->synt_sps.mpoc_lm4 = sps->log2_max_poc_lsb_minus4; - regs->reg_frm.synt_pps.etpy_mode = pps->entropy_coding_mode; - regs->reg_frm.synt_pps.trns_8x8 = pps->transform_8x8_mode; - regs->reg_frm.synt_pps.csip_flag = pps->constrained_intra_pred; - regs->reg_frm.synt_pps.num_ref0_idx = pps->num_ref_idx_l0_default_active - 1; - regs->reg_frm.synt_pps.num_ref1_idx = pps->num_ref_idx_l1_default_active - 1; - regs->reg_frm.synt_pps.pic_init_qp = pps->pic_init_qp; - regs->reg_frm.synt_pps.cb_ofst = pps->chroma_qp_index_offset; - regs->reg_frm.synt_pps.cr_ofst = pps->second_chroma_qp_index_offset; - regs->reg_frm.synt_pps.dbf_cp_flg = pps->deblocking_filter_control; + reg_frm->synt_pps.etpy_mode = pps->entropy_coding_mode; + reg_frm->synt_pps.trns_8x8 = pps->transform_8x8_mode; + reg_frm->synt_pps.csip_flag = pps->constrained_intra_pred; + reg_frm->synt_pps.num_ref0_idx = pps->num_ref_idx_l0_default_active - 1; + reg_frm->synt_pps.num_ref1_idx = pps->num_ref_idx_l1_default_active - 1; + reg_frm->synt_pps.pic_init_qp = pps->pic_init_qp; + reg_frm->synt_pps.cb_ofst = pps->chroma_qp_index_offset; + reg_frm->synt_pps.cr_ofst = pps->second_chroma_qp_index_offset; + reg_frm->synt_pps.dbf_cp_flg = pps->deblocking_filter_control; - regs->reg_frm.synt_sli0.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0); - regs->reg_frm.synt_sli0.pps_id = slice->pic_parameter_set_id; - regs->reg_frm.synt_sli0.drct_smvp = 0; - regs->reg_frm.synt_sli0.num_ref_ovrd = slice->num_ref_idx_override; - regs->reg_frm.synt_sli0.cbc_init_idc = slice->cabac_init_idc; - regs->reg_frm.synt_sli0.frm_num = slice->frame_num; + reg_frm->synt_sli0.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0); + reg_frm->synt_sli0.pps_id = slice->pic_parameter_set_id; + reg_frm->synt_sli0.drct_smvp = 0; + reg_frm->synt_sli0.num_ref_ovrd = slice->num_ref_idx_override; + reg_frm->synt_sli0.cbc_init_idc = slice->cabac_init_idc; + reg_frm->synt_sli0.frm_num = slice->frame_num; - regs->reg_frm.synt_sli1.idr_pid = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id : (RK_U32)(-1); - regs->reg_frm.synt_sli1.poc_lsb = slice->pic_order_cnt_lsb; + reg_frm->synt_sli1.idr_pid = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id : (RK_U32)(-1); + reg_frm->synt_sli1.poc_lsb = slice->pic_order_cnt_lsb; - regs->reg_frm.synt_sli2.dis_dblk_idc = slice->disable_deblocking_filter_idc; - regs->reg_frm.synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; + reg_frm->synt_sli2.dis_dblk_idc = slice->disable_deblocking_filter_idc; + reg_frm->synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; h264e_reorder_rd_rewind(slice->reorder); { /* reorder process */ @@ -884,16 +889,16 @@ static void setup_vepu510_codec(HalVepu510RegSet *regs, H264eSps *sps, MPP_RET ret = h264e_reorder_rd_op(slice->reorder, &rplmo); if (MPP_OK == ret) { - regs->reg_frm.synt_sli2.ref_list0_rodr = 1; - regs->reg_frm.synt_sli2.rodr_pic_idx = rplmo.modification_of_pic_nums_idc; + reg_frm->synt_sli2.ref_list0_rodr = 1; + reg_frm->synt_sli2.rodr_pic_idx = rplmo.modification_of_pic_nums_idc; switch (rplmo.modification_of_pic_nums_idc) { case 0 : case 1 : { - regs->reg_frm.synt_sli2.rodr_pic_num = rplmo.abs_diff_pic_num_minus1; + reg_frm->synt_sli2.rodr_pic_num = rplmo.abs_diff_pic_num_minus1; } break; case 2 : { - regs->reg_frm.synt_sli2.rodr_pic_num = rplmo.long_term_pic_idx; + reg_frm->synt_sli2.rodr_pic_num = rplmo.long_term_pic_idx; } break; default : { mpp_err_f("invalid modification_of_pic_nums_idc %d\n", @@ -902,38 +907,38 @@ static void setup_vepu510_codec(HalVepu510RegSet *regs, H264eSps *sps, } } else { // slice->ref_pic_list_modification_flag; - regs->reg_frm.synt_sli2.ref_list0_rodr = 0; - regs->reg_frm.synt_sli2.rodr_pic_idx = 0; - regs->reg_frm.synt_sli2.rodr_pic_num = 0; + reg_frm->synt_sli2.ref_list0_rodr = 0; + reg_frm->synt_sli2.rodr_pic_idx = 0; + reg_frm->synt_sli2.rodr_pic_num = 0; } } /* clear all mmco arg first */ - regs->reg_frm.synt_refm0.nopp_flg = 0; - regs->reg_frm.synt_refm0.ltrf_flg = 0; - regs->reg_frm.synt_refm0.arpm_flg = 0; - regs->reg_frm.synt_refm0.mmco4_pre = 0; - regs->reg_frm.synt_refm0.mmco_type0 = 0; - regs->reg_frm.synt_refm0.mmco_parm0 = 0; - regs->reg_frm.synt_refm0.mmco_type1 = 0; - regs->reg_frm.synt_refm1.mmco_parm1 = 0; - regs->reg_frm.synt_refm0.mmco_type2 = 0; - regs->reg_frm.synt_refm1.mmco_parm2 = 0; - regs->reg_frm.synt_refm2.long_term_frame_idx0 = 0; - regs->reg_frm.synt_refm2.long_term_frame_idx1 = 0; - regs->reg_frm.synt_refm2.long_term_frame_idx2 = 0; + reg_frm->synt_refm0.nopp_flg = 0; + reg_frm->synt_refm0.ltrf_flg = 0; + reg_frm->synt_refm0.arpm_flg = 0; + reg_frm->synt_refm0.mmco4_pre = 0; + reg_frm->synt_refm0.mmco_type0 = 0; + reg_frm->synt_refm0.mmco_parm0 = 0; + reg_frm->synt_refm0.mmco_type1 = 0; + reg_frm->synt_refm1.mmco_parm1 = 0; + reg_frm->synt_refm0.mmco_type2 = 0; + reg_frm->synt_refm1.mmco_parm2 = 0; + reg_frm->synt_refm2.long_term_frame_idx0 = 0; + reg_frm->synt_refm2.long_term_frame_idx1 = 0; + reg_frm->synt_refm2.long_term_frame_idx2 = 0; h264e_marking_rd_rewind(slice->marking); /* only update used parameter */ if (slice->slice_type == H264_I_SLICE) { - regs->reg_frm.synt_refm0.nopp_flg = slice->no_output_of_prior_pics; - regs->reg_frm.synt_refm0.ltrf_flg = slice->long_term_reference_flag; + reg_frm->synt_refm0.nopp_flg = slice->no_output_of_prior_pics; + reg_frm->synt_refm0.ltrf_flg = slice->long_term_reference_flag; } else { if (!h264e_marking_is_empty(slice->marking)) { H264eMmco mmco; - regs->reg_frm.synt_refm0.arpm_flg = 1; + reg_frm->synt_refm0.arpm_flg = 1; /* max 3 mmco */ do { @@ -968,9 +973,9 @@ static void setup_vepu510_codec(HalVepu510RegSet *regs, H264eSps *sps, } break; } - regs->reg_frm.synt_refm0.mmco_type0 = type; - regs->reg_frm.synt_refm0.mmco_parm0 = param_0; - regs->reg_frm.synt_refm2.long_term_frame_idx0 = param_1; + reg_frm->synt_refm0.mmco_type0 = type; + reg_frm->synt_refm0.mmco_parm0 = param_0; + reg_frm->synt_refm2.long_term_frame_idx0 = param_1; if (h264e_marking_is_empty(slice->marking)) break; @@ -1004,9 +1009,9 @@ static void setup_vepu510_codec(HalVepu510RegSet *regs, H264eSps *sps, } break; } - regs->reg_frm.synt_refm0.mmco_type1 = type; - regs->reg_frm.synt_refm1.mmco_parm1 = param_0; - regs->reg_frm.synt_refm2.long_term_frame_idx1 = param_1; + reg_frm->synt_refm0.mmco_type1 = type; + reg_frm->synt_refm1.mmco_parm1 = param_0; + reg_frm->synt_refm2.long_term_frame_idx1 = param_1; if (h264e_marking_is_empty(slice->marking)) break; @@ -1040,9 +1045,9 @@ static void setup_vepu510_codec(HalVepu510RegSet *regs, H264eSps *sps, } break; } - regs->reg_frm.synt_refm0.mmco_type2 = type; - regs->reg_frm.synt_refm1.mmco_parm2 = param_0; - regs->reg_frm.synt_refm2.long_term_frame_idx2 = param_1; + reg_frm->synt_refm0.mmco_type2 = type; + reg_frm->synt_refm1.mmco_parm2 = param_0; + reg_frm->synt_refm2.long_term_frame_idx2 = param_1; } while (0); } } @@ -1053,6 +1058,8 @@ static void setup_vepu510_codec(HalVepu510RegSet *regs, H264eSps *sps, static void setup_vepu510_rdo_pred(HalVepu510RegSet *regs, H264eSps *sps, H264ePps *pps, H264eSlice *slice) { + H264eVepu510Frame *reg_frm = ®s->reg_frm; + hal_h264e_dbg_func("enter\n"); if (slice->slice_type == H264_I_SLICE) { @@ -1061,79 +1068,78 @@ static void setup_vepu510_rdo_pred(HalVepu510RegSet *regs, H264eSps *sps, regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = 9; } - regs->reg_frm.rdo_cfg.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE && - sps->level_idc <= H264_LEVEL_3_0) ? 1 : 0; - regs->reg_frm.rdo_cfg.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) && - !pps->entropy_coding_mode; - regs->reg_frm.rdo_cfg.chrm_spcl = 1; - regs->reg_frm.rdo_cfg.ccwa_e = 1; - regs->reg_frm.rdo_cfg.scl_lst_sel = pps->pic_scaling_matrix_present; - regs->reg_frm.rdo_cfg.atf_e = 1; - regs->reg_frm.rdo_cfg.atr_e = 1; - regs->reg_frm.iprd_csts.rdo_mark_mode = 0x100; + reg_frm->rdo_cfg.rect_size = (sps->profile_idc == H264_PROFILE_BASELINE && + sps->level_idc <= H264_LEVEL_3_0) ? 1 : 0; + reg_frm->rdo_cfg.vlc_lmt = (sps->profile_idc < H264_PROFILE_MAIN) && + !pps->entropy_coding_mode; + reg_frm->rdo_cfg.chrm_spcl = 1; + reg_frm->rdo_cfg.ccwa_e = 1; + reg_frm->rdo_cfg.scl_lst_sel = pps->pic_scaling_matrix_present; + reg_frm->rdo_cfg.atf_e = 1; + reg_frm->rdo_cfg.atr_e = 1; + reg_frm->iprd_csts.rdo_mark_mode = 0x100; hal_h264e_dbg_func("leave\n"); } -static void setup_Vepu510Sqi(Vepu510Sqi *reg) +static void setup_vepu510_sqi(H264eVepu510Sqi *reg) { hal_h264e_dbg_func("enter\n"); - reg->rdo_smear_cfg_comb.rdo_smear_en = 0; - reg->rdo_smear_cfg_comb.rdo_smear_lvl16_multi = 9; - reg->rdo_smear_cfg_comb.rdo_smear_dlt_qp = 0 ; - reg->rdo_smear_cfg_comb.stated_mode = 0; + reg->smear_opt_cfg.rdo_smear_en = 0; + reg->smear_opt_cfg.rdo_smear_lvl16_multi = 9; + reg->smear_opt_cfg.rdo_smear_dlt_qp = 0 ; + reg->smear_opt_cfg.stated_mode = 0; - reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd0 = 0; - reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd1 = 24; - reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd2 = 48; - reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd3 = 64; - reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd0 = 16; - reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd1 = 32; - reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd2 = 48; - reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd3 = 96; - reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd4 = 48; - reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd5 = 24; - reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd0 = 96; - reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd1 = 48; + reg->rdo_smear_madp_thd0.rdo_smear_madp_cur_thd0 = 0; + reg->rdo_smear_madp_thd0.rdo_smear_madp_cur_thd1 = 24; + reg->rdo_smear_madp_thd1.rdo_smear_madp_cur_thd2 = 48; + reg->rdo_smear_madp_thd1.rdo_smear_madp_cur_thd3 = 64; + reg->rdo_smear_madp_thd2.rdo_smear_madp_around_thd0 = 16; + reg->rdo_smear_madp_thd2.rdo_smear_madp_around_thd1 = 32; + reg->rdo_smear_madp_thd3.rdo_smear_madp_around_thd2 = 48; + reg->rdo_smear_madp_thd3.rdo_smear_madp_around_thd3 = 96; + reg->rdo_smear_madp_thd4.rdo_smear_madp_around_thd4 = 48; + reg->rdo_smear_madp_thd4.rdo_smear_madp_around_thd5 = 24; + reg->rdo_smear_madp_thd5.rdo_smear_madp_ref_thd0 = 96; + reg->rdo_smear_madp_thd5.rdo_smear_madp_ref_thd1 = 48; - reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd0 = 1; - reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd1 = 3; - reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd2 = 1; - reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd3 = 3; - reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd0 = 1; - reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd1 = 4; - reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd2 = 1; - reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd3 = 4; - reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd4 = 0; - reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd5 = 3; - reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd6 = 0; - reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd7 = 3; - reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd0 = 1 ; - reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd1 = 3; + reg->rdo_smear_cnt_thd0.rdo_smear_cnt_cur_thd0 = 1; + reg->rdo_smear_cnt_thd0.rdo_smear_cnt_cur_thd1 = 3; + reg->rdo_smear_cnt_thd0.rdo_smear_cnt_cur_thd2 = 1; + reg->rdo_smear_cnt_thd0.rdo_smear_cnt_cur_thd3 = 3; + reg->rdo_smear_cnt_thd1.rdo_smear_cnt_around_thd0 = 1; + reg->rdo_smear_cnt_thd1.rdo_smear_cnt_around_thd1 = 4; + reg->rdo_smear_cnt_thd1.rdo_smear_cnt_around_thd2 = 1; + reg->rdo_smear_cnt_thd1.rdo_smear_cnt_around_thd3 = 4; + reg->rdo_smear_cnt_thd2.rdo_smear_cnt_around_thd4 = 0; + reg->rdo_smear_cnt_thd2.rdo_smear_cnt_around_thd5 = 3; + reg->rdo_smear_cnt_thd2.rdo_smear_cnt_around_thd6 = 0; + reg->rdo_smear_cnt_thd2.rdo_smear_cnt_around_thd7 = 3; + reg->rdo_smear_cnt_thd3.rdo_smear_cnt_ref_thd0 = 1 ; + reg->rdo_smear_cnt_thd3.rdo_smear_cnt_ref_thd1 = 3; - reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th0 = 6; - reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th0 = 9; - reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th1 = 6; - reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th1 = 9; - reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th0 = 6; - reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th0 = 11; - reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th1 = 6; - reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th1 = 8; - reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th2 = 9; - reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th2 = 20; - reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th3 = 6; - reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th3 = 20; - reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_small_ref_th0 = 7; - reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_big_ref_th0 = 16; + reg->rdo_smear_resi_thd0.rdo_smear_resi_small_cur_th0 = 6; + reg->rdo_smear_resi_thd0.rdo_smear_resi_big_cur_th0 = 9; + reg->rdo_smear_resi_thd0.rdo_smear_resi_small_cur_th1 = 6; + reg->rdo_smear_resi_thd0.rdo_smear_resi_big_cur_th1 = 9; + reg->rdo_smear_resi_thd1.rdo_smear_resi_small_around_th0 = 6; + reg->rdo_smear_resi_thd1.rdo_smear_resi_big_around_th0 = 11; + reg->rdo_smear_resi_thd1.rdo_smear_resi_small_around_th1 = 6; + reg->rdo_smear_resi_thd1.rdo_smear_resi_big_around_th1 = 8; + reg->rdo_smear_resi_thd2.rdo_smear_resi_small_around_th2 = 9; + reg->rdo_smear_resi_thd2.rdo_smear_resi_big_around_th2 = 20; + reg->rdo_smear_resi_thd2.rdo_smear_resi_small_around_th3 = 6; + reg->rdo_smear_resi_thd2.rdo_smear_resi_big_around_th3 = 20; + reg->rdo_smear_resi_thd3.rdo_smear_resi_small_ref_th0 = 7; + reg->rdo_smear_resi_thd3.rdo_smear_resi_big_ref_th0 = 16; + reg->rdo_smear_resi_thd4.rdo_smear_resi_th0 = 10; + reg->rdo_smear_resi_thd4.rdo_smear_resi_th1 = 6; - reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th0 = 10; - reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th1 = 6; - - reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th0 = 1; - reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th1 = 5; - reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th2 = 1; - reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th3 = 3; + reg->rdo_smear_st_thd.rdo_smear_madp_cnt_th0 = 1; + reg->rdo_smear_st_thd.rdo_smear_madp_cnt_th1 = 5; + reg->rdo_smear_st_thd.rdo_smear_madp_cnt_th2 = 1; + reg->rdo_smear_st_thd.rdo_smear_madp_cnt_th3 = 3; reg->rdo_b16_skip.atf_thd0.madp_thd0 = 1; reg->rdo_b16_skip.atf_thd0.madp_thd1 = 10; @@ -1161,14 +1167,14 @@ static void setup_Vepu510Sqi(Vepu510Sqi *reg) reg->rdo_b16_intra.atf_wgt.wgt2 = 20; reg->rdo_b16_intra.atf_wgt.wgt3 = 16; - reg->rdo_b16_intra_atf_cnt_thd_comb.thd0 = 1; - reg->rdo_b16_intra_atf_cnt_thd_comb.thd1 = 4; - reg->rdo_b16_intra_atf_cnt_thd_comb.thd2 = 1; - reg->rdo_b16_intra_atf_cnt_thd_comb.thd3 = 4; - reg->rdo_atf_resi_thd_comb.big_th0 = 16; - reg->rdo_atf_resi_thd_comb.big_th1 = 16; - reg->rdo_atf_resi_thd_comb.small_th0 = 8; - reg->rdo_atf_resi_thd_comb.small_th1 = 8; + reg->rdo_b16_intra_atf_cnt_thd.thd0 = 1; + reg->rdo_b16_intra_atf_cnt_thd.thd1 = 4; + reg->rdo_b16_intra_atf_cnt_thd.thd2 = 1; + reg->rdo_b16_intra_atf_cnt_thd.thd3 = 4; + reg->rdo_atf_resi_thd.big_th0 = 16; + reg->rdo_atf_resi_thd.big_th1 = 16; + reg->rdo_atf_resi_thd.small_th0 = 8; + reg->rdo_atf_resi_thd.small_th1 = 8; hal_h264e_dbg_func("leave\n"); } @@ -1182,6 +1188,7 @@ static void setup_vepu510_rc_base(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ct MppEncRcCfg *rc = &cfg->rc; MppEncHwCfg *hw = &cfg->hw; EncRcTaskInfo *rc_info = &rc_task->info; + H264eVepu510Frame *reg_frm = ®s->reg_frm; RK_S32 mb_w = sps->pic_width_in_mbs; RK_S32 mb_h = sps->pic_height_in_mbs; RK_U32 qp_target = rc_info->quality_target; @@ -1199,9 +1206,9 @@ static void setup_vepu510_rc_base(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ct hal_h264e_dbg_func("enter\n"); if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) { - regs->reg_frm.enc_pic.pic_qp = rc_info->quality_target; - regs->reg_frm.rc_qp.rc_max_qp = rc_info->quality_target; - regs->reg_frm.rc_qp.rc_min_qp = rc_info->quality_target; + reg_frm->common.enc_pic.pic_qp = rc_info->quality_target; + reg_frm->common.rc_qp.rc_max_qp = rc_info->quality_target; + reg_frm->common.rc_qp.rc_min_qp = rc_info->quality_target; return; } @@ -1213,18 +1220,17 @@ static void setup_vepu510_rc_base(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ct negative_bits_thd = 0 - 5 * mb_target_bits / 16; positive_bits_thd = 5 * mb_target_bits / 16; - regs->reg_frm.enc_pic.pic_qp = qp_target; + reg_frm->common.enc_pic.pic_qp = qp_target; - regs->reg_frm.rc_cfg.rc_en = 1; - regs->reg_frm.rc_cfg.aq_en = 1; - regs->reg_frm.rc_cfg.rc_ctu_num = mb_w; + reg_frm->common.rc_cfg.rc_en = 1; + reg_frm->common.rc_cfg.aq_en = 1; + reg_frm->common.rc_cfg.rc_ctu_num = mb_w; - regs->reg_frm.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ? - hw->qp_delta_row_i : hw->qp_delta_row; - regs->reg_frm.rc_qp.rc_max_qp = qp_max; - regs->reg_frm.rc_qp.rc_min_qp = qp_min; - - regs->reg_frm.rc_tgt.ctu_ebit = mb_target_bits_mul_16; + reg_frm->common.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ? + hw->qp_delta_row_i : hw->qp_delta_row; + reg_frm->common.rc_qp.rc_max_qp = qp_max; + reg_frm->common.rc_qp.rc_min_qp = qp_min; + reg_frm->common.rc_tgt.ctu_ebit = mb_target_bits_mul_16; regs->reg_rc_roi.rc_adj0.qp_adj0 = -2; regs->reg_rc_roi.rc_adj0.qp_adj1 = -1; @@ -1278,6 +1284,7 @@ static void setup_vepu510_io_buf(HalVepu510RegSet *regs, MppDevRegOffCfgs *offse MppBuffer buf_in = mpp_frame_get_buffer(frm); MppBuffer buf_out = task->output; MppFrameFormat fmt = mpp_frame_get_fmt(frm); + H264eVepu510Frame *reg_frm = ®s->reg_frm; RK_S32 hor_stride = mpp_frame_get_hor_stride(frm); RK_S32 ver_stride = mpp_frame_get_ver_stride(frm); RK_S32 fd_in = mpp_buffer_get_fd(buf_in); @@ -1288,19 +1295,19 @@ static void setup_vepu510_io_buf(HalVepu510RegSet *regs, MppDevRegOffCfgs *offse hal_h264e_dbg_func("enter\n"); - regs->reg_frm.adr_src0 = fd_in; - regs->reg_frm.adr_src1 = fd_in; - regs->reg_frm.adr_src2 = fd_in; + reg_frm->common.adr_src0 = fd_in; + reg_frm->common.adr_src1 = fd_in; + reg_frm->common.adr_src2 = fd_in; - regs->reg_frm.bsbt_addr = fd_out; - regs->reg_frm.bsbb_addr = fd_out; - regs->reg_frm.adr_bsbs = fd_out; - regs->reg_frm.bsbr_addr = fd_out; + reg_frm->common.bsbt_addr = fd_out; + reg_frm->common.bsbb_addr = fd_out; + reg_frm->common.adr_bsbs = fd_out; + reg_frm->common.bsbr_addr = fd_out; - regs->reg_frm.rfpt_h_addr = 0xffffffff; - regs->reg_frm.rfpb_h_addr = 0; - regs->reg_frm.rfpt_b_addr = 0xffffffff; - regs->reg_frm.adr_rfpb_b = 0; + reg_frm->common.rfpt_h_addr = 0xffffffff; + reg_frm->common.rfpb_h_addr = 0; + reg_frm->common.rfpt_b_addr = 0xffffffff; + reg_frm->common.adr_rfpb_b = 0; if (MPP_FRAME_FMT_IS_YUV(fmt)) { VepuFmtCfg cfg; @@ -1412,6 +1419,7 @@ static MPP_RET setup_vepu510_intra_refresh(HalVepu510RegSet *regs, HalH264eVepu5 RK_U32 w = mb_w * 16; RK_U32 h = mb_h * 16; MppEncROIRegion *region = NULL; + H264eVepu510Frame *reg_frm = ®s->reg_frm; RK_U32 refresh_num = ctx->cfg->rc.refresh_num; RK_U32 stride_h = MPP_ALIGN(mb_w, 4); RK_U32 stride_v = MPP_ALIGN(mb_h, 4); @@ -1460,7 +1468,7 @@ static MPP_RET setup_vepu510_intra_refresh(HalVepu510RegSet *regs, HalH264eVepu5 region->y = refresh_idx * 16 * refresh_num; region->h = 16 * refresh_num; } - regs->reg_frm.me_rnge.cime_srch_uph = 1; + reg_frm->common.me_rnge.cime_srch_uph = 1; } else if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_COL) { region->y = 0; region->h = h; @@ -1471,7 +1479,7 @@ static MPP_RET setup_vepu510_intra_refresh(HalVepu510RegSet *regs, HalH264eVepu5 region->x = refresh_idx * 16 * refresh_num; region->w = 16 * refresh_num; } - regs->reg_frm.me_rnge.cime_srch_dwnh = 1; + reg_frm->common.me_rnge.cime_srch_dwnh = 1; } region->intra = 1; @@ -1491,6 +1499,7 @@ RET: static void setup_vepu510_recn_refr(HalH264eVepu510Ctx *ctx, HalVepu510RegSet *regs) { + H264eVepu510Frame *reg_frm = ®s->reg_frm; H264eFrmInfo *frms = ctx->frms; HalBufs bufs = ctx->hw_recn; RK_S32 fbc_hdr_size = ctx->pixel_buf_fbc_hdr_size; @@ -1508,10 +1517,9 @@ static void setup_vepu510_recn_refr(HalH264eVepu510Ctx *ctx, HalVepu510RegSet *r mpp_assert(buf_pixel); mpp_assert(buf_thumb); - regs->reg_frm.rfpw_h_addr = fd; - regs->reg_frm.rfpw_b_addr = fd; - - regs->reg_frm.dspw_addr = mpp_buffer_get_fd(buf_thumb); + reg_frm->common.rfpw_h_addr = fd; + reg_frm->common.rfpw_b_addr = fd; + reg_frm->common.dspw_addr = mpp_buffer_get_fd(buf_thumb); } if (refr && refr->cnt) { @@ -1522,9 +1530,9 @@ static void setup_vepu510_recn_refr(HalH264eVepu510Ctx *ctx, HalVepu510RegSet *r mpp_assert(buf_pixel); mpp_assert(buf_thumb); - regs->reg_frm.rfpr_h_addr = fd; - regs->reg_frm.rfpr_b_addr = fd; - regs->reg_frm.dspr_addr = mpp_buffer_get_fd(buf_thumb); + reg_frm->common.rfpr_h_addr = fd; + reg_frm->common.rfpr_b_addr = fd; + reg_frm->common.dspr_addr = mpp_buffer_get_fd(buf_thumb); } mpp_dev_multi_offset_update(ctx->offsets, 164, fbc_hdr_size); mpp_dev_multi_offset_update(ctx->offsets, 166, fbc_hdr_size); @@ -1534,43 +1542,44 @@ static void setup_vepu510_recn_refr(HalH264eVepu510Ctx *ctx, HalVepu510RegSet *r static void setup_vepu510_split(HalVepu510RegSet *regs, MppEncCfgSet *enc_cfg) { + H264eVepu510Frame *reg_frm = ®s->reg_frm; MppEncSliceSplit *cfg = &enc_cfg->split; hal_h264e_dbg_func("enter\n"); switch (cfg->split_mode) { case MPP_ENC_SPLIT_NONE : { - regs->reg_frm.sli_splt.sli_splt = 0; - regs->reg_frm.sli_splt.sli_splt_mode = 0; - regs->reg_frm.sli_splt.sli_splt_cpst = 0; - regs->reg_frm.sli_splt.sli_max_num_m1 = 0; - regs->reg_frm.sli_splt.sli_flsh = 0; - regs->reg_frm.sli_cnum.sli_splt_cnum_m1 = 0; + reg_frm->common.sli_splt.sli_splt = 0; + reg_frm->common.sli_splt.sli_splt_mode = 0; + reg_frm->common.sli_splt.sli_splt_cpst = 0; + reg_frm->common.sli_splt.sli_max_num_m1 = 0; + reg_frm->common.sli_splt.sli_flsh = 0; + reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0; - regs->reg_frm.sli_byte.sli_splt_byte = 0; - regs->reg_frm.enc_pic.slen_fifo = 0; + reg_frm->common.sli_byte.sli_splt_byte = 0; + reg_frm->common.enc_pic.slen_fifo = 0; } break; case MPP_ENC_SPLIT_BY_BYTE : { - regs->reg_frm.sli_splt.sli_splt = 1; - regs->reg_frm.sli_splt.sli_splt_mode = 0; - regs->reg_frm.sli_splt.sli_splt_cpst = 0; - regs->reg_frm.sli_splt.sli_max_num_m1 = 500; - regs->reg_frm.sli_splt.sli_flsh = 1; - regs->reg_frm.sli_cnum.sli_splt_cnum_m1 = 0; + reg_frm->common.sli_splt.sli_splt = 1; + reg_frm->common.sli_splt.sli_splt_mode = 0; + reg_frm->common.sli_splt.sli_splt_cpst = 0; + reg_frm->common.sli_splt.sli_max_num_m1 = 500; + reg_frm->common.sli_splt.sli_flsh = 1; + reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0; - regs->reg_frm.sli_byte.sli_splt_byte = cfg->split_arg; - regs->reg_frm.enc_pic.slen_fifo = 0; + reg_frm->common.sli_byte.sli_splt_byte = cfg->split_arg; + reg_frm->common.enc_pic.slen_fifo = 0; } break; case MPP_ENC_SPLIT_BY_CTU : { - regs->reg_frm.sli_splt.sli_splt = 1; - regs->reg_frm.sli_splt.sli_splt_mode = 1; - regs->reg_frm.sli_splt.sli_splt_cpst = 0; - regs->reg_frm.sli_splt.sli_max_num_m1 = 500; - regs->reg_frm.sli_splt.sli_flsh = 1; - regs->reg_frm.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; + reg_frm->common.sli_splt.sli_splt = 1; + reg_frm->common.sli_splt.sli_splt_mode = 1; + reg_frm->common.sli_splt.sli_splt_cpst = 0; + reg_frm->common.sli_splt.sli_max_num_m1 = 500; + reg_frm->common.sli_splt.sli_flsh = 1; + reg_frm->common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; - regs->reg_frm.sli_byte.sli_splt_byte = 0; - regs->reg_frm.enc_pic.slen_fifo = 0; + reg_frm->common.sli_byte.sli_splt_byte = 0; + reg_frm->common.enc_pic.slen_fifo = 0; } break; default : { mpp_log_f("invalide slice split mode %d\n", cfg->split_mode); @@ -1583,21 +1592,23 @@ static void setup_vepu510_split(HalVepu510RegSet *regs, MppEncCfgSet *enc_cfg) static void setup_vepu510_me(HalVepu510RegSet *regs) { + H264eVepu510Frame *reg_frm = ®s->reg_frm; + hal_h264e_dbg_func("enter\n"); - regs->reg_frm.me_rnge.cime_srch_dwnh = 15; - regs->reg_frm.me_rnge.cime_srch_uph = 15; - regs->reg_frm.me_rnge.cime_srch_rgtw = 12; - regs->reg_frm.me_rnge.cime_srch_lftw = 12; - regs->reg_frm.me_cfg.rme_srch_h = 3; - regs->reg_frm.me_cfg.rme_srch_v = 3; + reg_frm->common.me_rnge.cime_srch_dwnh = 15; + reg_frm->common.me_rnge.cime_srch_uph = 15; + reg_frm->common.me_rnge.cime_srch_rgtw = 12; + reg_frm->common.me_rnge.cime_srch_lftw = 12; + reg_frm->common.me_cfg.rme_srch_h = 3; + reg_frm->common.me_cfg.rme_srch_v = 3; - regs->reg_frm.me_cfg.srgn_max_num = 54; - regs->reg_frm.me_cfg.cime_dist_thre = 1024; - regs->reg_frm.me_cfg.rme_dis = 0; - regs->reg_frm.me_cfg.fme_dis = 0; - regs->reg_frm.me_rnge.dlt_frm_num = 0x0; - regs->reg_frm.me_cach.cime_zero_thre = 64; + reg_frm->common.me_cfg.srgn_max_num = 54; + reg_frm->common.me_cfg.cime_dist_thre = 1024; + reg_frm->common.me_cfg.rme_dis = 0; + reg_frm->common.me_cfg.fme_dis = 0; + reg_frm->common.me_rnge.dlt_frm_num = 0x0; + reg_frm->common.me_cach.cime_zero_thre = 64; hal_h264e_dbg_func("leave\n"); } @@ -1631,11 +1642,11 @@ static void setup_vepu510_l2(HalVepu510RegSet *regs, H264eSlice *slice, MppEncHw memcpy(regs->reg_param.rdo_wgta_qp_grpa_0_51, &h264e_lambda_default[6], H264E_LAMBDA_TAB_SIZE); if (hw->qbias_en) { - regs->reg_param.RDO_QUANT.quant_f_bias_I = hw->qbias_i; - regs->reg_param.RDO_QUANT.quant_f_bias_P = hw->qbias_p; + regs->reg_param.qnt_bias_comb.qnt_f_bias_i = hw->qbias_i; + regs->reg_param.qnt_bias_comb.qnt_f_bias_p = hw->qbias_p; } else { - regs->reg_param.RDO_QUANT.quant_f_bias_I = 683; - regs->reg_param.RDO_QUANT.quant_f_bias_P = 341; + regs->reg_param.qnt_bias_comb.qnt_f_bias_i = 683; + regs->reg_param.qnt_bias_comb.qnt_f_bias_p = 341; } regs->reg_param.iprd_tthdy4_0.iprd_tthdy4_0 = 1; regs->reg_param.iprd_tthdy4_0.iprd_tthdy4_1 = 3; @@ -1675,40 +1686,40 @@ static void setup_vepu510_l2(HalVepu510RegSet *regs, H264eSlice *slice, MppEncHw regs->reg_param.iprd_wgtc8.iprd_wgtc8_3 = 19; if (slice->slice_type == H264_I_SLICE) { - regs->reg_param.ATR_THD0.atr_thd0 = 1; - regs->reg_param.ATR_THD0.atr_thd1 = 2; - regs->reg_param.ATR_THD1.atr_thd2 = 6; + regs->reg_param.atr_thd0.thd0 = 1; + regs->reg_param.atr_thd0.thd1 = 2; + regs->reg_param.atr_thd1.thd2 = 6; } else { - regs->reg_param.ATR_THD0.atr_thd0 = 2; - regs->reg_param.ATR_THD0.atr_thd1 = 4; - regs->reg_param.ATR_THD1.atr_thd2 = 9; + regs->reg_param.atr_thd0.thd0 = 2; + regs->reg_param.atr_thd0.thd1 = 4; + regs->reg_param.atr_thd1.thd2 = 9; } - regs->reg_param.ATR_THD1.atr_thdqp = 32; + regs->reg_param.atr_thd1.thdqp = 32; if (slice->slice_type == H264_I_SLICE) { - regs->reg_param.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 16; - regs->reg_param.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 16; - regs->reg_param.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16; + regs->reg_param.lvl16_atr_wgt.wgt0 = 16; + regs->reg_param.lvl16_atr_wgt.wgt1 = 16; + regs->reg_param.lvl16_atr_wgt.wgt2 = 16; - regs->reg_param.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 22; - regs->reg_param.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 21; - regs->reg_param.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 20; + regs->reg_param.lvl8_atr_wgt.wgt0 = 22; + regs->reg_param.lvl8_atr_wgt.wgt1 = 21; + regs->reg_param.lvl8_atr_wgt.wgt2 = 20; - regs->reg_param.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 20; - regs->reg_param.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 18; - regs->reg_param.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16; + regs->reg_param.lvl4_atr_wgt.wgt0 = 20; + regs->reg_param.lvl4_atr_wgt.wgt1 = 18; + regs->reg_param.lvl4_atr_wgt.wgt2 = 16; } else { - regs->reg_param.Lvl16_ATR_WGT.lvl16_atr_wgt0 = 25; - regs->reg_param.Lvl16_ATR_WGT.lvl16_atr_wgt1 = 20; - regs->reg_param.Lvl16_ATR_WGT.lvl16_atr_wgt2 = 16; + regs->reg_param.lvl16_atr_wgt.wgt0 = 25; + regs->reg_param.lvl16_atr_wgt.wgt1 = 20; + regs->reg_param.lvl16_atr_wgt.wgt2 = 16; - regs->reg_param.Lvl8_ATR_WGT.lvl8_atr_wgt0 = 25; - regs->reg_param.Lvl8_ATR_WGT.lvl8_atr_wgt1 = 20; - regs->reg_param.Lvl8_ATR_WGT.lvl8_atr_wgt2 = 18; + regs->reg_param.lvl8_atr_wgt.wgt0 = 25; + regs->reg_param.lvl8_atr_wgt.wgt1 = 20; + regs->reg_param.lvl8_atr_wgt.wgt2 = 18; - regs->reg_param.Lvl4_ATR_WGT.lvl4_atr_wgt0 = 25; - regs->reg_param.Lvl4_ATR_WGT.lvl4_atr_wgt1 = 20; - regs->reg_param.Lvl4_ATR_WGT.lvl4_atr_wgt2 = 16; + regs->reg_param.lvl4_atr_wgt.wgt0 = 25; + regs->reg_param.lvl4_atr_wgt.wgt1 = 20; + regs->reg_param.lvl4_atr_wgt.wgt2 = 16; } /* CIME */ { @@ -1722,40 +1733,40 @@ static void setup_vepu510_l2(HalVepu510RegSet *regs, H264eSlice *slice, MppEncHw regs->reg_param.me_sqi_comb.rime_prersu_en = 0; /* 0x1764 */ - regs->reg_param.cime_mvd_th.cime_mvd_th0 = 16; - regs->reg_param.cime_mvd_th.cime_mvd_th1 = 48; - regs->reg_param.cime_mvd_th.cime_mvd_th2 = 80; + regs->reg_param.cime_mvd_th_comb.cime_mvd_th0 = 16; + regs->reg_param.cime_mvd_th_comb.cime_mvd_th1 = 48; + regs->reg_param.cime_mvd_th_comb.cime_mvd_th2 = 80; /* 0x1768 */ - regs->reg_param.cime_madp_th.cime_madp_th = 16; + regs->reg_param.cime_madp_th_comb.cime_madp_th = 16; /* 0x176c */ - regs->reg_param.cime_multi.cime_multi0 = 8; - regs->reg_param.cime_multi.cime_multi1 = 12; - regs->reg_param.cime_multi.cime_multi2 = 16; - regs->reg_param.cime_multi.cime_multi3 = 20; + regs->reg_param.cime_multi_comb.cime_multi0 = 8; + regs->reg_param.cime_multi_comb.cime_multi1 = 12; + regs->reg_param.cime_multi_comb.cime_multi2 = 16; + regs->reg_param.cime_multi_comb.cime_multi3 = 20; } /* RIME && FME */ { /* 0x1770 */ - regs->reg_param.rime_mvd_th.rime_mvd_th0 = 1; - regs->reg_param.rime_mvd_th.rime_mvd_th1 = 2; - regs->reg_param.rime_mvd_th.fme_madp_th = 0; + regs->reg_param.rime_mvd_th_comb.rime_mvd_th0 = 1; + regs->reg_param.rime_mvd_th_comb.rime_mvd_th1 = 2; + regs->reg_param.rime_mvd_th_comb.fme_madp_th = 0; /* 0x1774 */ - regs->reg_param.rime_madp_th.rime_madp_th0 = 8; - regs->reg_param.rime_madp_th.rime_madp_th1 = 16; + regs->reg_param.rime_madp_th_comb.rime_madp_th0 = 8; + regs->reg_param.rime_madp_th_comb.rime_madp_th1 = 16; /* 0x1778 */ - regs->reg_param.rime_multi.rime_multi0 = 4; - regs->reg_param.rime_multi.rime_multi1 = 8; - regs->reg_param.rime_multi.rime_multi2 = 12; + regs->reg_param.rime_multi_comb.rime_multi0 = 4; + regs->reg_param.rime_multi_comb.rime_multi1 = 8; + regs->reg_param.rime_multi_comb.rime_multi2 = 12; /* 0x177C */ - regs->reg_param.cmv_st_th.cmv_th0 = 64; - regs->reg_param.cmv_st_th.cmv_th1 = 96; - regs->reg_param.cmv_st_th.cmv_th2 = 128; + regs->reg_param.cmv_st_th_comb.cmv_th0 = 64; + regs->reg_param.cmv_st_th_comb.cmv_th1 = 96; + regs->reg_param.cmv_st_th_comb.cmv_th2 = 128; } /* madi and madp */ { @@ -1821,21 +1832,22 @@ static void setup_vepu510_l2(HalVepu510RegSet *regs, H264eSlice *slice, MppEncHw static void setup_vepu510_ext_line_buf(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx) { + H264eVepu510Frame *reg_frm = ®s->reg_frm; MppDevRcbInfoCfg rcb_cfg; RK_S32 offset = 0; RK_S32 fd; if (!ctx->ext_line_buf) { - regs->reg_frm.ebufb_addr = 0; - regs->reg_frm.ebufb_addr = 0; + reg_frm->common.ebufb_addr = 0; + reg_frm->common.ebufb_addr = 0; return; } fd = mpp_buffer_get_fd(ctx->ext_line_buf); offset = ctx->ext_line_buf_size; - regs->reg_frm.ebuft_addr = fd; - regs->reg_frm.ebufb_addr = fd; + reg_frm->common.ebuft_addr = fd; + reg_frm->common.ebufb_addr = fd; mpp_dev_multi_offset_update(ctx->offsets, 178, offset); @@ -1853,7 +1865,7 @@ static void setup_vepu510_ext_line_buf(HalVepu510RegSet *regs, HalH264eVepu510Ct static MPP_RET setup_vepu510_dual_core(HalH264eVepu510Ctx *ctx, H264SliceType slice_type) { - Vepu510FrameCfg *reg_frm = &ctx->regs_set->reg_frm; + H264eVepu510Frame *reg_frm = &ctx->regs_set->reg_frm; RK_U32 dchs_ofst = 9; RK_U32 dchs_rxe = 1; RK_U32 dchs_dly = 0; @@ -1867,12 +1879,12 @@ static MPP_RET setup_vepu510_dual_core(HalH264eVepu510Ctx *ctx, H264SliceType sl dchs_rxe = 0; } - reg_frm->dual_core.dchs_txid = ctx->curr_idx; - reg_frm->dual_core.dchs_rxid = ctx->prev_idx; - reg_frm->dual_core.dchs_txe = 1; - reg_frm->dual_core.dchs_rxe = dchs_rxe; - reg_frm->dual_core.dchs_ofst = dchs_ofst; - reg_frm->dual_core.dchs_dly = dchs_dly; + reg_frm->common.dual_core.dchs_txid = ctx->curr_idx; + reg_frm->common.dual_core.dchs_rxid = ctx->prev_idx; + reg_frm->common.dual_core.dchs_txe = 1; + reg_frm->common.dual_core.dchs_rxe = dchs_rxe; + reg_frm->common.dual_core.dchs_ofst = dchs_ofst; + reg_frm->common.dual_core.dchs_dly = dchs_dly; ctx->prev_idx = ctx->curr_idx++; if (ctx->curr_idx > 3) @@ -1885,6 +1897,7 @@ static MPP_RET hal_h264e_vepu510_gen_regs(void *hal, HalEncTask *task) { HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal; HalVepu510RegSet *regs = ctx->regs_set; + H264eVepu510Frame *reg_frm = ®s->reg_frm; MppEncCfgSet *cfg = ctx->cfg; H264eSps *sps = ctx->sps; H264ePps *pps = ctx->pps; @@ -1908,17 +1921,17 @@ static MPP_RET hal_h264e_vepu510_gen_regs(void *hal, HalEncTask *task) setup_vepu510_dual_core(ctx, slice->slice_type); setup_vepu510_codec(regs, sps, pps, slice); setup_vepu510_rdo_pred(regs, sps, pps, slice); - setup_Vepu510Sqi(®s->reg_sqi); + setup_vepu510_sqi(®s->reg_sqi); setup_vepu510_rc_base(regs, ctx, rc_task); setup_vepu510_io_buf(regs, ctx->offsets, task); setup_vepu510_recn_refr(ctx, regs); - regs->reg_frm.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0; - regs->reg_frm.enc_pic.mei_stor = 0; + reg_frm->common.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0; + reg_frm->common.enc_pic.mei_stor = 0; - regs->reg_frm.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); - regs->reg_frm.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); + reg_frm->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); + reg_frm->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); setup_vepu510_split(regs, cfg); setup_vepu510_me(regs); diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h b/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h index d6e15467..55f9746a 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h +++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h @@ -9,669 +9,11 @@ #include "rk_type.h" #include "vepu510_common.h" -/* class: control/link */ -/* 0x00000000 reg0 - 0x00000120 reg72 */ -typedef struct Vepu510ControlCfg_t { - /* 0x00000000 reg0 */ - struct { - RK_U32 sub_ver : 8; - RK_U32 h264_cap : 1; - RK_U32 hevc_cap : 1; - RK_U32 reserved : 2; - RK_U32 res_cap : 4; - RK_U32 osd_cap : 2; - RK_U32 filtr_cap : 2; - RK_U32 bfrm_cap : 1; - RK_U32 fbc_cap : 2; - RK_U32 reserved1 : 1; - RK_U32 ip_id : 8; - } version; - - /* 0x00000004 - 0x0000000c */ - RK_U32 reserved1_3[3]; - - /* 0x00000010 reg4 */ - struct { - RK_U32 lkt_num : 8; - RK_U32 vepu_cmd : 3; - RK_U32 reserved : 21; - } enc_strt; - - /* 0x00000014 reg5 */ - struct { - RK_U32 safe_clr : 1; - RK_U32 force_clr : 1; - RK_U32 reserved : 30; - } enc_clr; - - /* 0x00000018 reg6 */ - struct { - RK_U32 vswm_lcnt_soft : 14; - RK_U32 vswm_fcnt_soft : 8; - RK_U32 reserved : 2; - RK_U32 dvbm_ack_soft : 1; - RK_U32 dvbm_ack_sel : 1; - RK_U32 dvbm_inf_sel : 1; - RK_U32 reserved1 : 5; - } vs_ldly; - - /* 0x0000001c */ - RK_U32 reserved_7; - - /* 0x00000020 reg8 */ - struct { - RK_U32 enc_done_en : 1; - RK_U32 lkt_node_done_en : 1; - RK_U32 sclr_done_en : 1; - RK_U32 vslc_done_en : 1; - RK_U32 vbsf_oflw_en : 1; - RK_U32 vbuf_lens_en : 1; - RK_U32 enc_err_en : 1; - RK_U32 vsrc_err_en : 1; - RK_U32 wdg_en : 1; - RK_U32 lkt_err_int_en : 1; - RK_U32 lkt_err_stop_en : 1; - RK_U32 lkt_force_stop_en : 1; - RK_U32 jslc_done_en : 1; - RK_U32 jbsf_oflw_en : 1; - RK_U32 jbuf_lens_en : 1; - RK_U32 dvbm_err_en : 1; - RK_U32 reserved : 16; - } int_en; - - /* 0x00000024 reg9 */ - struct { - RK_U32 enc_done_msk : 1; - RK_U32 lkt_node_done_msk : 1; - RK_U32 sclr_done_msk : 1; - RK_U32 vslc_done_msk : 1; - RK_U32 vbsf_oflw_msk : 1; - RK_U32 vbuf_lens_msk : 1; - RK_U32 enc_err_msk : 1; - RK_U32 vsrc_err_msk : 1; - RK_U32 wdg_msk : 1; - RK_U32 lkt_err_int_msk : 1; - RK_U32 lkt_err_stop_msk : 1; - RK_U32 lkt_force_stop_msk : 1; - RK_U32 jslc_done_msk : 1; - RK_U32 jbsf_oflw_msk : 1; - RK_U32 jbuf_lens_msk : 1; - RK_U32 dvbm_err_msk : 1; - RK_U32 reserved : 16; - } int_msk; - - /* 0x00000028 reg10 */ - struct { - RK_U32 enc_done_clr : 1; - RK_U32 lkt_node_done_clr : 1; - RK_U32 sclr_done_clr : 1; - RK_U32 vslc_done_clr : 1; - RK_U32 vbsf_oflw_clr : 1; - RK_U32 vbuf_lens_clr : 1; - RK_U32 enc_err_clr : 1; - RK_U32 vsrc_err_clr : 1; - RK_U32 wdg_clr : 1; - RK_U32 lkt_err_int_clr : 1; - RK_U32 lkt_err_stop_clr : 1; - RK_U32 lkt_force_stop_clr : 1; - RK_U32 jslc_done_clr : 1; - RK_U32 jbsf_oflw_clr : 1; - RK_U32 jbuf_lens_clr : 1; - RK_U32 dvbm_err_clr : 1; - RK_U32 reserved : 16; - } int_clr; - - /* 0x0000002c reg11 */ - struct { - RK_U32 enc_done_sta : 1; - RK_U32 lkt_node_done_sta : 1; - RK_U32 sclr_done_sta : 1; - RK_U32 vslc_done_sta : 1; - RK_U32 vbsf_oflw_sta : 1; - RK_U32 vbuf_lens_sta : 1; - RK_U32 enc_err_sta : 1; - RK_U32 vsrc_err_sta : 1; - RK_U32 wdg_sta : 1; - RK_U32 lkt_err_int_sta : 1; - RK_U32 lkt_err_stop_sta : 1; - RK_U32 lkt_force_stop_sta : 1; - RK_U32 jslc_done_sta : 1; - RK_U32 jbsf_oflw_sta : 1; - RK_U32 jbuf_lens_sta : 1; - RK_U32 dvbm_err_sta : 1; - RK_U32 reserved : 16; - } int_sta; - - /* 0x00000030 reg12 */ - struct { - RK_U32 jpeg_bus_edin : 4; - RK_U32 src_bus_edin : 4; - RK_U32 meiw_bus_edin : 4; - RK_U32 bsw_bus_edin : 4; - RK_U32 reserved : 8; - RK_U32 lktw_bus_edin : 4; - RK_U32 rec_nfbc_bus_edin : 4; - } dtrns_map; - - /* 0x00000034 reg13 */ - struct { - RK_U32 reserved : 16; - RK_U32 axi_brsp_cke : 10; - RK_U32 reserved1 : 6; - } dtrns_cfg; - - /* 0x00000038 reg14 */ - struct { - RK_U32 vs_load_thd : 24; - RK_U32 reserved : 8; - } enc_wdg; - - /* 0x0000003c - 0x0000004c */ - RK_U32 reserved15_19[5]; - - /* 0x00000050 reg20 */ - struct { - RK_U32 idle_en_core : 1; - RK_U32 idle_en_axi : 1; - RK_U32 idle_en_ahb : 1; - RK_U32 reserved : 29; - } enc_idle_en; - - /* 0x00000054 reg21 */ - struct { - RK_U32 cke : 1; - RK_U32 resetn_hw_en : 1; - RK_U32 rfpr_err_e : 1; - RK_U32 sram_ckg_en : 1; - RK_U32 link_err_stop : 1; - RK_U32 reserved : 27; - } func_en; - - /* 0x00000058 reg22 */ - struct { - RK_U32 tq8_ckg : 1; - RK_U32 tq4_ckg : 1; - RK_U32 bits_ckg_8x8 : 1; - RK_U32 bits_ckg_4x4_1 : 1; - RK_U32 bits_ckg_4x4_0 : 1; - RK_U32 inter_mode_ckg : 1; - RK_U32 inter_ctrl_ckg : 1; - RK_U32 inter_pred_ckg : 1; - RK_U32 intra8_ckg : 1; - RK_U32 intra4_ckg : 1; - RK_U32 reserved : 22; - } rdo_ckg; - - /* 0x0000005c reg23 */ - struct { - RK_U32 core_id : 2; - RK_U32 reserved : 30; - } core_id; - - /* 0x60 - 0x6c */ - RK_U32 reserved24_27[4]; - - /* 0x00000070 reg28 */ - struct { - RK_U32 reserved : 4; - RK_U32 lkt_addr : 28; - } lkt_base_addr; - - /* 0x00000074 reg29 */ - struct { - RK_U32 dvbm_en : 1; - RK_U32 src_badr_sel : 1; - RK_U32 vinf_frm_match : 1; - RK_U32 src_oflw_drop : 1; - RK_U32 dvbm_isp_cnct : 1; - RK_U32 dvbm_vepu_cnct : 1; - RK_U32 vepu_expt_type : 2; - RK_U32 vinf_dly_cycle : 8; - RK_U32 ybuf_full_mgn : 8; - RK_U32 ybuf_oflw_mgn : 8; - } dvbm_cfg; - - /* 0x00000078 reg30 */ - struct { - RK_U32 reserved : 4; - RK_U32 src_y_adr_str : 28; - } dvbm_y_sadr; - - /* 0x0000007c reg31 */ - struct { - RK_U32 reserved : 4; - RK_U32 src_c_adr_str : 28; - } dvbm_c_sadr; - - /* 0x00000080 reg32 */ - struct { - RK_U32 dvbm_y_line_strd : 21; - RK_U32 reserved : 11; - } dvbm_y_lstd; - - /* 0x84 */ - RK_U32 reserved_33; - - /* 0x00000088 reg34 */ - struct { - RK_U32 reserved : 4; - RK_U32 dvbm_y_frm_strd : 28; - } dvbm_y_fstd; - - /* 0x0000008c reg35 */ - struct { - RK_U32 reserved : 4; - RK_U32 dvbm_c_frm_strd : 28; - } dvbm_c_fstd; - - /* 0x00000090 reg36 */ - struct { - RK_U32 reserved : 4; - RK_U32 dvbm_y_top : 28; - } dvbm_y_top; - - /* 0x00000094 reg37 */ - struct { - RK_U32 reserved : 4; - RK_U32 dvbm_c_top : 28; - } dvbm_c_top; - - /* 0x00000098 reg38 */ - struct { - RK_U32 reserved : 4; - RK_U32 dvbm_y_botm : 28; - } dvbm_y_botm; - - /* 0x0000009c reg39 */ - struct { - RK_U32 reserved : 4; - RK_U32 dvbm_c_botm : 28; - } dvbm_c_botm; - - /* 0xa0 - 0xfc */ - RK_U32 reserved40_63[24]; - - /* 0x00000100 reg64 */ - struct { - RK_U32 node_core_id : 2; - RK_U32 node_int : 1; - RK_U32 reserved : 1; - RK_U32 task_id : 12; - RK_U32 reserved1 : 16; - } lkt_node_cfg; - - /* 0x00000104 reg65 */ - struct { - RK_U32 pcfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_pcfg : 28; - } lkt_addr_pcfg; - - /* 0x00000108 reg66 */ - struct { - RK_U32 rc_cfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_rc_cfg : 28; - } lkt_addr_rc_cfg; - - /* 0x0000010c reg67 */ - struct { - RK_U32 par_cfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_par_cfg : 28; - } lkt_addr_par_cfg; - - /* 0x00000110 reg68 */ - struct { - RK_U32 sqi_cfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_sqi_cfg : 28; - } lkt_addr_sqi_cfg; - - /* 0x00000114 reg69 */ - struct { - RK_U32 scal_cfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_scal_cfg : 28; - } lkt_addr_scal_cfg; - - /* 0x00000118 reg70 */ - struct { - RK_U32 pp_cfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_pp_cfg : 28; - } lkt_addr_osd_cfg; - - /* 0x0000011c reg71 */ - struct { - RK_U32 st_out_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_st : 28; - } lkt_addr_st; - - /* 0x00000120 reg72 */ - struct { - RK_U32 nxt_node_vld : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_nxt : 28; - } lkt_addr_nxt; -} Vepu510ControlCfg; - /* class: buffer/video syntax */ /* 0x00000270 reg156 - 0x000003f4 reg253*/ -typedef struct Vepu510FrameCfg_t { - /* 0x00000270 reg156 - 0x0000027c reg159 */ - vepu510_online online_addr; +typedef struct H264eVepu510Frame_t { - /* 0x00000280 reg160 4*/ - RK_U32 adr_src0; - - /* 0x00000284 reg161 5*/ - RK_U32 adr_src1; - - /* 0x00000288 reg162 6*/ - RK_U32 adr_src2; - - /* 0x0000028c reg163 7*/ - RK_U32 rfpw_h_addr; - - /* 0x00000290 reg164 8*/ - RK_U32 rfpw_b_addr; - - /* 0x00000294 reg165 9*/ - RK_U32 rfpr_h_addr; - - /* 0x00000298 reg166 10*/ - RK_U32 rfpr_b_addr; - - /* 0x0000029c reg167 11*/ - RK_U32 colmvw_addr; - - /* 0x000002a0 reg168 12*/ - RK_U32 colmvr_addr; - - /* 0x000002a4 reg169 13*/ - RK_U32 dspw_addr; - - /* 0x000002a8 reg170 14*/ - RK_U32 dspr_addr; - - /* 0x000002ac reg171 15*/ - RK_U32 meiw_addr; - - /* 0x000002b0 reg172 16*/ - RK_U32 bsbt_addr; - - /* 0x000002b4 reg173 17*/ - RK_U32 bsbb_addr; - - /* 0x000002b8 reg174 18*/ - RK_U32 adr_bsbs; - - /* 0x000002bc reg175 19*/ - RK_U32 bsbr_addr; - - /* 0x000002c0 reg176 20*/ - RK_U32 lpfw_addr; - - /* 0x000002c4 reg177 21*/ - RK_U32 lpfr_addr; - - /* 0x000002c8 reg178 22*/ - RK_U32 ebuft_addr; - - /* 0x000002cc reg179 23*/ - RK_U32 ebufb_addr; - - /* 0x000002d0 reg180 */ - RK_U32 rfpt_h_addr; - - /* 0x000002d4 reg181 */ - RK_U32 rfpb_h_addr; - - /* 0x000002d8 reg182 */ - RK_U32 rfpt_b_addr; - - /* 0x000002dc reg183 */ - RK_U32 adr_rfpb_b; - - /* 0x000002e0 reg184 */ - RK_U32 adr_smear_rd; - - /* 0x000002e4 reg185 */ - RK_U32 adr_smear_wr; - - /* 0x000002e8 reg186 */ - RK_U32 adr_roir; - - /* 0x2ec - 0x2fc */ - RK_U32 reserved187_191[5]; - - /* 0x00000300 reg192 */ - struct { - RK_U32 enc_stnd : 2; - RK_U32 cur_frm_ref : 1; - RK_U32 mei_stor : 1; - RK_U32 bs_scp : 1; - RK_U32 reserved : 3; - RK_U32 pic_qp : 6; - RK_U32 num_pic_tot_cur_hevc : 5; - RK_U32 log2_ctu_num_hevc : 5; - RK_U32 reserved1 : 6; - RK_U32 slen_fifo : 1; - RK_U32 rec_fbc_dis : 1; - } enc_pic; - - /* 0x00000304 reg193 */ - struct { - RK_U32 dchs_txid : 2; - RK_U32 dchs_rxid : 2; - RK_U32 dchs_txe : 1; - RK_U32 dchs_rxe : 1; - RK_U32 reserved : 2; - RK_U32 dchs_dly : 8; - RK_U32 dchs_ofst : 10; - RK_U32 reserved1 : 6; - } dual_core; - - /* 0x00000308 reg194 */ - struct { - RK_U32 frame_id : 8; - RK_U32 frm_id_match : 1; - RK_U32 reserved : 7; - RK_U32 ch_id : 2; - RK_U32 vrsp_rtn_en : 1; - RK_U32 vinf_req_en : 1; - RK_U32 reserved1 : 12; - } enc_id; - - /* 0x0000030c reg195 */ - RK_U32 bsp_size; - - /* 0x00000310 reg196 */ - struct { - RK_U32 pic_wd8_m1 : 11; - RK_U32 reserved : 5; - RK_U32 pic_hd8_m1 : 11; - RK_U32 reserved1 : 5; - } enc_rsl; - - /* 0x00000314 reg197 */ - struct { - RK_U32 pic_wfill : 6; - RK_U32 reserved : 10; - RK_U32 pic_hfill : 6; - RK_U32 reserved1 : 10; - } src_fill; - - /* 0x00000318 reg198 */ - struct { - RK_U32 alpha_swap : 1; - RK_U32 rbuv_swap : 1; - RK_U32 src_cfmt : 4; - RK_U32 src_rcne : 1; - RK_U32 out_fmt : 1; - RK_U32 src_range_trns_en : 1; - RK_U32 src_range_trns_sel : 1; - RK_U32 chroma_ds_mode : 1; - RK_U32 reserved : 21; - } src_fmt; - - /* 0x0000031c reg199 */ - struct { - RK_U32 csc_wgt_b2y : 9; - RK_U32 csc_wgt_g2y : 9; - RK_U32 csc_wgt_r2y : 9; - RK_U32 reserved : 5; - } src_udfy; - - /* 0x00000320 reg200 */ - struct { - RK_U32 csc_wgt_b2u : 9; - RK_U32 csc_wgt_g2u : 9; - RK_U32 csc_wgt_r2u : 9; - RK_U32 reserved : 5; - } src_udfu; - - /* 0x00000324 reg201 */ - struct { - RK_U32 csc_wgt_b2v : 9; - RK_U32 csc_wgt_g2v : 9; - RK_U32 csc_wgt_r2v : 9; - RK_U32 reserved : 5; - } src_udfv; - - /* 0x00000328 reg202 */ - struct { - RK_U32 csc_ofst_v : 8; - RK_U32 csc_ofst_u : 8; - RK_U32 csc_ofst_y : 5; - RK_U32 reserved : 11; - } src_udfo; - - /* 0x0000032c reg203 */ - struct { - RK_U32 cr_force_value : 8; - RK_U32 cb_force_value : 8; - RK_U32 chroma_force_en : 1; - RK_U32 reserved : 9; - RK_U32 src_mirr : 1; - RK_U32 src_rot : 2; - RK_U32 tile4x4_en : 1; - RK_U32 reserved1 : 2; - } src_proc; - - /* 0x00000330 reg204 */ - struct { - RK_U32 pic_ofst_x : 14; - RK_U32 reserved : 2; - RK_U32 pic_ofst_y : 14; - RK_U32 reserved1 : 2; - } pic_ofst; - - /* 0x00000334 reg205 */ - struct { - RK_U32 src_strd0 : 21; - RK_U32 reserved : 11; - } src_strd0; - - /* 0x00000338 reg206 */ - struct { - RK_U32 src_strd1 : 16; - RK_U32 reserved : 16; - } src_strd1; - - /* 0x33c - 0x34c */ - RK_U32 reserved207_211[5]; - - /* 0x00000350 reg212 */ - struct { - RK_U32 rc_en : 1; - RK_U32 aq_en : 1; - RK_U32 reserved : 10; - RK_U32 rc_ctu_num : 20; - } rc_cfg; - - /* 0x00000354 reg213 */ - struct { - RK_U32 reserved : 16; - RK_U32 rc_qp_range : 4; - RK_U32 rc_max_qp : 6; - RK_U32 rc_min_qp : 6; - } rc_qp; - - /* 0x00000358 reg214 */ - struct { - RK_U32 ctu_ebit : 20; - RK_U32 reserved : 12; - } rc_tgt; - - /* 0x35c */ - RK_U32 reserved_215; - - /* 0x00000360 reg216 */ - struct { - RK_U32 sli_splt : 1; - RK_U32 sli_splt_mode : 1; - RK_U32 sli_splt_cpst : 1; - RK_U32 reserved : 12; - RK_U32 sli_flsh : 1; - RK_U32 sli_max_num_m1 : 15; - RK_U32 reserved1 : 1; - } sli_splt; - - /* 0x00000364 reg217 */ - struct { - RK_U32 sli_splt_byte : 20; - RK_U32 reserved : 12; - } sli_byte; - - /* 0x00000368 reg218 */ - struct { - RK_U32 sli_splt_cnum_m1 : 20; - RK_U32 reserved : 12; - } sli_cnum; - - /* 0x0000036c reg219 */ - struct { - RK_U32 uvc_partition0_len : 12; - RK_U32 uvc_partition_len : 12; - RK_U32 uvc_skip_len : 6; - RK_U32 reserved : 2; - } vbs_pad; - - /* 0x00000370 reg220 */ - struct { - RK_U32 cime_srch_dwnh : 4; - RK_U32 cime_srch_uph : 4; - RK_U32 cime_srch_rgtw : 4; - RK_U32 cime_srch_lftw : 4; - RK_U32 dlt_frm_num : 16; - } me_rnge; - - /* 0x00000374 reg221 */ - struct { - RK_U32 srgn_max_num : 7; - RK_U32 cime_dist_thre : 13; - RK_U32 rme_srch_h : 2; - RK_U32 rme_srch_v : 2; - RK_U32 rme_dis : 3; - RK_U32 reserved : 1; - RK_U32 fme_dis : 3; - RK_U32 reserved1 : 1; - } me_cfg; - - /* 0x00000378 reg222 */ - struct { - RK_U32 cime_zero_thre : 13; - RK_U32 reserved : 15; - RK_U32 fme_prefsu_en : 2; - RK_U32 colmv_stor_hevc : 1; - RK_U32 colmv_load_hevc : 1; - } me_cach; - - /* 0x37c - 0x39c */ - RK_U32 reserved223_231[9]; + Vepu510FrmCommon common; /* 0x000003a0 reg232 */ struct { @@ -827,196 +169,12 @@ typedef struct Vepu510FrameCfg_t { RK_U32 reserved : 7; RK_U32 tile_y : 9; RK_U32 reserved1 : 7; - } tile_pos; -} Vepu510FrameCfg; + } tile_pos_hevc; +} H264eVepu510Frame; -/* class: rc/roi/aq/klut */ -/* 0x00001000 reg1024 - 0x0000110c reg1091 */ -typedef struct Vepu510RcRoiCfg_t { - /* 0x00001000 reg1024 */ - struct { - RK_U32 qp_adj0 : 5; - RK_U32 qp_adj1 : 5; - RK_U32 qp_adj2 : 5; - RK_U32 qp_adj3 : 5; - RK_U32 qp_adj4 : 5; - RK_U32 reserved : 7; - } rc_adj0; - - /* 0x00001004 reg1025 */ - struct { - RK_U32 qp_adj5 : 5; - RK_U32 qp_adj6 : 5; - RK_U32 qp_adj7 : 5; - RK_U32 qp_adj8 : 5; - RK_U32 reserved : 12; - } rc_adj1; - - /* 0x00001008 reg1026 - 0x00001028 reg1034 */ - RK_U32 rc_dthd_0_8[9]; - - /* 0x102c */ - RK_U32 reserved_1035; - - /* 0x00001030 reg1036 */ - struct { - RK_U32 qpmin_area0 : 6; - RK_U32 qpmax_area0 : 6; - RK_U32 qpmin_area1 : 6; - RK_U32 qpmax_area1 : 6; - RK_U32 qpmin_area2 : 6; - RK_U32 reserved : 2; - } roi_qthd0; - - /* 0x00001034 reg1037 */ - struct { - RK_U32 qpmax_area2 : 6; - RK_U32 qpmin_area3 : 6; - RK_U32 qpmax_area3 : 6; - RK_U32 qpmin_area4 : 6; - RK_U32 qpmax_area4 : 6; - RK_U32 reserved : 2; - } roi_qthd1; - - /* 0x00001038 reg1038 */ - struct { - RK_U32 qpmin_area5 : 6; - RK_U32 qpmax_area5 : 6; - RK_U32 qpmin_area6 : 6; - RK_U32 qpmax_area6 : 6; - RK_U32 qpmin_area7 : 6; - RK_U32 reserved : 2; - } roi_qthd2; - - /* 0x0000103c reg1039 */ - struct { - RK_U32 qpmax_area7 : 6; - RK_U32 reserved : 24; - RK_U32 qpmap_mode : 2; - } roi_qthd3; - - /* 0x1040 */ - RK_U32 reserved_1040; - - /* 0x00001044 reg1041 */ - struct { - RK_U32 aq_tthd0 : 8; - RK_U32 aq_tthd1 : 8; - RK_U32 aq_tthd2 : 8; - RK_U32 aq_tthd3 : 8; - } aq_tthd0; - - /* 0x00001048 reg1042 */ - struct { - RK_U32 aq_tthd4 : 8; - RK_U32 aq_tthd5 : 8; - RK_U32 aq_tthd6 : 8; - RK_U32 aq_tthd7 : 8; - } aq_tthd1; - - /* 0x0000104c reg1043 */ - struct { - RK_U32 aq_tthd8 : 8; - RK_U32 aq_tthd9 : 8; - RK_U32 aq_tthd10 : 8; - RK_U32 aq_tthd11 : 8; - } aq_tthd2; - - /* 0x00001050 reg1044 */ - struct { - RK_U32 aq_tthd12 : 8; - RK_U32 aq_tthd13 : 8; - RK_U32 aq_tthd14 : 8; - RK_U32 aq_tthd15 : 8; - } aq_tthd3; - - /* 0x00001054 reg1045 */ - struct { - RK_U32 aq_stp_s0 : 5; - RK_U32 aq_stp_0t1 : 5; - RK_U32 aq_stp_1t2 : 5; - RK_U32 aq_stp_2t3 : 5; - RK_U32 aq_stp_3t4 : 5; - RK_U32 aq_stp_4t5 : 5; - RK_U32 reserved : 2; - } aq_stp0; - - /* 0x00001058 reg1046 */ - struct { - RK_U32 aq_stp_5t6 : 5; - RK_U32 aq_stp_6t7 : 5; - RK_U32 aq_stp_7t8 : 5; - RK_U32 aq_stp_8t9 : 5; - RK_U32 aq_stp_9t10 : 5; - RK_U32 aq_stp_10t11 : 5; - RK_U32 reserved : 2; - } aq_stp1; - - /* 0x0000105c reg1047 */ - struct { - RK_U32 aq_stp_11t12 : 5; - RK_U32 aq_stp_12t13 : 5; - RK_U32 aq_stp_13t14 : 5; - RK_U32 aq_stp_14t15 : 5; - RK_U32 aq_stp_b15 : 5; - RK_U32 reserved : 7; - } aq_stp2; - - /* 0x00001060 reg1048 */ - struct { - RK_U32 aq16_rnge : 4; - RK_U32 aq32_rnge : 4; - RK_U32 aq8_rnge : 5; - RK_U32 aq16_dif0 : 5; - RK_U32 aq16_dif1 : 5; - RK_U32 reserved : 1; - RK_U32 aq_cme_en : 1; - RK_U32 aq_subj_cme_en : 1; - RK_U32 aq_rme_en : 1; - RK_U32 aq_subj_rme_en : 1; - RK_U32 reserved1 : 4; - } aq_clip; - - /* 0x00001064 reg1049 */ - struct { - RK_U32 madi_th0 : 8; - RK_U32 madi_th1 : 8; - RK_U32 madi_th2 : 8; - RK_U32 reserved : 8; - } madi_st_thd; - - /* 0x00001068 reg1050 */ - struct { - RK_U32 madp_th0 : 12; - RK_U32 reserved : 4; - RK_U32 madp_th1 : 12; - RK_U32 reserved1 : 4; - } madp_st_thd0; - - /* 0x0000106c reg1051 */ - struct { - RK_U32 madp_th2 : 12; - RK_U32 reserved : 20; - } madp_st_thd1; - - /* 0x1070 - 0x1078 */ - RK_U32 reserved1052_1054[3]; - - /* 0x0000107c reg1055 */ - struct { - RK_U32 chrm_klut_ofst : 4; - RK_U32 reserved : 4; - RK_U32 inter_chrm_dist_multi_hevc : 6; - RK_U32 reserved1 : 18; - } klut_ofst; - - /* 0x00001080 reg1056 - - 0x0000110c reg1091 */ - Vepu510RoiCfg roi_cfg; -} Vepu510RcRoiCfg; - -/* class: iprd/iprd_wgt/rdo_wgta/prei_dif/sobel */ -/* 0x00001700 reg1472 -0x000019cc reg1651 */ -typedef struct Vepu510Param_t { +/* class: param */ +/* 0x00001700 reg1472 - 0x000019cc reg1651 */ +typedef struct H264eVepu510Param_t { /* 0x00001700 reg1472 */ struct { RK_U32 iprd_tthdy4_0 : 12; @@ -1108,55 +266,56 @@ typedef struct Vepu510Param_t { /* 0x00001730 reg1484 */ struct { - RK_U32 quant_f_bias_I : 10; - RK_U32 quant_f_bias_P : 10; - RK_U32 reserve : 12; - } RDO_QUANT; + RK_U32 qnt_f_bias_i : 10; + RK_U32 qnt_f_bias_p : 10; + RK_U32 reserve : 12; + } qnt_bias_comb; /* 0x1734 - 0x173c */ RK_U32 reserved1485_1487[3]; /* 0x00001740 reg1488 */ struct { - RK_U32 atr_thd0 : 12; - RK_U32 reserve0 : 4; - RK_U32 atr_thd1 : 12; - RK_U32 reserve1 : 4; - } ATR_THD0; + RK_U32 thd0 : 8; + RK_U32 reserve0 : 8; + RK_U32 thd1 : 8; + RK_U32 reserve1 : 8; + } atr_thd0; + /* 0x00001744 reg1489 */ struct { - RK_U32 atr_thd2 : 12; - RK_U32 reserve0 : 4; - RK_U32 atr_thdqp : 6; - RK_U32 reserve1 : 10; - } ATR_THD1; + RK_U32 thd2 : 8; + RK_U32 reserve0 : 8; + RK_U32 thdqp : 6; + RK_U32 reserve1 : 10; + } atr_thd1; /* 0x1748 - 0x174c */ RK_U32 reserved1490_1491[2]; /* 0x00001750 reg1492 */ struct { - RK_U32 lvl16_atr_wgt0 : 8; - RK_U32 lvl16_atr_wgt1 : 8; - RK_U32 lvl16_atr_wgt2 : 8; - RK_U32 reserved : 8; - } Lvl16_ATR_WGT; + RK_U32 wgt0 : 8; + RK_U32 wgt1 : 8; + RK_U32 wgt2 : 8; + RK_U32 reserved : 8; + } lvl16_atr_wgt; /* 0x00001754 reg1493*/ struct { - RK_U32 lvl8_atr_wgt0 : 8; - RK_U32 lvl8_atr_wgt1 : 8; - RK_U32 lvl8_atr_wgt2 : 8; - RK_U32 reserved : 8; - } Lvl8_ATR_WGT; + RK_U32 wgt0 : 8; + RK_U32 wgt1 : 8; + RK_U32 wgt2 : 8; + RK_U32 reserved : 8; + } lvl8_atr_wgt; /* 0x00001758 reg1494 */ struct { - RK_U32 lvl4_atr_wgt0 : 8; - RK_U32 lvl4_atr_wgt1 : 8; - RK_U32 lvl4_atr_wgt2 : 8; - RK_U32 reserved : 8; - } Lvl4_ATR_WGT; + RK_U32 wgt0 : 8; + RK_U32 wgt1 : 8; + RK_U32 wgt2 : 8; + RK_U32 reserved : 8; + } lvl4_atr_wgt; /* 0x175c */ RK_U32 reserved_1495; @@ -1182,13 +341,13 @@ typedef struct Vepu510Param_t { RK_U32 reserved1 : 1; RK_U32 cime_mvd_th2 : 9; RK_U32 reserved2 : 3; - } cime_mvd_th; + } cime_mvd_th_comb; /* 0x00001768 reg1498 */ struct { RK_U32 cime_madp_th : 12; RK_U32 reserved : 20; - } cime_madp_th; + } cime_madp_th_comb; /* 0x0000176c reg1499 */ struct { @@ -1196,7 +355,7 @@ typedef struct Vepu510Param_t { RK_U32 cime_multi1 : 8; RK_U32 cime_multi2 : 8; RK_U32 cime_multi3 : 8; - } cime_multi; + } cime_multi_comb; /* 0x00001770 reg1500 */ struct { @@ -1206,7 +365,7 @@ typedef struct Vepu510Param_t { RK_U32 reserved1 : 9; RK_U32 fme_madp_th : 12; RK_U32 reserved2 : 4; - } rime_mvd_th; + } rime_mvd_th_comb; /* 0x00001774 reg1501 */ struct { @@ -1214,7 +373,7 @@ typedef struct Vepu510Param_t { RK_U32 reserved : 4; RK_U32 rime_madp_th1 : 12; RK_U32 reserved1 : 4; - } rime_madp_th; + } rime_madp_th_comb; /* 0x00001778 reg1502 */ struct { @@ -1222,7 +381,7 @@ typedef struct Vepu510Param_t { RK_U32 rime_multi1 : 10; RK_U32 rime_multi2 : 10; RK_U32 reserved : 2; - } rime_multi; + } rime_multi_comb; /* 0x0000177c reg1503 */ struct { @@ -1230,26 +389,242 @@ typedef struct Vepu510Param_t { RK_U32 cmv_th1 : 8; RK_U32 cmv_th2 : 8; RK_U32 reserved : 8; - } cmv_st_th; + } cmv_st_th_comb; /* 0x1780 - 0x17fc */ RK_U32 reserved1504_1535[32]; /* 0x00001800 reg1536 - 0x000018cc reg1587*/ - RK_U32 pprd_lamb_satd_hevc_0_51[52]; + RK_U32 pprd_lamb_satd_0_51[52]; /* 0x000018d0 reg1588 */ - RK_U32 iprd_lamb_satd_ofst_hevc; + struct { + RK_U32 lambda_satd_offset : 5; + RK_U32 reserved : 27; + } iprd_lamb_satd_ofst; /* 0x18d4 - 0x18fc */ RK_U32 reserved1589_1599[11]; - // /* 0x00001900 reg1600 - 0x000019cc reg1651*/ + /* 0x00001900 reg1600 - 0x000019cc reg1651*/ RK_U32 rdo_wgta_qp_grpa_0_51[52]; -} Vepu510Param; +} H264eVepu510Param; + +/* class: rdo/q_i */ +/* 0x00002000 reg2048 - 0x000020fc reg2111 */ +typedef struct H264eVepu510SqiCfg_t { + /* 0x00002000 reg2048 - 0x00002010 reg2052*/ + RK_U32 reserved_2048_2052[5]; + + /* 0x00002014 reg2053 */ + struct { + RK_U32 rdo_smear_lvl16_multi : 8; + RK_U32 rdo_smear_dlt_qp : 4; + RK_U32 reserved : 1; + RK_U32 stated_mode : 2; + RK_U32 rdo_smear_en : 1; + RK_U32 reserved1 : 16; + } smear_opt_cfg; + + /* 0x00002018 reg2054 */ + struct { + RK_U32 rdo_smear_madp_cur_thd0 : 12; + RK_U32 reserved : 4; + RK_U32 rdo_smear_madp_cur_thd1 : 12; + RK_U32 reserved1 : 4; + } rdo_smear_madp_thd0; + + /* 0x0000201c reg2055 */ + struct { + RK_U32 rdo_smear_madp_cur_thd2 : 12; + RK_U32 reserved : 4; + RK_U32 rdo_smear_madp_cur_thd3 : 12; + RK_U32 reserved1 : 4; + } rdo_smear_madp_thd1; + + /* 0x00002020 reg2056 */ + struct { + RK_U32 rdo_smear_madp_around_thd0 : 12; + RK_U32 reserved : 4; + RK_U32 rdo_smear_madp_around_thd1 : 12; + RK_U32 reserved1 : 4; + } rdo_smear_madp_thd2; + + /* 0x00002024 reg2057 */ + struct { + RK_U32 rdo_smear_madp_around_thd2 : 12; + RK_U32 reserved : 4; + RK_U32 rdo_smear_madp_around_thd3 : 12; + RK_U32 reserved1 : 4; + } rdo_smear_madp_thd3; + + /* 0x00002028 reg2058 */ + struct { + RK_U32 rdo_smear_madp_around_thd4 : 12; + RK_U32 reserved : 4; + RK_U32 rdo_smear_madp_around_thd5 : 12; + RK_U32 reserved1 : 4; + } rdo_smear_madp_thd4; + + /* 0x0000202c reg2059 */ + struct { + RK_U32 rdo_smear_madp_ref_thd0 : 12; + RK_U32 reserved : 4; + RK_U32 rdo_smear_madp_ref_thd1 : 12; + RK_U32 reserved1 : 4; + } rdo_smear_madp_thd5; + + /* 0x00002030 reg2060 */ + struct { + RK_U32 rdo_smear_cnt_cur_thd0 : 4; + RK_U32 reserved : 4; + RK_U32 rdo_smear_cnt_cur_thd1 : 4; + RK_U32 reserved1 : 4; + RK_U32 rdo_smear_cnt_cur_thd2 : 4; + RK_U32 reserved2 : 4; + RK_U32 rdo_smear_cnt_cur_thd3 : 4; + RK_U32 reserved3 : 4; + } rdo_smear_cnt_thd0; + + /* 0x00002034 reg2061 */ + struct { + RK_U32 rdo_smear_cnt_around_thd0 : 4; + RK_U32 reserved : 4; + RK_U32 rdo_smear_cnt_around_thd1 : 4; + RK_U32 reserved1 : 4; + RK_U32 rdo_smear_cnt_around_thd2 : 4; + RK_U32 reserved2 : 4; + RK_U32 rdo_smear_cnt_around_thd3 : 4; + RK_U32 reserved3 : 4; + } rdo_smear_cnt_thd1; + + /* 0x00002038 reg2062 */ + struct { + RK_U32 rdo_smear_cnt_around_thd4 : 4; + RK_U32 reserved : 4; + RK_U32 rdo_smear_cnt_around_thd5 : 4; + RK_U32 reserved1 : 4; + RK_U32 rdo_smear_cnt_around_thd6 : 4; + RK_U32 reserved2 : 4; + RK_U32 rdo_smear_cnt_around_thd7 : 4; + RK_U32 reserved3 : 4; + } rdo_smear_cnt_thd2; + + /* 0x0000203c reg2063 */ + struct { + RK_U32 rdo_smear_cnt_ref_thd0 : 4; + RK_U32 reserved : 4; + RK_U32 rdo_smear_cnt_ref_thd1 : 4; + RK_U32 reserved1 : 20; + } rdo_smear_cnt_thd3; + + /* 0x00002040 reg2064 */ + struct { + RK_U32 rdo_smear_resi_small_cur_th0 : 6; + RK_U32 reserved : 2; + RK_U32 rdo_smear_resi_big_cur_th0 : 6; + RK_U32 reserved1 : 2; + RK_U32 rdo_smear_resi_small_cur_th1 : 6; + RK_U32 reserved2 : 2; + RK_U32 rdo_smear_resi_big_cur_th1 : 6; + RK_U32 reserved3 : 2; + } rdo_smear_resi_thd0; + + /* 0x00002044 reg2065 */ + struct { + RK_U32 rdo_smear_resi_small_around_th0 : 6; + RK_U32 reserved : 2; + RK_U32 rdo_smear_resi_big_around_th0 : 6; + RK_U32 reserved1 : 2; + RK_U32 rdo_smear_resi_small_around_th1 : 6; + RK_U32 reserved2 : 2; + RK_U32 rdo_smear_resi_big_around_th1 : 6; + RK_U32 reserved3 : 2; + } rdo_smear_resi_thd1; + + /* 0x00002048 reg2066 */ + struct { + RK_U32 rdo_smear_resi_small_around_th2 : 6; + RK_U32 reserved : 2; + RK_U32 rdo_smear_resi_big_around_th2 : 6; + RK_U32 reserved1 : 2; + RK_U32 rdo_smear_resi_small_around_th3 : 6; + RK_U32 reserved2 : 2; + RK_U32 rdo_smear_resi_big_around_th3 : 6; + RK_U32 reserved3 : 2; + } rdo_smear_resi_thd2; + + /* 0x0000204c reg2067 */ + struct { + RK_U32 rdo_smear_resi_small_ref_th0 : 6; + RK_U32 reserved : 2; + RK_U32 rdo_smear_resi_big_ref_th0 : 6; + RK_U32 reserved1 : 18; + } rdo_smear_resi_thd3; + + /* 0x00002050 reg2068 */ + struct { + RK_U32 rdo_smear_resi_th0 : 8; + RK_U32 reserved : 8; + RK_U32 rdo_smear_resi_th1 : 8; + RK_U32 reserved1 : 8; + } rdo_smear_resi_thd4; + + /* 0x00002054 reg2069 */ + struct { + RK_U32 rdo_smear_madp_cnt_th0 : 4; + RK_U32 rdo_smear_madp_cnt_th1 : 4; + RK_U32 rdo_smear_madp_cnt_th2 : 4; + RK_U32 rdo_smear_madp_cnt_th3 : 4; + RK_U32 reserved : 16; + } rdo_smear_st_thd; + + /* 0x2058 - 0x206c */ + RK_U32 reserved2070_2075[6]; + + /* 0x00002070 reg2076 - 0x0000207c reg2079*/ + rdo_skip_par rdo_b16_skip; + + /* 0x00002080 reg2080 - 0x00002088 reg2082 */ + RK_U32 reserved2080_2082[3]; + + /* 0x0000208c reg2083 - 0x00002094 reg2085 */ + rdo_noskip_par rdo_b16_inter; + + /* 0x00002098 reg2086 - 0x000020a4 reg2088 */ + RK_U32 reserved2086_2088[3]; + + /* 0x000020a8 reg2089 - 0x000020ac reg2091 */ + rdo_noskip_par rdo_b16_intra; + + /* 0x000020b0 reg2092 */ + RK_U32 reserved2092; + + /* 0x000020b4 reg2093 */ + struct { + RK_U32 thd0 : 4; + RK_U32 reserved : 4; + RK_U32 thd1 : 4; + RK_U32 reserved1 : 4; + RK_U32 thd2 : 4; + RK_U32 reserved2 : 4; + RK_U32 thd3 : 4; + RK_U32 reserved3 : 4; + } rdo_b16_intra_atf_cnt_thd; + + /* 0x000020b8 reg2094 */ + struct { + RK_U32 big_th0 : 6; + RK_U32 reserved : 2; + RK_U32 big_th1 : 6; + RK_U32 reserved1 : 2; + RK_U32 small_th0 : 6; + RK_U32 reserved2 : 2; + RK_U32 small_th1 : 6; + RK_U32 reserved3 : 2; + } rdo_atf_resi_thd; +} H264eVepu510Sqi; -/* class: scaling list */ -/* 0x00002200 reg2176- 0x00002584 reg2401*/ typedef struct Vepu510SclCfg_t { RK_U32 q_scal_list_0_225[226]; } Vepu510SclCfg; @@ -1258,10 +633,10 @@ typedef struct Vepu510SclCfg_t { /* 0x0000f000 reg15360 - 0x0000f024 reg15369 */ typedef struct HalVepu510Reg_t { Vepu510ControlCfg reg_ctl; - Vepu510FrameCfg reg_frm; - Vepu510RcRoiCfg reg_rc_roi; - Vepu510Param reg_param; - Vepu510Sqi reg_sqi; + H264eVepu510Frame reg_frm; + Vepu510RcRoi reg_rc_roi; + H264eVepu510Param reg_param; + H264eVepu510Sqi reg_sqi; Vepu510SclCfg reg_scl; Vepu510Status reg_st; Vepu510Dbg reg_dbg; diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c index 2b6454b6..6c5ba654 100644 --- a/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c +++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c @@ -291,72 +291,12 @@ static MPP_RET vepu510_h265_setup_hal_bufs(H265eV510HalContext *ctx) return ret; } -static void vepu510_h265_rdo_cfg (Vepu510Sqi *reg) +static void vepu510_h265_rdo_cfg(H265eVepu510Sqi *reg) { rdo_skip_par *p_rdo_skip = NULL; rdo_noskip_par *p_rdo_noskip = NULL; pre_cst_par *p_pre_cst = NULL; - reg->rdo_segment_cfg.rdo_segment_multi = 28; - reg->rdo_segment_cfg.rdo_segment_en = 1; - reg->rdo_smear_cfg_comb.rdo_smear_en = 0; - reg->rdo_smear_cfg_comb.rdo_smear_lvl16_multi = 9; - reg->rdo_segment_cfg.rdo_smear_lvl8_multi = 8; - reg->rdo_segment_cfg.rdo_smear_lvl4_multi = 8 ; - reg->rdo_smear_cfg_comb.rdo_smear_dlt_qp = 0 ; - reg->rdo_smear_cfg_comb.rdo_smear_order_state = 0; - reg->rdo_smear_cfg_comb.stated_mode = 0; - reg->rdo_smear_cfg_comb.online_en = 0; - reg->rdo_smear_cfg_comb.smear_stride = 0; - reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd0 = 0 ; - reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd1 = 24; - reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd2 = 48; - reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd3 = 64; - reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd0 = 16; - reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd1 = 32; - reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd2 = 48; - reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd3 = 96; - reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd4 = 48; - reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd5 = 24; - reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd0 = 96; - reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd1 = 48; - reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd0 = 1 ; - reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd1 = 3 ; - reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd2 = 1 ; - reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd3 = 3 ; - reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd0 = 1 ; - reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd1 = 4 ; - reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd2 = 1 ; - reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd3 = 4 ; - reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd4 = 0 ; - reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd5 = 3 ; - reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd6 = 0 ; - reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd7 = 3 ; - reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd0 = 1 ; - reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd1 = 3 ; - reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th0 = 6; - reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th0 = 9; - reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th1 = 6; - reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th1 = 9; - reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th0 = 6; - reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th0 = 11; - reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th1 = 6; - reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th1 = 8; - reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th2 = 9; - reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th2 = 20; - reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th3 = 6; - reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th3 = 20; - reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_small_ref_th0 = 7; - reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_big_ref_th0 = 16; - reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th0 = 9; - reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th1 = 6; - reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th0 = 1; - reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th1 = 5; - reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th2 = 1; - reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th3 = 3; - reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th4 = 1; - reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th5 = 2; - p_rdo_skip = ®->rdo_b32_skip; p_rdo_skip->atf_thd0.madp_thd0 = 5 ; p_rdo_skip->atf_thd0.madp_thd1 = 10 ; @@ -415,20 +355,6 @@ static void vepu510_h265_rdo_cfg (Vepu510Sqi *reg) p_rdo_noskip->atf_wgt.wgt2 = 20; p_rdo_noskip->atf_wgt.wgt3 = 16; - reg->rdo_b32_intra_atf_cnt_thd.thd0 = 1 ; - reg->rdo_b32_intra_atf_cnt_thd.thd1 = 4 ; - reg->rdo_b32_intra_atf_cnt_thd.thd2 = 1 ; - reg->rdo_b32_intra_atf_cnt_thd.thd3 = 4 ; - - reg->rdo_b16_intra_atf_cnt_thd_comb.thd0 = 1 ; - reg->rdo_b16_intra_atf_cnt_thd_comb.thd1 = 4 ; - reg->rdo_b16_intra_atf_cnt_thd_comb.thd2 = 1 ; - reg->rdo_b16_intra_atf_cnt_thd_comb.thd3 = 4 ; - reg->rdo_atf_resi_thd_comb.big_th0 = 16; - reg->rdo_atf_resi_thd_comb.big_th1 = 16; - reg->rdo_atf_resi_thd_comb.small_th0 = 8; - reg->rdo_atf_resi_thd_comb.small_th1 = 8; - p_pre_cst = ®->preintra32_cst; p_pre_cst->cst_madi_thd0.madi_thd0 = 5 ; p_pre_cst->cst_madi_thd0.madi_thd1 = 3 ; @@ -446,7 +372,6 @@ static void vepu510_h265_rdo_cfg (Vepu510Sqi *reg) p_pre_cst->cst_wgt1.wgt7 = 18 ; p_pre_cst->cst_wgt2.wgt8 = 17 ; p_pre_cst->cst_wgt2.wgt9 = 17 ; - p_pre_cst->cst_wgt2.mode_th = 5 ; p_pre_cst = ®->preintra16_cst; p_pre_cst->cst_madi_thd0.madi_thd0 = 5 ; @@ -465,22 +390,6 @@ static void vepu510_h265_rdo_cfg (Vepu510Sqi *reg) p_pre_cst->cst_wgt1.wgt7 = 18; p_pre_cst->cst_wgt2.wgt8 = 17; p_pre_cst->cst_wgt2.wgt9 = 17; - p_pre_cst->cst_wgt2.mode_th = 5 ; - - reg->preintra_sqi_cfg.pre_intra_qp_thd = 28; - reg->preintra_sqi_cfg.pre_intra4_lambda_mv_bit = 3; - reg->preintra_sqi_cfg.pre_intra8_lambda_mv_bit = 4; - reg->preintra_sqi_cfg.pre_intra16_lambda_mv_bit = 4; - reg->preintra_sqi_cfg.pre_intra32_lambda_mv_bit = 5; - reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd0 = 3; - reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd1 = 25; - reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd2 = 25; - reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_cnt_thd3 = 0; - reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_thd4 = 20; - reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_cost_multi = 24; - reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd0 = 4; - reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd1 = 6; - reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_cost_multi = 24; /* 0x00002100 reg2112 */ reg->cudecis_thd0.base_thre_rough_mad32_intra = 9; @@ -599,9 +508,9 @@ static void vepu510_h265_global_cfg_set(H265eV510HalContext *ctx, H265eV510RegSe { MppEncHwCfg *hw = &ctx->cfg->hw; RK_U32 i; - H265eVepu510RcRoi *rc_regs = ®s->reg_rc_roi; + Vepu510RcRoi *rc_regs = ®s->reg_rc_roi; H265eVepu510Param *reg_param = ®s->reg_param; - Vepu510Sqi *reg_sqi = ®s->reg_sqi; + H265eVepu510Sqi *reg_sqi = ®s->reg_sqi; vepu510_h265_rdo_cfg(reg_sqi); memcpy(®_param->pprd_lamb_satd_0_51[0], lamd_satd_qp_510, sizeof(lamd_satd_qp)); @@ -626,58 +535,58 @@ static void vepu510_h265_global_cfg_set(H265eV510HalContext *ctx, H265eV510RegSe reg_param->iprd_lamb_satd_ofst.lambda_satd_offset = 11; memcpy(®_param->rdo_wgta_qp_grpa_0_51[0], lamd_modb_qp, sizeof(lamd_modb_qp)); } - reg_param->reg1484_qnt_bias_comb.qnt_bias_i = 171; - reg_param->reg1484_qnt_bias_comb.qnt_bias_p = 85; + reg_param->qnt_bias_comb.qnt_f_bias_i = 171; + reg_param->qnt_bias_comb.qnt_f_bias_p = 85; if (hw->qbias_en) { - reg_param->reg1484_qnt_bias_comb.qnt_bias_i = hw->qbias_i; - reg_param->reg1484_qnt_bias_comb.qnt_bias_p = hw->qbias_p; + reg_param->qnt_bias_comb.qnt_f_bias_i = hw->qbias_i; + reg_param->qnt_bias_comb.qnt_f_bias_p = hw->qbias_p; } /* CIME */ { /* 0x1760 */ - regs->reg_param.me_sqi_cfg.cime_pmv_num = 1; - regs->reg_param.me_sqi_cfg.cime_fuse = 1; - regs->reg_param.me_sqi_cfg.itp_mode = 0; - regs->reg_param.me_sqi_cfg.move_lambda = 2; - regs->reg_param.me_sqi_cfg.rime_lvl_mrg = 0; - regs->reg_param.me_sqi_cfg.rime_prelvl_en = 3; - regs->reg_param.me_sqi_cfg.rime_prersu_en = 3; + regs->reg_param.me_sqi_comb.cime_pmv_num = 1; + regs->reg_param.me_sqi_comb.cime_fuse = 1; + regs->reg_param.me_sqi_comb.itp_mode = 0; + regs->reg_param.me_sqi_comb.move_lambda = 2; + regs->reg_param.me_sqi_comb.rime_lvl_mrg = 0; + regs->reg_param.me_sqi_comb.rime_prelvl_en = 3; + regs->reg_param.me_sqi_comb.rime_prersu_en = 3; /* 0x1764 */ - regs->reg_param.cime_mvd_th.cime_mvd_th0 = 8; - regs->reg_param.cime_mvd_th.cime_mvd_th1 = 20; - regs->reg_param.cime_mvd_th.cime_mvd_th2 = 32; + regs->reg_param.cime_mvd_th_comb.cime_mvd_th0 = 8; + regs->reg_param.cime_mvd_th_comb.cime_mvd_th1 = 20; + regs->reg_param.cime_mvd_th_comb.cime_mvd_th2 = 32; /* 0x1768 */ - regs->reg_param.cime_madp_th.cime_madp_th = 16; + regs->reg_param.cime_madp_th_comb.cime_madp_th = 16; /* 0x176c */ - regs->reg_param.cime_multi.cime_multi0 = 8; - regs->reg_param.cime_multi.cime_multi1 = 12; - regs->reg_param.cime_multi.cime_multi2 = 16; - regs->reg_param.cime_multi.cime_multi3 = 20; + regs->reg_param.cime_multi_comb.cime_multi0 = 8; + regs->reg_param.cime_multi_comb.cime_multi1 = 12; + regs->reg_param.cime_multi_comb.cime_multi2 = 16; + regs->reg_param.cime_multi_comb.cime_multi3 = 20; } /* RIME && FME */ { /* 0x1770 */ - regs->reg_param.rime_mvd_th.rime_mvd_th0 = 1; - regs->reg_param.rime_mvd_th.rime_mvd_th1 = 2; - regs->reg_param.rime_mvd_th.fme_madp_th = 0; + regs->reg_param.rime_mvd_th_comb.rime_mvd_th0 = 1; + regs->reg_param.rime_mvd_th_comb.rime_mvd_th1 = 2; + regs->reg_param.rime_mvd_th_comb.fme_madp_th = 0; /* 0x1774 */ - regs->reg_param.rime_madp_th.rime_madp_th0 = 8; - regs->reg_param.rime_madp_th.rime_madp_th1 = 16; + regs->reg_param.rime_madp_th_comb.rime_madp_th0 = 8; + regs->reg_param.rime_madp_th_comb.rime_madp_th1 = 16; /* 0x1778 */ - regs->reg_param.rime_multi.rime_multi0 = 4; - regs->reg_param.rime_multi.rime_multi1 = 8; - regs->reg_param.rime_multi.rime_multi2 = 12; + regs->reg_param.rime_multi_comb.rime_multi0 = 4; + regs->reg_param.rime_multi_comb.rime_multi1 = 8; + regs->reg_param.rime_multi_comb.rime_multi2 = 12; /* 0x177C */ - regs->reg_param.cmv_st_th.cmv_th0 = 64; - regs->reg_param.cmv_st_th.cmv_th1 = 96; - regs->reg_param.cmv_st_th.cmv_th2 = 128; + regs->reg_param.cmv_st_th_comb.cmv_th0 = 64; + regs->reg_param.cmv_st_th_comb.cmv_th1 = 96; + regs->reg_param.cmv_st_th_comb.cmv_th2 = 128; } } @@ -922,7 +831,7 @@ static MPP_RET vepu510_h265_set_rc_regs(H265eV510HalContext *ctx, H265eV510RegSe H265eSyntax_new *syn = ctx->syn; EncRcTaskInfo *rc_cfg = &task->rc_task->info; H265eVepu510Frame *reg_frm = ®s->reg_frm; - H265eVepu510RcRoi *reg_rc = ®s->reg_rc_roi; + Vepu510RcRoi *reg_rc = ®s->reg_rc_roi; MppEncCfgSet *cfg = ctx->cfg; MppEncRcCfg *rc = &cfg->rc; MppEncHwCfg *hw = &cfg->hw; @@ -936,11 +845,11 @@ static MPP_RET vepu510_h265_set_rc_regs(H265eV510HalContext *ctx, H265eV510RegSe RK_S32 negative_bits_thd, positive_bits_thd; if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) { - reg_frm->reg0192_enc_pic.pic_qp = rc_cfg->quality_target; - reg_frm->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target; + reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target; + reg_frm->synt_sli1.sli_qp = rc_cfg->quality_target; - reg_frm->reg213_rc_qp.rc_max_qp = rc_cfg->quality_target; - reg_frm->reg213_rc_qp.rc_min_qp = rc_cfg->quality_target; + reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_target; + reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_target; } else { if (ctu_target_bits_mul_16 >= 0x100000) { ctu_target_bits_mul_16 = 0x50000; @@ -949,16 +858,16 @@ static MPP_RET vepu510_h265_set_rc_regs(H265eV510HalContext *ctx, H265eV510RegSe negative_bits_thd = 0 - 5 * ctu_target_bits / 16; positive_bits_thd = 5 * ctu_target_bits / 16; - reg_frm->reg0192_enc_pic.pic_qp = rc_cfg->quality_target; - reg_frm->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target; - reg_frm->reg212_rc_cfg.rc_en = 1; - reg_frm->reg212_rc_cfg.aq_en = 1; - reg_frm->reg212_rc_cfg.rc_ctu_num = mb_wd32; - reg_frm->reg213_rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ? - hw->qp_delta_row_i : hw->qp_delta_row; - reg_frm->reg213_rc_qp.rc_max_qp = rc_cfg->quality_max; - reg_frm->reg213_rc_qp.rc_min_qp = rc_cfg->quality_min; - reg_frm->reg214_rc_tgt.ctu_ebit = ctu_target_bits_mul_16; + reg_frm->common.enc_pic.pic_qp = rc_cfg->quality_target; + reg_frm->synt_sli1.sli_qp = rc_cfg->quality_target; + reg_frm->common.rc_cfg.rc_en = 1; + reg_frm->common.rc_cfg.aq_en = 1; + reg_frm->common.rc_cfg.rc_ctu_num = mb_wd32; + reg_frm->common.rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ? + hw->qp_delta_row_i : hw->qp_delta_row; + reg_frm->common.rc_qp.rc_max_qp = rc_cfg->quality_max; + reg_frm->common.rc_qp.rc_min_qp = rc_cfg->quality_min; + reg_frm->common.rc_tgt.ctu_ebit = ctu_target_bits_mul_16; reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd; reg_rc->rc_dthd_0_8[1] = negative_bits_thd; @@ -1003,26 +912,25 @@ static MPP_RET vepu510_h265_set_rc_regs(H265eV510HalContext *ctx, H265eV510RegSe static MPP_RET vepu510_h265_set_pp_regs(H265eV510RegSet *regs, VepuFmtCfg *fmt, MppEncPrepCfg *prep_cfg) { - H265eVepu510ControlCfg *reg_ctl = ®s->reg_ctl; + Vepu510ControlCfg *reg_ctl = ®s->reg_ctl; H265eVepu510Frame *reg_frm = ®s->reg_frm; RK_S32 stridey = 0; RK_S32 stridec = 0; - reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian; - reg_frm->reg0198_src_fmt.src_cfmt = fmt->format; - reg_frm->reg0198_src_fmt.alpha_swap = fmt->alpha_swap; - reg_frm->reg0198_src_fmt.rbuv_swap = fmt->rbuv_swap; + reg_ctl->dtrns_map.src_bus_edin = fmt->src_endian; + reg_frm->common.src_fmt.src_cfmt = fmt->format; + reg_frm->common.src_fmt.alpha_swap = fmt->alpha_swap; + reg_frm->common.src_fmt.rbuv_swap = fmt->rbuv_swap; - // reg_frm->reg0198_src_fmt.src_range = fmt->src_range; - reg_frm->reg0198_src_fmt.out_fmt = ((prep_cfg->format & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400) ? 0 : 1; + reg_frm->common.src_fmt.out_fmt = ((prep_cfg->format & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400) ? 0 : 1; - reg_frm->reg0203_src_proc.src_mirr = prep_cfg->mirroring > 0; - reg_frm->reg0203_src_proc.src_rot = prep_cfg->rotation; - reg_frm->reg0203_src_proc.tile4x4_en = 0; + reg_frm->common.src_proc.src_mirr = prep_cfg->mirroring > 0; + reg_frm->common.src_proc.src_rot = prep_cfg->rotation; + reg_frm->common.src_proc.tile4x4_en = 0; if (prep_cfg->hor_stride) { if (MPP_FRAME_FMT_IS_TILE(prep_cfg->format)) { - reg_frm->reg0203_src_proc.tile4x4_en = 1; + reg_frm->common.src_proc.tile4x4_en = 1; switch (prep_cfg->format & MPP_FRAME_FMT_MASK) { case MPP_FMT_YUV400: @@ -1049,175 +957,175 @@ static MPP_RET vepu510_h265_set_pp_regs(H265eV510RegSet *regs, VepuFmtCfg *fmt, stridey = prep_cfg->hor_stride; } } else { - if (reg_frm->reg0198_src_fmt.src_cfmt == VEPU541_FMT_BGRA8888 ) + if (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_BGRA8888 ) stridey = prep_cfg->width * 4; - else if (reg_frm->reg0198_src_fmt.src_cfmt == VEPU541_FMT_BGR888 ) + else if (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_BGR888 ) stridey = prep_cfg->width * 3; - else if (reg_frm->reg0198_src_fmt.src_cfmt == VEPU541_FMT_BGR565 || - reg_frm->reg0198_src_fmt.src_cfmt == VEPU541_FMT_YUYV422 || - reg_frm->reg0198_src_fmt.src_cfmt == VEPU541_FMT_UYVY422) + else if (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_BGR565 || + reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_YUYV422 || + reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_UYVY422) stridey = prep_cfg->width * 2; } - stridec = (reg_frm->reg0198_src_fmt.src_cfmt == VEPU541_FMT_YUV420SP || - reg_frm->reg0198_src_fmt.src_cfmt == VEPU541_FMT_YUV422SP || - reg_frm->reg0198_src_fmt.src_cfmt == VEPU580_FMT_YUV444P) ? + stridec = (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_YUV420SP || + reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_YUV422SP || + reg_frm->common.src_fmt.src_cfmt == VEPU580_FMT_YUV444P) ? stridey : stridey / 2; - if (reg_frm->reg0198_src_fmt.src_cfmt == VEPU580_FMT_YUV444SP) + if (reg_frm->common.src_fmt.src_cfmt == VEPU580_FMT_YUV444SP) stridec = stridey * 2; - if (reg_frm->reg0198_src_fmt.src_cfmt < VEPU541_FMT_NONE) { + if (reg_frm->common.src_fmt.src_cfmt < VEPU541_FMT_NONE) { const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color); hal_h265e_dbg_simple("input color range %d colorspace %d", prep_cfg->range, prep_cfg->color); - reg_frm->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; - reg_frm->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; - reg_frm->reg0199_src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; + reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; + reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; + reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; - reg_frm->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; - reg_frm->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; - reg_frm->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; + reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; + reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; + reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; - reg_frm->reg0201_src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; - reg_frm->reg0201_src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; - reg_frm->reg0201_src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; + reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; + reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; + reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; - reg_frm->reg0202_src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; - reg_frm->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; - reg_frm->reg0202_src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; + reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; + reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; + reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset; hal_h265e_dbg_simple("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color); } - reg_frm->reg0205_src_strd0.src_strd0 = stridey; - reg_frm->reg0206_src_strd1.src_strd1 = stridec; + reg_frm->common.src_strd0.src_strd0 = stridey; + reg_frm->common.src_strd1.src_strd1 = stridec; return MPP_OK; } static void vepu510_h265_set_slice_regs(H265eSyntax_new *syn, H265eVepu510Frame *regs) { - regs->reg0237_synt_sps.smpl_adpt_ofst_e = syn->pp.sample_adaptive_offset_enabled_flag; - regs->reg0237_synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets; - regs->reg0237_synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps; - regs->reg0237_synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag; - regs->reg0237_synt_sps.tmpl_mvp_e = syn->pp.sps_temporal_mvp_enabled_flag; - regs->reg0237_synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4; - regs->reg0237_synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag; + regs->synt_sps.smpl_adpt_ofst_e = syn->pp.sample_adaptive_offset_enabled_flag; + regs->synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets; + regs->synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps; + regs->synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag; + regs->synt_sps.tmpl_mvp_e = syn->pp.sps_temporal_mvp_enabled_flag; + regs->synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4; + regs->synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag; - regs->reg0238_synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag; - regs->reg0238_synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag; - regs->reg0238_synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits; - regs->reg0238_synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag; - regs->reg0238_synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag; - regs->reg0238_synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26; - regs->reg0238_synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag; - regs->reg0238_synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag; - regs->reg0238_synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag; - regs->reg0238_synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag; - regs->reg0238_synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag; - regs->reg0238_synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag; - regs->reg0238_synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth; - regs->reg0238_synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag; + regs->synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag; + regs->synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag; + regs->synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits; + regs->synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag; + regs->synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag; + regs->synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26; + regs->synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag; + regs->synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag; + regs->synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag; + regs->synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag; + regs->synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag; + regs->synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag; + regs->synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth; + regs->synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag; - regs->reg0239_synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg; - regs->reg0239_synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg; - regs->reg0239_synt_sli0.mrg_up_flg = syn->sp.merge_up_flag; - regs->reg0239_synt_sli0.mrg_lft_flg = syn->sp.merge_left_flag; - regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; + regs->synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg; + regs->synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg; + regs->synt_sli0.mrg_up_flg = syn->sp.merge_up_flag; + regs->synt_sli0.mrg_lft_flg = syn->sp.merge_left_flag; + regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; - regs->reg0239_synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act; - regs->reg0239_synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act; + regs->synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act; + regs->synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act; - regs->reg0239_synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd; + regs->synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd; - regs->reg0239_synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg; - regs->reg0239_synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg; - regs->reg0239_synt_sli0.sli_tmprl_mvp_e = syn->sp.sli_tmprl_mvp_en; - regs->reg0192_enc_pic.num_pic_tot_cur = syn->sp.tot_poc_num; + regs->synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg; + regs->synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg; + regs->synt_sli0.sli_tmprl_mvp_e = syn->sp.sli_tmprl_mvp_en; + regs->common.enc_pic.num_pic_tot_cur_hevc = syn->sp.tot_poc_num; - regs->reg0239_synt_sli0.pic_out_flg = syn->sp.pic_out_flg; - regs->reg0239_synt_sli0.sli_type = syn->sp.slice_type; - regs->reg0239_synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg; - regs->reg0239_synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg; - regs->reg0239_synt_sli0.sli_pps_id = syn->sp.sli_pps_id; - regs->reg0239_synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic; + regs->synt_sli0.pic_out_flg = syn->sp.pic_out_flg; + regs->synt_sli0.sli_type = syn->sp.slice_type; + regs->synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg; + regs->synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg; + regs->synt_sli0.sli_pps_id = syn->sp.sli_pps_id; + regs->synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic; - regs->reg0240_synt_sli1.sp_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;; - regs->reg0240_synt_sli1.sp_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2; - regs->reg0240_synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli; - regs->reg0240_synt_sli1.sp_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis; - regs->reg0240_synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg; - regs->reg0240_synt_sli1.sli_cb_qp_ofst = syn->sp.sli_cb_qp_ofst; - regs->reg0240_synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd; + regs->synt_sli1.sp_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;; + regs->synt_sli1.sp_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2; + regs->synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli; + regs->synt_sli1.sp_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis; + regs->synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg; + regs->synt_sli1.sli_cb_qp_ofst = syn->sp.sli_cb_qp_ofst; + regs->synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd; - regs->reg0240_synt_sli1.col_ref_idx = syn->sp.col_ref_idx; - regs->reg0240_synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg; - regs->reg0241_synt_sli2.sli_poc_lsb = syn->sp.sli_poc_lsb; - regs->reg0241_synt_sli2.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len; + regs->synt_sli1.col_ref_idx = syn->sp.col_ref_idx; + regs->synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg; + regs->synt_sli2.sli_poc_lsb = syn->sp.sli_poc_lsb; + regs->synt_sli2.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len; } static void vepu510_h265_set_ref_regs(H265eSyntax_new *syn, H265eVepu510Frame *regs) { - regs->reg0242_synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg; - regs->reg0242_synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0; - regs->reg0242_synt_refm0.num_lt_pic = syn->sp.num_lt_pic; + regs->synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg; + regs->synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0; + regs->synt_refm0.num_lt_pic = syn->sp.num_lt_pic; - regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; - regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; - regs->reg0243_synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0; - regs->reg0243_synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1; - regs->reg0243_synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2; - regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; - regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; - regs->reg0243_synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1; - regs->reg0243_synt_refm1.num_negative_pics = syn->sp.num_neg_pic; - regs->reg0243_synt_refm1.num_pos_pic = syn->sp.num_pos_pic; + regs->synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; + regs->synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; + regs->synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0; + regs->synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1; + regs->synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2; + regs->synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0; + regs->synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0; + regs->synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1; + regs->synt_refm1.num_negative_pics = syn->sp.num_neg_pic; + regs->synt_refm1.num_pos_pic = syn->sp.num_pos_pic; - regs->reg0243_synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg; - regs->reg0244_synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10; - regs->reg0244_synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11; - regs->reg0245_synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12; - regs->reg0245_synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13; + regs->synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg; + regs->synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10; + regs->synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11; + regs->synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12; + regs->synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13; - regs->reg0246_synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1; - regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1; - regs->reg0246_synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2; - regs->reg0243_synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2; - regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2; - regs->reg0240_synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0; - regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; + regs->synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1; + regs->synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1; + regs->synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2; + regs->synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2; + regs->synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2; + regs->synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0; + regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0; } static void vepu510_h265_set_me_regs(H265eV510HalContext *ctx, H265eSyntax_new *syn, H265eVepu510Frame *regs) { - regs->reg0220_me_rnge.cime_srch_dwnh = 15; - regs->reg0220_me_rnge.cime_srch_uph = 14; - regs->reg0220_me_rnge.cime_srch_rgtw = 12; - regs->reg0220_me_rnge.cime_srch_lftw = 12; - regs->reg0221_me_cfg.rme_srch_h = 3; - regs->reg0221_me_cfg.rme_srch_v = 3; + regs->common.me_rnge.cime_srch_dwnh = 15; + regs->common.me_rnge.cime_srch_uph = 14; + regs->common.me_rnge.cime_srch_rgtw = 12; + regs->common.me_rnge.cime_srch_lftw = 12; + regs->common.me_cfg.rme_srch_h = 3; + regs->common.me_cfg.rme_srch_v = 3; - regs->reg0221_me_cfg.srgn_max_num = 72; - regs->reg0221_me_cfg.cime_dist_thre = 1024; - regs->reg0221_me_cfg.rme_dis = 0; - regs->reg0221_me_cfg.fme_dis = 0; - regs->reg0220_me_rnge.dlt_frm_num = 0x1; + regs->common.me_cfg.srgn_max_num = 72; + regs->common.me_cfg.cime_dist_thre = 1024; + regs->common.me_cfg.rme_dis = 0; + regs->common.me_cfg.fme_dis = 0; + regs->common.me_rnge.dlt_frm_num = 0x1; if (syn->pp.sps_temporal_mvp_enabled_flag && (ctx->frame_type != INTRA_FRAME)) { if (ctx->last_frame_type == INTRA_FRAME) { - regs->reg0222_me_cach.colmv_load = 0; + regs->common.me_cach.colmv_load_hevc = 0; } else { - regs->reg0222_me_cach.colmv_load = 1; + regs->common.me_cach.colmv_load_hevc = 1; } - regs->reg0222_me_cach.colmv_stor = 1; + regs->common.me_cach.colmv_stor_hevc = 1; } - regs->reg0222_me_cach.cime_zero_thre = 1024; - regs->reg0222_me_cach.fme_prefsu_en = 0; + regs->common.me_cach.cime_zero_thre = 1024; + regs->common.me_cach.fme_prefsu_en = 0; } void vepu510_h265_set_hw_address(H265eV510HalContext *ctx, H265eVepu510Frame *regs, HalEncTask *task) @@ -1230,51 +1138,51 @@ void vepu510_h265_set_hw_address(H265eV510HalContext *ctx, H265eVepu510Frame *re hal_h265e_enter(); - regs->reg0160_adr_src0 = mpp_buffer_get_fd(enc_task->input); - regs->reg0161_adr_src1 = regs->reg0160_adr_src0; - regs->reg0162_adr_src2 = regs->reg0160_adr_src0; + regs->common.adr_src0 = mpp_buffer_get_fd(enc_task->input); + regs->common.adr_src1 = regs->common.adr_src0; + regs->common.adr_src2 = regs->common.adr_src0; recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_curr_idx); ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_refr_idx); if (!syn->sp.non_reference_flag) { - regs->reg0163_rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]); - regs->reg0164_rfpw_b_addr = regs->reg0163_rfpw_h_addr; + regs->common.rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]); + regs->common.rfpw_b_addr = regs->common.rfpw_h_addr; mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len); } - regs->reg0165_rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]); - regs->reg0166_rfpr_b_addr = regs->reg0165_rfpr_h_addr; - regs->reg0167_cmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]); - regs->reg0168_cmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]); - regs->reg0169_dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]); - regs->reg0170_dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]); + regs->common.rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]); + regs->common.rfpr_b_addr = regs->common.rfpr_h_addr; + regs->common.colmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]); + regs->common.colmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]); + regs->common.dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]); + regs->common.dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]); mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len); if (md_info_buf) { - regs->reg0192_enc_pic.mei_stor = 1; - regs->reg0171_meiw_addr = mpp_buffer_get_fd(md_info_buf); + regs->common.enc_pic.mei_stor = 1; + regs->common.meiw_addr = mpp_buffer_get_fd(md_info_buf); } else { - regs->reg0192_enc_pic.mei_stor = 0; - regs->reg0171_meiw_addr = 0; + regs->common.enc_pic.mei_stor = 0; + regs->common.meiw_addr = 0; } - regs->reg0172_bsbt_addr = mpp_buffer_get_fd(enc_task->output); + regs->common.bsbt_addr = mpp_buffer_get_fd(enc_task->output); /* TODO: stream size relative with syntax */ - regs->reg0173_bsbb_addr = regs->reg0172_bsbt_addr; - regs->reg0175_bsbr_addr = regs->reg0172_bsbt_addr; - regs->reg0174_adr_bsbs = regs->reg0172_bsbt_addr; + regs->common.bsbb_addr = regs->common.bsbt_addr; + regs->common.bsbr_addr = regs->common.bsbt_addr; + regs->common.adr_bsbs = regs->common.bsbt_addr; - regs->reg0180_adr_rfpt_h = 0xffffffff; - regs->reg0181_adr_rfpb_h = 0; - regs->reg0182_adr_rfpt_b = 0xffffffff; - regs->reg0183_adr_rfpb_b = 0; + regs->common.rfpt_h_addr = 0xffffffff; + regs->common.rfpb_h_addr = 0; + regs->common.rfpt_b_addr = 0xffffffff; + regs->common.adr_rfpb_b = 0; mpp_dev_multi_offset_update(ctx->reg_cfg, 174, mpp_packet_get_length(task->packet)); mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output)); - regs->reg0204_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); - regs->reg0204_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); + regs->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame); + regs->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame); } static MPP_RET vepu510_h265e_save_pass1_patch(H265eV510RegSet *regs, H265eV510HalContext *ctx, @@ -1294,26 +1202,26 @@ static MPP_RET vepu510_h265e_save_pass1_patch(H265eV510RegSet *regs, H265eV510Ha } } - reg_frm->reg0192_enc_pic.cur_frm_ref = 1; - reg_frm->reg0163_rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); - reg_frm->reg0164_rfpw_b_addr = reg_frm->reg0163_rfpw_h_addr; - reg_frm->reg0192_enc_pic.rec_fbc_dis = 1; + reg_frm->common.enc_pic.cur_frm_ref = 1; + reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1); + reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr; + reg_frm->common.enc_pic.rec_fbc_dis = 1; if (tiles_enabled_flag) - reg_frm->reg0238_synt_pps.lpf_fltr_acrs_til = 0; + reg_frm->synt_pps.lpf_fltr_acrs_til = 0; mpp_dev_multi_offset_update(ctx->reg_cfg, 164, 0); /* NOTE: disable split to avoid lowdelay slice output */ - regs->reg_frm.reg0216_sli_splt.sli_splt = 0; - regs->reg_frm.reg0192_enc_pic.slen_fifo = 0; + reg_frm->common.sli_splt.sli_splt = 0; + reg_frm->common.enc_pic.slen_fifo = 0; return MPP_OK; } static MPP_RET vepu510_h265e_use_pass1_patch(H265eV510RegSet *regs, H265eV510HalContext *ctx) { - H265eVepu510ControlCfg *reg_ctl = ®s->reg_ctl; + Vepu510ControlCfg *reg_ctl = ®s->reg_ctl; H265eVepu510Frame *reg_frm = ®s->reg_frm; RK_U32 hor_stride = MPP_ALIGN(ctx->cfg->prep.width, 16); VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt; @@ -1321,22 +1229,22 @@ static MPP_RET vepu510_h265e_use_pass1_patch(H265eV510RegSet *regs, H265eV510Hal hal_h265e_dbg_func("enter\n"); - reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian; - reg_frm->reg0198_src_fmt.src_cfmt = VEPU541_FMT_YUV420SP; - reg_frm->reg0198_src_fmt.alpha_swap = 0; - reg_frm->reg0198_src_fmt.rbuv_swap = 0; - reg_frm->reg0198_src_fmt.out_fmt = 1; - regs->reg_frm.reg0198_src_fmt.src_rcne = 1; + reg_ctl->dtrns_map.src_bus_edin = fmt->src_endian; + reg_frm->common.src_fmt.src_cfmt = VEPU541_FMT_YUV420SP; + reg_frm->common.src_fmt.alpha_swap = 0; + reg_frm->common.src_fmt.rbuv_swap = 0; + reg_frm->common.src_fmt.out_fmt = 1; + reg_frm->common.src_fmt.src_rcne = 1; - reg_frm->reg0205_src_strd0.src_strd0 = hor_stride; - reg_frm->reg0206_src_strd1.src_strd1 = 3 * hor_stride; + reg_frm->common.src_strd0.src_strd0 = hor_stride; + reg_frm->common.src_strd1.src_strd1 = 3 * hor_stride; - reg_frm->reg0203_src_proc.src_mirr = 0; - reg_frm->reg0203_src_proc.src_rot = 0; + reg_frm->common.src_proc.src_mirr = 0; + reg_frm->common.src_proc.src_rot = 0; - reg_frm->reg0160_adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1); - reg_frm->reg0161_adr_src1 = reg_frm->reg0160_adr_src0; - reg_frm->reg0162_adr_src2 = 0; + reg_frm->common.adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1); + reg_frm->common.adr_src1 = reg_frm->common.adr_src0; + reg_frm->common.adr_src2 = 0; /* input cb addr */ ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, 2 * hor_stride); @@ -1349,6 +1257,7 @@ static MPP_RET vepu510_h265e_use_pass1_patch(H265eV510RegSet *regs, H265eV510Hal static void setup_vepu510_ext_line_buf(H265eV510HalContext *ctx, H265eV510RegSet *regs) { MppDevRcbInfoCfg rcb_cfg; + H265eVepu510Frame *reg_frm = ®s->reg_frm; RK_S32 offset = 0; RK_S32 fd; @@ -1356,12 +1265,12 @@ static void setup_vepu510_ext_line_buf(H265eV510HalContext *ctx, H265eV510RegSet fd = mpp_buffer_get_fd(ctx->ext_line_buf); offset = ctx->ext_line_buf_size; - regs->reg_frm.reg0179_adr_ebufb = fd; - regs->reg_frm.reg0178_adr_ebuft = fd; + reg_frm->common.ebufb_addr = fd; + reg_frm->common.ebuft_addr = fd; mpp_dev_multi_offset_update(ctx->reg_cfg, 178, ctx->ext_line_buf_size); } else { - regs->reg_frm.reg0179_adr_ebufb = 0; - regs->reg_frm.reg0178_adr_ebuft = 0; + reg_frm->common.ebufb_addr = 0; + reg_frm->common.ebuft_addr = 0; } /* rcb info for sram */ @@ -1394,12 +1303,12 @@ static MPP_RET setup_vepu510_dual_core(H265eV510HalContext *ctx) dchs_rxe = 0; } - reg_frm->reg0193_dual_core.dchs_txid = ctx->curr_idx; - reg_frm->reg0193_dual_core.dchs_rxid = ctx->prev_idx; - reg_frm->reg0193_dual_core.dchs_txe = 1; - reg_frm->reg0193_dual_core.dchs_rxe = dchs_rxe; - reg_frm->reg0193_dual_core.dchs_ofst = dchs_ofst; - reg_frm->reg0193_dual_core.dchs_dly = dchs_dly; + reg_frm->common.dual_core.dchs_txid = ctx->curr_idx; + reg_frm->common.dual_core.dchs_rxid = ctx->prev_idx; + reg_frm->common.dual_core.dchs_txe = 1; + reg_frm->common.dual_core.dchs_rxe = dchs_rxe; + reg_frm->common.dual_core.dchs_ofst = dchs_ofst; + reg_frm->common.dual_core.dchs_dly = dchs_dly; ctx->prev_idx = ctx->curr_idx++; if (ctx->curr_idx > 3) @@ -1414,37 +1323,37 @@ static void setup_vepu510_split(H265eVepu510Frame *regs, MppEncSliceSplit *cfg) switch (cfg->split_mode) { case MPP_ENC_SPLIT_NONE : { - regs->reg0216_sli_splt.sli_splt = 0; - regs->reg0216_sli_splt.sli_splt_mode = 0; - regs->reg0216_sli_splt.sli_splt_cpst = 0; - regs->reg0216_sli_splt.sli_max_num_m1 = 0; - regs->reg0216_sli_splt.sli_flsh = 0; - regs->reg0218_sli_cnum.sli_splt_cnum_m1 = 0; + regs->common.sli_splt.sli_splt = 0; + regs->common.sli_splt.sli_splt_mode = 0; + regs->common.sli_splt.sli_splt_cpst = 0; + regs->common.sli_splt.sli_max_num_m1 = 0; + regs->common.sli_splt.sli_flsh = 0; + regs->common.sli_cnum.sli_splt_cnum_m1 = 0; - regs->reg0217_sli_byte.sli_splt_byte = 0; - regs->reg0192_enc_pic.slen_fifo = 0; + regs->common.sli_byte.sli_splt_byte = 0; + regs->common.enc_pic.slen_fifo = 0; } break; case MPP_ENC_SPLIT_BY_BYTE : { - regs->reg0216_sli_splt.sli_splt = 1; - regs->reg0216_sli_splt.sli_splt_mode = 0; - regs->reg0216_sli_splt.sli_splt_cpst = 0; - regs->reg0216_sli_splt.sli_max_num_m1 = 500; - regs->reg0216_sli_splt.sli_flsh = 1; - regs->reg0218_sli_cnum.sli_splt_cnum_m1 = 0; + regs->common.sli_splt.sli_splt = 1; + regs->common.sli_splt.sli_splt_mode = 0; + regs->common.sli_splt.sli_splt_cpst = 0; + regs->common.sli_splt.sli_max_num_m1 = 500; + regs->common.sli_splt.sli_flsh = 1; + regs->common.sli_cnum.sli_splt_cnum_m1 = 0; - regs->reg0217_sli_byte.sli_splt_byte = cfg->split_arg;//4096 - regs->reg0192_enc_pic.slen_fifo = 0; + regs->common.sli_byte.sli_splt_byte = cfg->split_arg;//4096 + regs->common.enc_pic.slen_fifo = 0; } break; case MPP_ENC_SPLIT_BY_CTU : { - regs->reg0216_sli_splt.sli_splt = 1; - regs->reg0216_sli_splt.sli_splt_mode = 1; - regs->reg0216_sli_splt.sli_splt_cpst = 0; - regs->reg0216_sli_splt.sli_max_num_m1 = 500; - regs->reg0216_sli_splt.sli_flsh = 1; - regs->reg0218_sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; + regs->common.sli_splt.sli_splt = 1; + regs->common.sli_splt.sli_splt_mode = 1; + regs->common.sli_splt.sli_splt_cpst = 0; + regs->common.sli_splt.sli_max_num_m1 = 500; + regs->common.sli_splt.sli_flsh = 1; + regs->common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1; - regs->reg0217_sli_byte.sli_splt_byte = 0; - regs->reg0192_enc_pic.slen_fifo = 0; + regs->common.sli_byte.sli_splt_byte = 0; + regs->common.enc_pic.slen_fifo = 0; } break; default : { mpp_log_f("invalide slice split mode %d\n", cfg->split_mode); @@ -1469,9 +1378,9 @@ MPP_RET hal_h265e_v510_gen_regs(void *hal, HalEncTask *task) RK_S32 pic_wd32, pic_h32; VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt; MppEncSliceSplit *slice_cfg = &ctx->cfg->split; - H265eVepu510ControlCfg *reg_ctl = ®s->reg_ctl; + Vepu510ControlCfg *reg_ctl = ®s->reg_ctl; H265eVepu510Frame *reg_frm = ®s->reg_frm; - H265eVepu510RcRoi *reg_klut = ®s->reg_rc_roi; + Vepu510RcRoi *reg_klut = ®s->reg_rc_roi; MPP_RET ret = MPP_OK; hal_h265e_enter(); @@ -1485,100 +1394,97 @@ MPP_RET hal_h265e_v510_gen_regs(void *hal, HalEncTask *task) memset(regs, 0, sizeof(H265eV510RegSet)); - reg_ctl->reg0004_enc_strt.lkt_num = 0; - reg_ctl->reg0004_enc_strt.vepu_cmd = ctx->enc_mode; - reg_ctl->reg0005_enc_clr.safe_clr = 0x0; - reg_ctl->reg0005_enc_clr.force_clr = 0x0; + reg_ctl->enc_strt.lkt_num = 0; + reg_ctl->enc_strt.vepu_cmd = ctx->enc_mode; + reg_ctl->enc_clr.safe_clr = 0x0; + reg_ctl->enc_clr.force_clr = 0x0; - reg_ctl->reg0008_int_en.enc_done_en = 1; - reg_ctl->reg0008_int_en.lkt_node_done_en = 1; - reg_ctl->reg0008_int_en.sclr_done_en = 1; - reg_ctl->reg0008_int_en.vslc_done_en = 1; - reg_ctl->reg0008_int_en.vbsf_oflw_en = 1; - reg_ctl->reg0008_int_en.vbuf_lens_en = 1; - reg_ctl->reg0008_int_en.enc_err_en = 1; - reg_ctl->reg0008_int_en.dvbm_fcfg_en = 1; - reg_ctl->reg0008_int_en.wdg_en = 1; - reg_ctl->reg0008_int_en.lkt_err_int_en = 0; - reg_ctl->reg0008_int_en.lkt_err_stop_en = 1; - reg_ctl->reg0008_int_en.lkt_force_stop_en = 1; - reg_ctl->reg0008_int_en.jslc_done_en = 1; - reg_ctl->reg0008_int_en.jbsf_oflw_en = 1; - reg_ctl->reg0008_int_en.jbuf_lens_en = 1; - reg_ctl->reg0008_int_en.dvbm_dcnt_en = 1; + reg_ctl->int_en.enc_done_en = 1; + reg_ctl->int_en.lkt_node_done_en = 1; + reg_ctl->int_en.sclr_done_en = 1; + reg_ctl->int_en.vslc_done_en = 1; + reg_ctl->int_en.vbsf_oflw_en = 1; + reg_ctl->int_en.vbuf_lens_en = 1; + reg_ctl->int_en.enc_err_en = 1; + reg_ctl->int_en.vsrc_err_en = 1; + reg_ctl->int_en.wdg_en = 1; + reg_ctl->int_en.lkt_err_int_en = 0; + reg_ctl->int_en.lkt_err_stop_en = 1; + reg_ctl->int_en.lkt_force_stop_en = 1; + reg_ctl->int_en.jslc_done_en = 1; + reg_ctl->int_en.jbsf_oflw_en = 1; + reg_ctl->int_en.jbuf_lens_en = 1; + reg_ctl->int_en.dvbm_err_en = 1; - reg_ctl->reg0012_dtrns_map.jpeg_bus_edin = 0x0; - reg_ctl->reg0012_dtrns_map.src_bus_edin = 0x0; - reg_ctl->reg0012_dtrns_map.meiw_bus_edin = 0x0; - reg_ctl->reg0012_dtrns_map.bsw_bus_edin = 0x7; - reg_ctl->reg0012_dtrns_map.lktr_bus_edin = 0x0; - reg_ctl->reg0012_dtrns_map.roir_bus_edin = 0x0; - reg_ctl->reg0012_dtrns_map.lktw_bus_edin = 0x0; - reg_ctl->reg0012_dtrns_map.rec_nfbc_bus_edin = 0x0; + reg_ctl->dtrns_map.jpeg_bus_edin = 0x0; + reg_ctl->dtrns_map.src_bus_edin = 0x0; + reg_ctl->dtrns_map.meiw_bus_edin = 0x0; + reg_ctl->dtrns_map.bsw_bus_edin = 0x7; + reg_ctl->dtrns_map.lktw_bus_edin = 0x0; + reg_ctl->dtrns_map.rec_nfbc_bus_edin = 0x0; - reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0; - reg_ctl->reg0014_enc_wdg.vs_load_thd = 0; - reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0; + reg_ctl->dtrns_cfg.axi_brsp_cke = 0x0; + reg_ctl->enc_wdg.vs_load_thd = 0; - reg_ctl->reg0021_func_en.cke = 1; - reg_ctl->reg0021_func_en.resetn_hw_en = 1; - reg_ctl->reg0021_func_en.rfpr_err_e = 1; + reg_ctl->opt_strg.cke = 1; + reg_ctl->opt_strg.resetn_hw_en = 1; + reg_ctl->opt_strg.rfpr_err_e = 1; - reg_frm->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; - reg_frm->reg0197_src_fill.pic_wfill = (syn->pp.pic_width & 0x7) - ? (8 - (syn->pp.pic_width & 0x7)) : 0; - reg_frm->reg0196_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1; - reg_frm->reg0197_src_fill.pic_hfill = (syn->pp.pic_height & 0x7) - ? (8 - (syn->pp.pic_height & 0x7)) : 0; + reg_frm->common.enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; + reg_frm->common.src_fill.pic_wfill = (syn->pp.pic_width & 0x7) + ? (8 - (syn->pp.pic_width & 0x7)) : 0; + reg_frm->common.enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1; + reg_frm->common.src_fill.pic_hfill = (syn->pp.pic_height & 0x7) + ? (8 - (syn->pp.pic_height & 0x7)) : 0; - reg_frm->reg0192_enc_pic.enc_stnd = 1; //H265 - reg_frm->reg0192_enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered - reg_frm->reg0192_enc_pic.bs_scp = 1; - reg_frm->reg0192_enc_pic.log2_ctu_num = mpp_ceil_log2(pic_wd32 * pic_h32); + reg_frm->common.enc_pic.enc_stnd = 1; //H265 + reg_frm->common.enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered + reg_frm->common.enc_pic.bs_scp = 1; + reg_frm->common.enc_pic.log2_ctu_num_hevc = mpp_ceil_log2(pic_wd32 * pic_h32); - reg_frm->reg0203_src_proc.src_mirr = 0; - reg_frm->reg0203_src_proc.src_rot = 0; - reg_frm->reg0203_src_proc.tile4x4_en = 0; + reg_frm->common.src_proc.src_mirr = 0; + reg_frm->common.src_proc.src_rot = 0; + reg_frm->common.src_proc.tile4x4_en = 0; reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 6 : (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC ? 9 : 6); - reg_frm->reg0216_sli_splt.sli_splt_mode = syn->sp.sli_splt_mode; - reg_frm->reg0216_sli_splt.sli_splt_cpst = syn->sp.sli_splt_cpst; - reg_frm->reg0216_sli_splt.sli_splt = syn->sp.sli_splt; - reg_frm->reg0216_sli_splt.sli_flsh = syn->sp.sli_flsh; - reg_frm->reg0216_sli_splt.sli_max_num_m1 = syn->sp.sli_max_num_m1; + reg_frm->common.sli_splt.sli_splt_mode = syn->sp.sli_splt_mode; + reg_frm->common.sli_splt.sli_splt_cpst = syn->sp.sli_splt_cpst; + reg_frm->common.sli_splt.sli_splt = syn->sp.sli_splt; + reg_frm->common.sli_splt.sli_flsh = syn->sp.sli_flsh; + reg_frm->common.sli_splt.sli_max_num_m1 = syn->sp.sli_max_num_m1; - reg_frm->reg0218_sli_cnum.sli_splt_cnum_m1 = syn->sp.sli_splt_cnum_m1; - reg_frm->reg0217_sli_byte.sli_splt_byte = syn->sp.sli_splt_byte; - reg_frm->reg0248_sao_cfg.sao_lambda_multi = 5; + reg_frm->common.sli_cnum.sli_splt_cnum_m1 = syn->sp.sli_splt_cnum_m1; + reg_frm->common.sli_byte.sli_splt_byte = syn->sp.sli_splt_byte; + reg_frm->sao_cfg.sao_lambda_multi = 5; setup_vepu510_split(reg_frm, &ctx->cfg->split); - reg_frm->reg0192_enc_pic.slen_fifo = slice_cfg->split_out ? 1 : 0; + reg_frm->common.enc_pic.slen_fifo = slice_cfg->split_out ? 1 : 0; if (ctx->task_cnt > 1) setup_vepu510_dual_core(ctx); vepu510_h265_set_me_regs(ctx, syn, reg_frm); - reg_frm->reg0232_rdo_cfg.chrm_spcl = 0; - reg_frm->reg0232_rdo_cfg.cu_inter_e = 0x0092; - reg_frm->reg0232_rdo_cfg.cu_intra_e = 0xe; - reg_frm->reg0232_rdo_cfg.lambda_qp_use_avg_cu16_flag = 1; - reg_frm->reg0232_rdo_cfg.yuvskip_calc_en = 1; - reg_frm->reg0232_rdo_cfg.atf_e = 1; - reg_frm->reg0232_rdo_cfg.atr_e = 1; + reg_frm->rdo_cfg.chrm_spcl = 0; + reg_frm->rdo_cfg.cu_inter_e = 0x0092; + reg_frm->rdo_cfg.cu_intra_e = 0xe; + reg_frm->rdo_cfg.lambda_qp_use_avg_cu16_flag = 1; + reg_frm->rdo_cfg.yuvskip_calc_en = 1; + reg_frm->rdo_cfg.atf_e = 1; + reg_frm->rdo_cfg.atr_e = 1; if (syn->pp.num_long_term_ref_pics_sps) { - reg_frm->reg0232_rdo_cfg.ltm_col = 0; - reg_frm->reg0232_rdo_cfg.ltm_idx0l0 = 1; + reg_frm->rdo_cfg.ltm_col = 0; + reg_frm->rdo_cfg.ltm_idx0l0 = 1; } else { - reg_frm->reg0232_rdo_cfg.ltm_col = 0; - reg_frm->reg0232_rdo_cfg.ltm_idx0l0 = 0; + reg_frm->rdo_cfg.ltm_col = 0; + reg_frm->rdo_cfg.ltm_idx0l0 = 0; } - reg_frm->reg0232_rdo_cfg.ccwa_e = 1; - reg_frm->reg0232_rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag; + reg_frm->rdo_cfg.ccwa_e = 1; + reg_frm->rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag; { RK_U32 i_nal_type = 0; @@ -1591,7 +1497,7 @@ MPP_RET hal_h265e_v510_gen_regs(void *hal, HalEncTask *task) } else { i_nal_type = NAL_TRAIL_R; } - reg_frm->reg0236_synt_nal.nal_unit_type = i_nal_type; + reg_frm->synt_nal.nal_unit_type = i_nal_type; } vepu510_h265_set_hw_address(ctx, reg_frm, task); @@ -1646,7 +1552,7 @@ MPP_RET hal_h265e_v510_start(void *hal, HalEncTask *enc_task) } cfg.reg = (RK_U32*)&hw_regs->reg_ctl; - cfg.size = sizeof(H265eVepu510ControlCfg); + cfg.size = sizeof(Vepu510ControlCfg); cfg.offset = VEPU510_CTL_OFFSET; ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); @@ -1657,7 +1563,7 @@ MPP_RET hal_h265e_v510_start(void *hal, HalEncTask *enc_task) if (hal_h265e_debug & HAL_H265E_DBG_CTL_REGS) { regs = (RK_U32*)&hw_regs->reg_ctl; - for (i = 0; i < sizeof(H265eVepu510ControlCfg) / 4; i++) { + for (i = 0; i < sizeof(Vepu510ControlCfg) / 4; i++) { hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]); } } @@ -1683,7 +1589,7 @@ MPP_RET hal_h265e_v510_start(void *hal, HalEncTask *enc_task) } } cfg.reg = &hw_regs->reg_rc_roi; - cfg.size = sizeof(H265eVepu510RcRoi); + cfg.size = sizeof(Vepu510RcRoi); cfg.offset = VEPU510_RC_ROI_OFFSET; ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); @@ -1694,7 +1600,7 @@ MPP_RET hal_h265e_v510_start(void *hal, HalEncTask *enc_task) if (hal_h265e_debug & HAL_H265E_DBG_RCKUT_REGS) { regs = (RK_U32*)&hw_regs->reg_rc_roi; - for (i = 0; i < sizeof(H265eVepu510RcRoi) / 4; i++) { + for (i = 0; i < sizeof(Vepu510RcRoi) / 4; i++) { hal_h265e_dbg_rckut("set reg[%04x]: 0%08x\n", i * 4, regs[i]); } } @@ -1717,7 +1623,7 @@ MPP_RET hal_h265e_v510_start(void *hal, HalEncTask *enc_task) } cfg.reg = &hw_regs->reg_sqi; - cfg.size = sizeof(Vepu510Sqi); + cfg.size = sizeof(H265eVepu510Sqi); cfg.offset = VEPU510_SQI_OFFSET; ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu510_reg.h b/mpp/hal/rkenc/h265e/hal_h265e_vepu510_reg.h index 3ec854bf..47cea722 100644 --- a/mpp/hal/rkenc/h265e/hal_h265e_vepu510_reg.h +++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu510_reg.h @@ -9,652 +9,94 @@ #include "rk_type.h" #include "vepu510_common.h" -/* class: control/link */ -/* 0x00000000 reg0 - 0x00000120 reg72 */ -typedef struct H265eVepu510ControlCfg_t { - /* 0x00000000 reg0 */ +typedef struct PreCstPar_t { struct { - RK_U32 sub_ver : 8; - RK_U32 h264_cap : 1; - RK_U32 hevc_cap : 1; - RK_U32 reserved : 2; - RK_U32 res_cap : 4; - RK_U32 osd_cap : 2; - RK_U32 filtr_cap : 2; - RK_U32 bfrm_cap : 1; - RK_U32 fbc_cap : 2; + RK_U32 madi_thd0 : 7; + RK_U32 reserved : 1; + RK_U32 madi_thd1 : 7; RK_U32 reserved1 : 1; - RK_U32 ip_id : 8; - } reg0001_version; + RK_U32 madi_thd2 : 7; + RK_U32 reserved2 : 1; + RK_U32 madi_thd3 : 7; + RK_U32 reserved3 : 1; + } cst_madi_thd0; - /* 0x4 - 0xc */ - RK_U32 reserved1_3[3]; - - /* 0x00000010 reg4 */ + /* 0x000020c4 reg2097 */ struct { - RK_U32 lkt_num : 8; - RK_U32 vepu_cmd : 3; - RK_U32 reserved : 21; - } reg0004_enc_strt; + RK_U32 madi_thd4 : 7; + RK_U32 reserved : 1; + RK_U32 madi_thd5 : 7; + RK_U32 reserved1 : 1; + RK_U32 madi_thd6 : 7; + RK_U32 reserved2 : 1; + RK_U32 madi_thd7 : 7; + RK_U32 reserved3 : 1; + } cst_madi_thd1; - /* 0x00000014 reg5 */ + /* 0x000020c8 reg2098 */ struct { - RK_U32 safe_clr : 1; - RK_U32 force_clr : 1; - RK_U32 reserved : 30; - } reg0005_enc_clr; + RK_U32 madi_thd8 : 7; + RK_U32 reserved : 1; + RK_U32 madi_thd9 : 7; + RK_U32 reserved1 : 1; + RK_U32 madi_thd10 : 7; + RK_U32 reserved2 : 1; + RK_U32 madi_thd11 : 7; + RK_U32 reserved3 : 1; + } cst_madi_thd2; - /* 0x18 */ + /* 0x000020cc reg2099 */ struct { - RK_U32 vswm_lcnt_soft : 14; - RK_U32 vswm_fcnt_soft : 8; - RK_U32 reserved : 2; - RK_U32 dvbm_ack_soft : 1; - RK_U32 dvbm_ack_sel : 1; - RK_U32 dvbm_inf_sel : 1; - RK_U32 reserved1 : 5; - } reg0006_vs_ldly; + RK_U32 madi_thd12 : 7; + RK_U32 reserved : 1; + RK_U32 madi_thd13 : 7; + RK_U32 reserved1 : 1; + RK_U32 mode_th : 3; + RK_U32 reserved2 : 1; + RK_U32 qp_thd : 6; + RK_U32 reserved3 : 6; + } cst_madi_thd3; - /* 0x1c */ - RK_U32 reserved007; - - /* 0x00000020 reg8 */ + /* 0x000020d0 reg2100 */ struct { - RK_U32 enc_done_en : 1; - RK_U32 lkt_node_done_en : 1; - RK_U32 sclr_done_en : 1; - RK_U32 vslc_done_en : 1; - RK_U32 vbsf_oflw_en : 1; - RK_U32 vbuf_lens_en : 1; - RK_U32 enc_err_en : 1; - RK_U32 dvbm_fcfg_en : 1; - RK_U32 wdg_en : 1; - RK_U32 lkt_err_int_en : 1; - RK_U32 lkt_err_stop_en : 1; - RK_U32 lkt_force_stop_en : 1; - RK_U32 jslc_done_en : 1; - RK_U32 jbsf_oflw_en : 1; - RK_U32 jbuf_lens_en : 1; - RK_U32 dvbm_dcnt_en : 1; - RK_U32 reserved : 16; - } reg0008_int_en; + RK_U32 wgt0 : 8; + RK_U32 wgt1 : 8; + RK_U32 wgt2 : 8; + RK_U32 wgt3 : 8; + } cst_wgt0; - /* 0x00000024 reg9 */ + /* 0x000020d4 reg2101 */ struct { - RK_U32 enc_done_msk : 1; - RK_U32 lkt_node_done_msk : 1; - RK_U32 sclr_done_msk : 1; - RK_U32 vslc_done_msk : 1; - RK_U32 vbsf_oflw_msk : 1; - RK_U32 vbuf_lens_msk : 1; - RK_U32 enc_err_msk : 1; - RK_U32 dvbm_fcfg_msk : 1; - RK_U32 wdg_msk : 1; - RK_U32 lkt_err_int_msk : 1; - RK_U32 lkt_err_stop_msk : 1; - RK_U32 lkt_force_stop_msk : 1; - RK_U32 jslc_done_msk : 1; - RK_U32 jbsf_oflw_msk : 1; - RK_U32 jbuf_lens_msk : 1; - RK_U32 dvbm_dcnt_msk : 1; - RK_U32 reserved : 16; - } reg0009_int_msk; + RK_U32 wgt4 : 8; + RK_U32 wgt5 : 8; + RK_U32 wgt6 : 8; + RK_U32 wgt7 : 8; + } cst_wgt1; - /* 0x00000028 reg10 */ + /* 0x000020d8 reg2102 */ struct { - RK_U32 enc_done_clr : 1; - RK_U32 lkt_node_done_clr : 1; - RK_U32 sclr_done_clr : 1; - RK_U32 vslc_done_clr : 1; - RK_U32 vbsf_oflw_clr : 1; - RK_U32 vbuf_lens_clr : 1; - RK_U32 enc_err_clr : 1; - RK_U32 dvbm_fcfg_clr : 1; - RK_U32 wdg_clr : 1; - RK_U32 lkt_err_int_clr : 1; - RK_U32 lkt_err_stop_clr : 1; - RK_U32 lkt_force_stop_clr : 1; - RK_U32 jslc_done_clr : 1; - RK_U32 jbsf_oflw_clr : 1; - RK_U32 jbuf_lens_clr : 1; - RK_U32 dvbm_dcnt_clr : 1; - RK_U32 reserved : 16; - } reg0010_int_clr; + RK_U32 wgt8 : 8; + RK_U32 wgt9 : 8; + RK_U32 wgt10 : 8; + RK_U32 wgt11 : 8; + } cst_wgt2; - /* 0x0000002c reg11 */ + /* 0x000020dc reg2103 */ struct { - RK_U32 enc_done_sta : 1; - RK_U32 lkt_node_done_sta : 1; - RK_U32 sclr_done_sta : 1; - RK_U32 vslc_done_sta : 1; - RK_U32 vbsf_oflw_sta : 1; - RK_U32 vbuf_lens_sta : 1; - RK_U32 enc_err_sta : 1; - RK_U32 dvbm_fcfg_sta : 1; - RK_U32 wdg_sta : 1; - RK_U32 lkt_err_int_sta : 1; - RK_U32 lkt_err_stop_sta : 1; - RK_U32 lkt_force_stop_sta : 1; - RK_U32 jslc_done_sta : 1; - RK_U32 jbsf_oflw_sta : 1; - RK_U32 jbuf_lens_sta : 1; - RK_U32 dvbm_dcnt_sta : 1; - RK_U32 reserved : 16; - } reg0011_int_sta; - - /* 0x00000030 reg12 */ - struct { - RK_U32 jpeg_bus_edin : 4; - RK_U32 src_bus_edin : 4; - RK_U32 meiw_bus_edin : 4; - RK_U32 bsw_bus_edin : 4; - RK_U32 lktr_bus_edin : 4; - RK_U32 roir_bus_edin : 4; - RK_U32 lktw_bus_edin : 4; - RK_U32 rec_nfbc_bus_edin : 4; - } reg0012_dtrns_map; - - /* 0x00000034 reg13 */ - struct { - RK_U32 reserved : 16; - RK_U32 axi_brsp_cke : 10; - RK_U32 reserved1 : 6; - } reg0013_dtrns_cfg; - - /* 0x00000038 reg14 */ - struct { - RK_U32 vs_load_thd : 24; - RK_U32 rfp_load_thd : 8; - } reg0014_enc_wdg; - - /* 0x0000003c reg15 */ - struct { - RK_U32 hurry_en : 1; - RK_U32 hurry_low : 3; - RK_U32 hurry_mid : 3; - RK_U32 hurry_high : 3; - RK_U32 reserved : 22; - } reg0015_qos_cfg; - - /* 0x00000040 reg16 */ - struct { - RK_U32 qos_period : 16; - RK_U32 reserved : 16; - } reg0016_qos_perd; - - /* 0x00000044 reg17 */ - RK_U32 reg0017_hurry_thd_low; - - /* 0x00000048 reg18 */ - RK_U32 reg0018_hurry_thd_mid; - - /* 0x0000004c reg19 */ - RK_U32 reg0019_hurry_thd_high; - - /* 0x00000050 reg20 */ - struct { - RK_U32 idle_en_core : 1; - RK_U32 idle_en_axi : 1; - RK_U32 idle_en_ahb : 1; - RK_U32 reserved : 29; - } reg0020_enc_idle_en; - - /* 0x00000054 reg21 */ - struct { - RK_U32 cke : 1; - RK_U32 resetn_hw_en : 1; - RK_U32 rfpr_err_e : 1; - RK_U32 sram_ckg_en : 1; - RK_U32 link_err_stop : 1; - RK_U32 reserved : 27; - } reg0021_func_en; - - /* 0x00000058 reg22 */ - struct { - RK_U32 recon32_ckg : 1; - RK_U32 iqit32_ckg : 1; - RK_U32 q32_ckg : 1; - RK_U32 t32_ckg : 1; - RK_U32 cabac32_ckg : 1; - RK_U32 recon16_ckg : 1; - RK_U32 iqit16_ckg : 1; - RK_U32 q16_ckg : 1; - RK_U32 t16_ckg : 1; - RK_U32 cabac16_ckg : 1; - RK_U32 recon8_ckg : 1; - RK_U32 iqit8_ckg : 1; - RK_U32 q8_ckg : 1; - RK_U32 t8_ckg : 1; - RK_U32 cabac8_ckg : 1; - RK_U32 recon4_ckg : 1; - RK_U32 iqit4_ckg : 1; - RK_U32 q4_ckg : 1; - RK_U32 t4_ckg : 1; - RK_U32 cabac4_ckg : 1; - RK_U32 intra32_ckg : 1; - RK_U32 intra16_ckg : 1; - RK_U32 intra8_ckg : 1; - RK_U32 intra4_ckg : 1; - RK_U32 inter_pred_ckg : 1; - RK_U32 reserved : 7; - } reg0022_rdo_ckg; - - /* 0x0000005c reg23 */ - struct { - RK_U32 core_id : 2; - RK_U32 reserved : 30; - } reg0023_enc_id; - - /* 0x00000060 reg24 */ - struct { - RK_U32 dvbm_en : 1; - RK_U32 src_badr_sel : 1; - RK_U32 vinf_frm_match : 1; - RK_U32 reserved : 1; - RK_U32 vrsp_half_cycle : 4; - RK_U32 reserved1 : 24; - } reg0024_dvbm_cfg; - - /* 0x00000064 - 0x6c*/ - RK_U32 reg025_027[3]; - - /* 0x00000070*/ - struct { - RK_U32 reserved : 4; - RK_U32 lkt_addr : 28; - } reg0028_lkt_base_addr; - - /* 0x74 - 0xfc */ - RK_U32 reserved29_63[35]; - - struct { - RK_U32 node_core_id : 2; - RK_U32 node_int : 1; - RK_U32 reserved : 1; - RK_U32 task_id : 12; - RK_U32 reserved1 : 16; - } reg0064_lkt_node_cfg; - - /* 0x00000104 reg65 */ - struct { - RK_U32 pcfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_pcfg : 28; - } reg0065_lkt_addr_pcfg; - - /* 0x00000108 reg66 */ - struct { - RK_U32 rc_cfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_rc_cfg : 28; - } reg0066_lkt_addr_rc_cfg; - - /* 0x0000010c reg67 */ - struct { - RK_U32 par_cfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_par_cfg : 28; - } reg0067_lkt_addr_par_cfg; - - /* 0x00000110 reg68 */ - struct { - RK_U32 sqi_cfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_sqi_cfg : 28; - } reg0068_lkt_addr_sqi_cfg; - - /* 0x00000114 reg69 */ - struct { - RK_U32 scal_cfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_scal_cfg : 28; - } reg0069_lkt_addr_scal_cfg; - - /* 0x00000118 reg70 */ - struct { - RK_U32 pp_cfg_rd_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_pp_cfg : 28; - } reg0070_lkt_addr_osd_cfg; - - /* 0x0000011c reg71 */ - struct { - RK_U32 st_out_en : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_st : 28; - } reg0071_lkt_addr_st; - - /* 0x00000120 reg72 */ - struct { - RK_U32 nxt_node_vld : 1; - RK_U32 reserved : 3; - RK_U32 lkt_addr_nxt : 28; - } reg0072_lkt_addr_nxt; -} H265eVepu510ControlCfg; + RK_U32 wgt12 : 8; + RK_U32 wgt13 : 8; + RK_U32 wgt14 : 8; + RK_U32 lambda_mv_bit_0 : 3; + RK_U32 reserved : 1; + RK_U32 lambda_mv_bit_1 : 3; + RK_U32 anti_strp_e : 1; + } cst_wgt3; +} pre_cst_par; /* class: buffer/video syntax */ -/* 0x00000280 reg160 - 0x000003f4 reg253*/ +/* 0x00000270 reg156 - 0x000003f4 reg253*/ typedef struct H265eVepu510Frame_t { - vepu510_online online_addr; - /* 0x00000280 reg160 */ - RK_U32 reg0160_adr_src0; - - /* 0x00000284 reg161 */ - RK_U32 reg0161_adr_src1; - - /* 0x00000288 reg162 */ - RK_U32 reg0162_adr_src2; - - /* 0x0000028c reg163 */ - RK_U32 reg0163_rfpw_h_addr; - - /* 0x00000290 reg164 */ - RK_U32 reg0164_rfpw_b_addr; - - /* 0x00000294 reg165 */ - RK_U32 reg0165_rfpr_h_addr; - - /* 0x00000298 reg166 */ - RK_U32 reg0166_rfpr_b_addr; - - /* 0x0000029c reg167 */ - RK_U32 reg0167_cmvw_addr; - - /* 0x000002a0 reg168 */ - RK_U32 reg0168_cmvr_addr; - - /* 0x000002a4 reg169 */ - RK_U32 reg0169_dspw_addr; - - /* 0x000002a8 reg170 */ - RK_U32 reg0170_dspr_addr; - - /* 0x000002ac reg171 */ - RK_U32 reg0171_meiw_addr; - - /* 0x000002b0 reg172 */ - RK_U32 reg0172_bsbt_addr; - - /* 0x000002b4 reg173 */ - RK_U32 reg0173_bsbb_addr; - - /* 0x000002b8 reg174 */ - RK_U32 reg0174_adr_bsbs; - - /* 0x000002bc reg175 */ - RK_U32 reg0175_bsbr_addr; - - /* 0x000002c0 reg176 */ - RK_U32 reg0176_lpfw_addr; - - /* 0x000002c4 reg177 */ - RK_U32 reg0177_lpfr_addr; - - /* 0x000002c8 reg178 */ - RK_U32 reg0178_adr_ebuft; - - /* 0x000002cc reg179 */ - RK_U32 reg0179_adr_ebufb; - - /* 0x000002d0 reg180 */ - RK_U32 reg0180_adr_rfpt_h; - - /* 0x000002d4 reg181 */ - RK_U32 reg0181_adr_rfpb_h; - - /* 0x000002d8 reg182 */ - RK_U32 reg0182_adr_rfpt_b; - - /* 0x000002dc reg183 */ - RK_U32 reg0183_adr_rfpb_b; - - /* 0x000002e0 reg184 */ - RK_U32 reg0184_adr_smr_rd; - - /* 0x000002e4 reg185 */ - RK_U32 reg0185_adr_smr_wr; - - /* 0x000002e8 reg186 */ - RK_U32 reg0186_adr_roir; - - /* 0x2ec - 0x2fc */ - RK_U32 reserved187_191[5]; - - /* 0x00000300 reg192 */ - struct { - RK_U32 enc_stnd : 2; - RK_U32 cur_frm_ref : 1; - RK_U32 mei_stor : 1; - RK_U32 bs_scp : 1; - RK_U32 reserved : 3; - RK_U32 pic_qp : 6; - RK_U32 num_pic_tot_cur : 5; - RK_U32 log2_ctu_num : 5; - RK_U32 reserved1 : 6; - RK_U32 slen_fifo : 1; - RK_U32 rec_fbc_dis : 1; - } reg0192_enc_pic; - - /* 0x00000304 reg193 */ - struct { - RK_U32 dchs_txid : 2; - RK_U32 dchs_rxid : 2; - RK_U32 dchs_txe : 1; - RK_U32 dchs_rxe : 1; - RK_U32 reserved : 2; - RK_U32 dchs_dly : 8; - RK_U32 dchs_ofst : 10; - RK_U32 reserved1 : 6; - } reg0193_dual_core; - - /* 0x00000308 reg194 */ - struct { - RK_U32 frame_id : 8; - RK_U32 frm_id_match : 1; - RK_U32 reserved : 7; - RK_U32 ch_id : 2; - RK_U32 vrsp_rtn_en : 1; - RK_U32 vinf_req_en : 1; - RK_U32 reserved1 : 12; - } reg0194_enc_id; - - /* 0x0000030c reg195 */ - RK_U32 bsp_size; - - /* 0x00000310 reg196 */ - struct { - RK_U32 pic_wd8_m1 : 11; - RK_U32 reserved : 5; - RK_U32 pic_hd8_m1 : 11; - RK_U32 reserved1 : 5; - } reg0196_enc_rsl; - - /* 0x00000314 reg197 */ - struct { - RK_U32 pic_wfill : 6; - RK_U32 reserved : 10; - RK_U32 pic_hfill : 6; - RK_U32 reserved1 : 10; - } reg0197_src_fill; - - /* 0x00000318 reg198 */ - struct { - RK_U32 alpha_swap : 1; - RK_U32 rbuv_swap : 1; - RK_U32 src_cfmt : 4; - RK_U32 src_rcne : 1; - RK_U32 out_fmt : 1; - RK_U32 src_range_trns_en : 1; - RK_U32 src_range_trns_sel : 1; - RK_U32 chroma_ds_mode : 1; - RK_U32 reserved : 21; - } reg0198_src_fmt; - - /* 0x0000031c reg199 */ - struct { - RK_U32 csc_wgt_b2y : 9; - RK_U32 csc_wgt_g2y : 9; - RK_U32 csc_wgt_r2y : 9; - RK_U32 reserved : 5; - } reg0199_src_udfy; - - /* 0x00000320 reg200 */ - struct { - RK_U32 csc_wgt_b2u : 9; - RK_U32 csc_wgt_g2u : 9; - RK_U32 csc_wgt_r2u : 9; - RK_U32 reserved : 5; - } reg0200_src_udfu; - - /* 0x00000324 reg201 */ - struct { - RK_U32 csc_wgt_b2v : 9; - RK_U32 csc_wgt_g2v : 9; - RK_U32 csc_wgt_r2v : 9; - RK_U32 reserved : 5; - } reg0201_src_udfv; - - /* 0x00000328 reg202 */ - struct { - RK_U32 csc_ofst_v : 8; - RK_U32 csc_ofst_u : 8; - RK_U32 csc_ofst_y : 5; - RK_U32 reserved : 11; - } reg0202_src_udfo; - - /* 0x0000032c reg203 */ - struct { - RK_U32 cr_force_value : 8; - RK_U32 cb_force_value : 8; - RK_U32 chroma_force_en : 1; - RK_U32 reserved : 9; - RK_U32 src_mirr : 1; - RK_U32 src_rot : 2; - RK_U32 tile4x4_en : 1; - RK_U32 reserved1 : 2; - } reg0203_src_proc; - - /* 0x00000330 reg204 */ - struct { - RK_U32 pic_ofst_x : 14; - RK_U32 reserved : 2; - RK_U32 pic_ofst_y : 14; - RK_U32 reserved1 : 2; - } reg0204_pic_ofst; - - /* 0x00000334 reg205 */ - struct { - RK_U32 src_strd0 : 21; - RK_U32 reserved : 11; - } reg0205_src_strd0; - - /* 0x00000338 reg206 */ - struct { - RK_U32 src_strd1 : 16; - RK_U32 reserved : 16; - } reg0206_src_strd1; - - /* 0x0000033c reg207 */ - struct { - RK_U32 pp_corner_filter_strength : 2; - RK_U32 reserved : 2; - RK_U32 pp_edge_filter_strength : 2; - RK_U32 reserved1 : 2; - RK_U32 pp_internal_filter_strength : 2; - RK_U32 reserved2 : 22; - } reg0207_src_flt_cfg; - - /* 0x340 - 0x34c */ - RK_U32 reserved208_211[4]; - - /* 0x00000350 reg212 */ - struct { - RK_U32 rc_en : 1; - RK_U32 aq_en : 1; - RK_U32 reserved : 10; - RK_U32 rc_ctu_num : 20; - } reg212_rc_cfg; - - /* 0x00000354 reg213 */ - struct { - RK_U32 reserved : 16; - RK_U32 rc_qp_range : 4; - RK_U32 rc_max_qp : 6; - RK_U32 rc_min_qp : 6; - } reg213_rc_qp; - - /* 0x00000358 reg214 */ - struct { - RK_U32 ctu_ebit : 20; - RK_U32 reserved : 12; - } reg214_rc_tgt; - - /* 0x35c */ - RK_U32 reserved_215; - - /* 0x00000360 reg216 */ - struct { - RK_U32 sli_splt : 1; - RK_U32 sli_splt_mode : 1; - RK_U32 sli_splt_cpst : 1; - RK_U32 reserved : 12; - RK_U32 sli_flsh : 1; - RK_U32 sli_max_num_m1 : 15; - RK_U32 reserved1 : 1; - } reg0216_sli_splt; - - /* 0x00000364 reg217 */ - struct { - RK_U32 sli_splt_byte : 20; - RK_U32 reserved : 12; - } reg0217_sli_byte; - - /* 0x00000368 reg218 */ - struct { - RK_U32 sli_splt_cnum_m1 : 20; - RK_U32 reserved : 12; - } reg0218_sli_cnum; - - /* 0x0000036c reg219 */ - struct { - RK_U32 uvc_partition0_len : 12; - RK_U32 uvc_partition_len : 12; - RK_U32 uvc_skip_len : 6; - RK_U32 reserved : 2; - } reg0218_uvc_cfg; - - /* 0x00000370 reg220 */ - struct { - RK_U32 cime_srch_dwnh : 4; - RK_U32 cime_srch_uph : 4; - RK_U32 cime_srch_rgtw : 4; - RK_U32 cime_srch_lftw : 4; - RK_U32 dlt_frm_num : 16; - } reg0220_me_rnge; - - /* 0x00000374 reg221 */ - struct { - RK_U32 srgn_max_num : 7; - RK_U32 cime_dist_thre : 13; - RK_U32 rme_srch_h : 2; - RK_U32 rme_srch_v : 2; - RK_U32 rme_dis : 3; - RK_U32 reserved1 : 1; - RK_U32 fme_dis : 3; - RK_U32 reserved2 : 1; - } reg0221_me_cfg; - - /* 0x00000378 reg222 */ - struct { - RK_U32 cime_zero_thre : 13; - RK_U32 reserved : 15; - RK_U32 fme_prefsu_en : 2; - RK_U32 colmv_stor : 1; - RK_U32 colmv_load : 1; - } reg0222_me_cach; - - /* 0x37c - 0x39c */ - RK_U32 reserved223_231[9]; + Vepu510FrmCommon common; /* 0x000003a0 reg232 */ struct { @@ -671,13 +113,13 @@ typedef struct H265eVepu510Frame_t { RK_U32 atf_e : 1; RK_U32 atr_e : 1; RK_U32 reserved1 : 2; - } reg0232_rdo_cfg; + } rdo_cfg; /* 0x000003a4 reg233 */ struct { RK_U32 rdo_mark_mode : 9; RK_U32 reserved : 23; - } reg0233_iprd_csts; + } iprd_csts; /* 0x3a8 - 0x3ac */ RK_U32 reserved234_235[2]; @@ -686,7 +128,7 @@ typedef struct H265eVepu510Frame_t { struct { RK_U32 nal_unit_type : 6; RK_U32 reserved : 26; - } reg0236_synt_nal; + } synt_nal; /* 0x000003b4 reg237 */ struct { @@ -698,7 +140,7 @@ typedef struct H265eVepu510Frame_t { RK_U32 log2_max_poc_lsb : 4; RK_U32 strg_intra_smth : 1; RK_U32 reserved : 11; - } reg0237_synt_sps; + } synt_sps; /* 0x000003b8 reg238 */ struct { @@ -718,7 +160,7 @@ typedef struct H265eVepu510Frame_t { RK_U32 lpf_fltr_acrs_til : 1; RK_U32 csip_flag : 1; RK_U32 reserved : 9; - } reg0238_synt_pps; + } synt_pps; /* 0x000003bc reg239 */ struct { @@ -740,7 +182,7 @@ typedef struct H265eVepu510Frame_t { RK_U32 dpdnt_sli_seg_flg : 1; RK_U32 sli_pps_id : 6; RK_U32 no_out_pri_pic : 1; - } reg0239_synt_sli0; + } synt_sli0; /* 0x000003c0 reg240 */ struct { @@ -757,14 +199,14 @@ typedef struct H265eVepu510Frame_t { RK_U32 col_frm_l0_flg : 1; RK_U32 lst_entry_l0 : 4; RK_U32 reserved1 : 1; - } reg0240_synt_sli1; + } synt_sli1; /* 0x000003c4 reg241 */ struct { RK_U32 sli_poc_lsb : 16; RK_U32 sli_hdr_ext_len : 9; RK_U32 reserved : 7; - } reg0241_synt_sli2; + } synt_sli2; /* 0x000003c8 reg242 */ struct { @@ -774,7 +216,7 @@ typedef struct H265eVepu510Frame_t { RK_U32 num_lt_pic : 2; RK_U32 st_ref_pic_idx : 6; RK_U32 num_lt_sps : 2; - } reg0242_synt_refm0; + } synt_refm0; /* 0x000003cc reg243 */ struct { @@ -788,36 +230,36 @@ typedef struct H265eVepu510Frame_t { RK_U32 used_by_lt_flg0 : 1; RK_U32 used_by_lt_flg1 : 1; RK_U32 used_by_lt_flg2 : 1; - } reg0243_synt_refm1; + } synt_refm1; /* 0x000003d0 reg244 */ struct { RK_U32 dlt_poc_s0_m10 : 16; RK_U32 dlt_poc_s0_m11 : 16; - } reg0244_synt_refm2; + } synt_refm2; /* 0x000003d4 reg245 */ struct { RK_U32 dlt_poc_s0_m12 : 16; RK_U32 dlt_poc_s0_m13 : 16; - } reg0245_synt_refm3; + } synt_refm3; /* 0x000003d8 reg246 */ struct { RK_U32 poc_lsb_lt1 : 16; RK_U32 poc_lsb_lt2 : 16; - } reg0246_synt_long_refm0; + } synt_long_refm0; /* 0x000003dc reg247 */ struct { RK_U32 dlt_poc_msb_cycl1 : 16; RK_U32 dlt_poc_msb_cycl2 : 16; - } reg0247_synt_long_refm1; + } synt_long_refm1; struct { RK_U32 sao_lambda_multi : 3; RK_U32 reserved : 29; - } reg0248_sao_cfg; + } sao_cfg; /* 0x3e4 - 0x3ec */ RK_U32 reserved249_251[3]; @@ -829,7 +271,7 @@ typedef struct H265eVepu510Frame_t { RK_U32 tile_h_m1 : 9; RK_U32 reserved1 : 6; RK_U32 tile_en : 1; - } reg0252_tile_cfg; + } tile_cfg; /* 0x000003f4 reg253 */ struct { @@ -837,210 +279,23 @@ typedef struct H265eVepu510Frame_t { RK_U32 reserved : 7; RK_U32 tile_y : 9; RK_U32 reserved1 : 7; - } reg0253_tile_pos; - - /* 0x3f8 - 0x3fc */ - RK_U32 reserved254_255[2]; + } tile_pos_hevc; } H265eVepu510Frame; -/* class: rc/roi/aq/klut */ -/* 0x00001000 reg1024 - 0x0000110c reg1091 */ -typedef struct H265eVepu510RcRoi_t { - /* 0x00001000 reg1024 */ - struct { - RK_U32 qp_adj0 : 5; - RK_U32 qp_adj1 : 5; - RK_U32 qp_adj2 : 5; - RK_U32 qp_adj3 : 5; - RK_U32 qp_adj4 : 5; - RK_U32 reserved : 7; - } rc_adj0; - - /* 0x00001004 reg1025 */ - struct { - RK_U32 qp_adj5 : 5; - RK_U32 qp_adj6 : 5; - RK_U32 qp_adj7 : 5; - RK_U32 qp_adj8 : 5; - RK_U32 reserved : 12; - } rc_adj1; - - /* 0x00001008 reg1026 - 0x00001028 reg1034 */ - RK_U32 rc_dthd_0_8[9]; - - /* 0x102c */ - RK_U32 reserved_1035; - - /* 0x00001030 reg1036 */ - struct { - RK_U32 qpmin_area0 : 6; - RK_U32 qpmax_area0 : 6; - RK_U32 qpmin_area1 : 6; - RK_U32 qpmax_area1 : 6; - RK_U32 qpmin_area2 : 6; - RK_U32 reserved : 2; - } roi_qthd0; - - /* 0x00001034 reg1037 */ - struct { - RK_U32 qpmax_area2 : 6; - RK_U32 qpmin_area3 : 6; - RK_U32 qpmax_area3 : 6; - RK_U32 qpmin_area4 : 6; - RK_U32 qpmax_area4 : 6; - RK_U32 reserved : 2; - } roi_qthd1; - - /* 0x00001038 reg1038 */ - struct { - RK_U32 qpmin_area5 : 6; - RK_U32 qpmax_area5 : 6; - RK_U32 qpmin_area6 : 6; - RK_U32 qpmax_area6 : 6; - RK_U32 qpmin_area7 : 6; - RK_U32 reserved : 2; - } roi_qthd2; - - /* 0x0000103c reg1039 */ - struct { - RK_U32 qpmax_area7 : 6; - RK_U32 reserved : 24; - RK_U32 qpmap_mode : 2; - } roi_qthd3; - - /* 0x00001040 reg1040 */ - RK_U32 reserved_1040; - - /* 0x00001044 reg1041 */ - struct { - RK_U32 aq_tthd0 : 8; - RK_U32 aq_tthd1 : 8; - RK_U32 aq_tthd2 : 8; - RK_U32 aq_tthd3 : 8; - } aq_tthd0; - - /* 0x00001048 reg1042 */ - struct { - RK_U32 aq_tthd4 : 8; - RK_U32 aq_tthd5 : 8; - RK_U32 aq_tthd6 : 8; - RK_U32 aq_tthd7 : 8; - } aq_tthd1; - - /* 0x0000104c reg1043 */ - struct { - RK_U32 aq_tthd8 : 8; - RK_U32 aq_tthd9 : 8; - RK_U32 aq_tthd10 : 8; - RK_U32 aq_tthd11 : 8; - } aq_tthd2; - - /* 0x00001050 reg1044 */ - struct { - RK_U32 aq_tthd12 : 8; - RK_U32 aq_tthd13 : 8; - RK_U32 aq_tthd14 : 8; - RK_U32 aq_tthd15 : 8; - } aq_tthd3; - - /* 0x00001054 reg1045 */ - struct { - RK_U32 aq_stp_s0 : 5; - RK_U32 aq_stp_0t1 : 5; - RK_U32 aq_stp_1t2 : 5; - RK_U32 aq_stp_2t3 : 5; - RK_U32 aq_stp_3t4 : 5; - RK_U32 aq_stp_4t5 : 5; - RK_U32 reserved : 2; - } aq_stp0; - - /* 0x00001058 reg1046 */ - struct { - RK_U32 aq_stp_5t6 : 5; - RK_U32 aq_stp_6t7 : 5; - RK_U32 aq_stp_7t8 : 5; - RK_U32 aq_stp_8t9 : 5; - RK_U32 aq_stp_9t10 : 5; - RK_U32 aq_stp_10t11 : 5; - RK_U32 reserved : 2; - } aq_stp1; - - /* 0x0000105c reg1047 */ - struct { - RK_U32 aq_stp_11t12 : 5; - RK_U32 aq_stp_12t13 : 5; - RK_U32 aq_stp_13t14 : 5; - RK_U32 aq_stp_14t15 : 5; - RK_U32 aq_stp_b15 : 5; - RK_U32 reserved : 7; - } aq_stp2; - - /* 0x00001060 reg1048 */ - struct { - RK_U32 aq16_rnge : 4; - RK_U32 aq32_rnge : 4; - RK_U32 aq8_rnge : 5; - RK_U32 aq16_dif0 : 5; - RK_U32 aq16_dif1 : 5; - RK_U32 reserved : 1; - RK_U32 aq_cme_en : 1; - RK_U32 aq_subj_cme_en : 1; - RK_U32 aq_rme_en : 1; - RK_U32 aq_subj_rme_en : 1; - RK_U32 reserved1 : 4; - } aq_clip; - - /* 0x00001064 reg1049 */ - struct { - RK_U32 madi_th0 : 8; - RK_U32 madi_th1 : 8; - RK_U32 madi_th2 : 8; - RK_U32 reserved : 8; - } madi_st_thd; - - /* 0x00001068 reg1050 */ - struct { - RK_U32 madp_th0 : 12; - RK_U32 reserved : 4; - RK_U32 madp_th1 : 12; - RK_U32 reserved1 : 4; - } madp_st_thd0; - - /* 0x0000106c reg1051 */ - struct { - RK_U32 madp_th2 : 12; - RK_U32 reserved : 20; - } madp_st_thd1; - - /* 0x1078 - 0x107c */ - RK_U32 reserved1052_1054[3]; - - /* 0x0000107c reg1055 */ - struct { - RK_U32 chrm_klut_ofst : 4; - RK_U32 reserved : 4; - RK_U32 inter_chrm_dist_multi : 6; - RK_U32 reserved1 : 18; - } klut_ofst; - - /*0x00001080 reg1056 - 0x0000110c reg1091 */ - Vepu510RoiCfg roi_cfg; -} H265eVepu510RcRoi; - -/* class: iprd/iprd_wgt/rdo_wgta/prei_dif*/ -/* 0x00001700 reg1472 - 0x00001cd4 reg1845 */ +/* class: param */ +/* 0x00001700 reg1472 - 0x000019cc reg1651 */ typedef struct H265eVepu510Param_t { - /* 0x00001700 - 0x0000172c reg1472 */ - RK_U32 reserved1472_1483[12]; + /* 0x00001700 reg1472 - 0x0000172c reg1483*/ + RK_U32 reserved_1472_1483[12]; /* 0x00001730 reg1484 */ struct { - RK_U32 qnt_bias_i : 10; - RK_U32 qnt_bias_p : 10; - RK_U32 reserved : 12; - } reg1484_qnt_bias_comb; + RK_U32 qnt_f_bias_i : 10; + RK_U32 qnt_f_bias_p : 10; + RK_U32 reserve : 12; + } qnt_bias_comb; - /* 0x1734 - 0x175c */ + /* 0x00001734 reg1485 - 0x0000175c reg1495*/ RK_U32 reserved1485_1495[11]; /* 0x00001760 reg1496 */ @@ -1054,7 +309,7 @@ typedef struct H265eVepu510Param_t { RK_U32 rime_prelvl_en : 2; RK_U32 rime_prersu_en : 3; RK_U32 reserved1 : 17; - } me_sqi_cfg; + } me_sqi_comb; /* 0x00001764 reg1497 */ struct { @@ -1064,13 +319,13 @@ typedef struct H265eVepu510Param_t { RK_U32 reserved1 : 1; RK_U32 cime_mvd_th2 : 9; RK_U32 reserved2 : 3; - } cime_mvd_th; + } cime_mvd_th_comb; /* 0x00001768 reg1498 */ struct { RK_U32 cime_madp_th : 12; RK_U32 reserved : 20; - } cime_madp_th; + } cime_madp_th_comb; /* 0x0000176c reg1499 */ struct { @@ -1078,7 +333,7 @@ typedef struct H265eVepu510Param_t { RK_U32 cime_multi1 : 8; RK_U32 cime_multi2 : 8; RK_U32 cime_multi3 : 8; - } cime_multi; + } cime_multi_comb; /* 0x00001770 reg1500 */ struct { @@ -1088,7 +343,7 @@ typedef struct H265eVepu510Param_t { RK_U32 reserved1 : 9; RK_U32 fme_madp_th : 12; RK_U32 reserved2 : 4; - } rime_mvd_th; + } rime_mvd_th_comb; /* 0x00001774 reg1501 */ struct { @@ -1096,7 +351,7 @@ typedef struct H265eVepu510Param_t { RK_U32 reserved : 4; RK_U32 rime_madp_th1 : 12; RK_U32 reserved1 : 4; - } rime_madp_th; + } rime_madp_th_comb; /* 0x00001778 reg1502 */ struct { @@ -1104,7 +359,7 @@ typedef struct H265eVepu510Param_t { RK_U32 rime_multi1 : 10; RK_U32 rime_multi2 : 10; RK_U32 reserved : 2; - } rime_multi; + } rime_multi_comb; /* 0x0000177c reg1503 */ struct { @@ -1112,13 +367,12 @@ typedef struct H265eVepu510Param_t { RK_U32 cmv_th1 : 8; RK_U32 cmv_th2 : 8; RK_U32 reserved : 8; - } cmv_st_th; + } cmv_st_th_comb; /* 0x1780 - 0x17fc */ RK_U32 reserved1504_1535[32]; - /* 0x1800 - 0x18cc */ - // rmd_inter_wgt_qp0_51 + /* 0x00001800 reg1536 - 0x000018cc reg1587*/ RK_U32 pprd_lamb_satd_0_51[52]; /* 0x000018d0 reg1588 */ @@ -1130,12 +384,13 @@ typedef struct H265eVepu510Param_t { /* 0x18d4 - 0x18fc */ RK_U32 reserved1589_1599[11]; - /* wgt_qp48_grpa */ - /* 0x00001900 reg1600 */ + /* 0x00001900 reg1600 - 0x000019cc reg1651*/ RK_U32 rdo_wgta_qp_grpa_0_51[52]; } H265eVepu510Param; -typedef struct H265eVepu510SubjOpt_t { +/* class: rdo/q_i */ +/* 0x00002000 reg2048 - 0x000020fc reg2111 */ +typedef struct H265eVepu510SqiCfg_t { /* 0x00002000 reg2048 */ struct { RK_U32 subj_opt_en : 1; @@ -1361,16 +616,204 @@ typedef struct H265eVepu510SubjOpt_t { /* 0x2058 - 0x205c */ RK_U32 reserved2070_2071[2]; -} H265eVepu510SubjOpt; + + /* 0x00002060 reg2072 - 0x0000206c reg2075 */ + rdo_skip_par rdo_b32_skip; + + /* 0x00002070 reg2076 - 0x0000207c reg2079*/ + rdo_skip_par rdo_b16_skip; + + /* 0x00002080 reg2080 - 0x00002088 reg2082 */ + rdo_noskip_par rdo_b32_inter; + + /* 0x0000208c reg2083 - 0x00002094 reg2085 */ + rdo_noskip_par rdo_b16_inter; + + /* 0x00002098 reg2086 - 0x000020a4 reg2088 */ + rdo_noskip_par rdo_b32_intra; + + /* 0x000020a8 reg2089 - 0x000020ac reg2091 */ + rdo_noskip_par rdo_b16_intra; + + /* 0x000020b0 reg2092 */ + struct { + RK_U32 blur_low_madi_thd : 7; + RK_U32 reserved : 1; + RK_U32 blur_high_madi_thd : 7; + RK_U32 reserved1 : 1; + RK_U32 blur_low_cnt_thd : 4; + RK_U32 blur_hight_cnt_thd : 4; + RK_U32 blur_sum_cnt_thd : 4; + RK_U32 anti_blur_en : 1; + RK_U32 reserved2 : 3; + } subj_anti_blur_thd; + + /* 0x000020b4 reg2093 */ + struct { + RK_U32 blur_motion_thd : 12; + RK_U32 sao_ofst_thd_eo_luma : 3; + RK_U32 reserved : 1; + RK_U32 sao_ofst_thd_bo_luma : 3; + RK_U32 reserved1 : 1; + RK_U32 sao_ofst_thd_eo_chroma : 3; + RK_U32 reserved2 : 1; + RK_U32 sao_ofst_thd_bo_chroma : 3; + RK_U32 reserved3 : 5; + } subj_anti_blur_sao; + + /* 0x000020b8 reg2094 - 0x000020bc reg2095*/ + RK_U32 reserved_2094_2095[2]; + + /* 0x000020c0 reg2096 - 0x000020dc reg2103 */ + pre_cst_par preintra32_cst; + + /* 0x000020e0 reg2104 - 0x000020fc reg2111 */ + pre_cst_par preintra16_cst; + + /* 0x00002100 reg2112 */ + struct { + RK_U32 base_thre_rough_mad32_intra : 4; + RK_U32 delta0_thre_rough_mad32_intra : 4; + RK_U32 delta1_thre_rough_mad32_intra : 6; + RK_U32 delta2_thre_rough_mad32_intra : 6; + RK_U32 delta3_thre_rough_mad32_intra : 7; + RK_U32 delta4_thre_rough_mad32_intra_low5 : 5; + } cudecis_thd0; + + /* 0x00002104 reg2113 */ + struct { + RK_U32 delta4_thre_rough_mad32_intra_high2 : 2; + RK_U32 delta5_thre_rough_mad32_intra : 7; + RK_U32 delta6_thre_rough_mad32_intra : 7; + RK_U32 base_thre_fine_mad32_intra : 4; + RK_U32 delta0_thre_fine_mad32_intra : 4; + RK_U32 delta1_thre_fine_mad32_intra : 5; + RK_U32 delta2_thre_fine_mad32_intra_low3 : 3; + } cudecis_thd1; + + /* 0x00002108 reg2114 */ + struct { + RK_U32 delta2_thre_fine_mad32_intra_high2 : 2; + RK_U32 delta3_thre_fine_mad32_intra : 5; + RK_U32 delta4_thre_fine_mad32_intra : 5; + RK_U32 delta5_thre_fine_mad32_intra : 6; + RK_U32 delta6_thre_fine_mad32_intra : 6; + RK_U32 base_thre_str_edge_mad32_intra : 3; + RK_U32 delta0_thre_str_edge_mad32_intra : 2; + RK_U32 delta1_thre_str_edge_mad32_intra : 3; + } cudecis_thd2; + + /* 0x0000210c reg2115 */ + struct { + RK_U32 delta2_thre_str_edge_mad32_intra : 3; + RK_U32 delta3_thre_str_edge_mad32_intra : 4; + RK_U32 base_thre_str_edge_bgrad32_intra : 5; + RK_U32 delta0_thre_str_edge_bgrad32_intra : 2; + RK_U32 delta1_thre_str_edge_bgrad32_intra : 3; + RK_U32 delta2_thre_str_edge_bgrad32_intra : 4; + RK_U32 delta3_thre_str_edge_bgrad32_intra : 5; + RK_U32 base_thre_mad16_intra : 3; + RK_U32 delta0_thre_mad16_intra : 3; + } cudecis_thd3; + + /* 0x00002110 reg2116 */ + struct { + RK_U32 delta1_thre_mad16_intra : 3; + RK_U32 delta2_thre_mad16_intra : 4; + RK_U32 delta3_thre_mad16_intra : 5; + RK_U32 delta4_thre_mad16_intra : 5; + RK_U32 delta5_thre_mad16_intra : 6; + RK_U32 delta6_thre_mad16_intra : 6; + RK_U32 delta0_thre_mad16_ratio_intra : 3; + } cudecis_thd4; + + /* 0x00002114 reg2117 */ + struct { + RK_U32 delta1_thre_mad16_ratio_intra : 3; + RK_U32 delta2_thre_mad16_ratio_intra : 3; + RK_U32 delta3_thre_mad16_ratio_intra : 3; + RK_U32 delta4_thre_mad16_ratio_intra : 3; + RK_U32 delta5_thre_mad16_ratio_intra : 3; + RK_U32 delta6_thre_mad16_ratio_intra : 3; + RK_U32 delta7_thre_mad16_ratio_intra : 3; + RK_U32 delta0_thre_rough_bgrad32_intra : 3; + RK_U32 delta1_thre_rough_bgrad32_intra : 4; + RK_U32 delta2_thre_rough_bgrad32_intra_low4 : 4; + } cudecis_thd5; + + /* 0x00002118 reg2118 */ + struct { + RK_U32 delta2_thre_rough_bgrad32_intra_high2 : 2; + RK_U32 delta3_thre_rough_bgrad32_intra : 10; + RK_U32 delta4_thre_rough_bgrad32_intra : 10; + RK_U32 delta5_thre_rough_bgrad32_intra_low10 : 10; + } cudecis_thd6; + + /* 0x0000211c reg2119 */ + struct { + RK_U32 delta5_thre_rough_bgrad32_intra_high1 : 1; + RK_U32 delta6_thre_rough_bgrad32_intra : 12; + RK_U32 delta7_thre_rough_bgrad32_intra : 13; + RK_U32 delta0_thre_bgrad16_ratio_intra : 4; + RK_U32 delta1_thre_bgrad16_ratio_intra_low2 : 2; + } cudecis_thd7; + + /* 0x00002120 reg2120 */ + struct { + RK_U32 delta1_thre_bgrad16_ratio_intra_high2 : 2; + RK_U32 delta2_thre_bgrad16_ratio_intra : 4; + RK_U32 delta3_thre_bgrad16_ratio_intra : 4; + RK_U32 delta4_thre_bgrad16_ratio_intra : 4; + RK_U32 delta5_thre_bgrad16_ratio_intra : 4; + RK_U32 delta6_thre_bgrad16_ratio_intra : 4; + RK_U32 delta7_thre_bgrad16_ratio_intra : 4; + RK_U32 delta0_thre_fme_ratio_inter : 3; + RK_U32 delta1_thre_fme_ratio_inter : 3; + } cudecis_thdt8; + + /* 0x00002124 reg2121 */ + struct { + RK_U32 delta2_thre_fme_ratio_inter : 3; + RK_U32 delta3_thre_fme_ratio_inter : 3; + RK_U32 delta4_thre_fme_ratio_inter : 3; + RK_U32 delta5_thre_fme_ratio_inter : 3; + RK_U32 delta6_thre_fme_ratio_inter : 3; + RK_U32 delta7_thre_fme_ratio_inter : 3; + RK_U32 base_thre_fme32_inter : 3; + RK_U32 delta0_thre_fme32_inter : 3; + RK_U32 delta1_thre_fme32_inter : 4; + RK_U32 delta2_thre_fme32_inter : 4; + } cudecis_thd9; + + /* 0x00002128 reg2122 */ + struct { + RK_U32 delta3_thre_fme32_inter : 5; + RK_U32 delta4_thre_fme32_inter : 6; + RK_U32 delta5_thre_fme32_inter : 7; + RK_U32 delta6_thre_fme32_inter : 8; + RK_U32 thre_cme32_inter : 6; + } cudecis_thd10; + + /* 0x0000212c reg2123 */ + struct { + RK_U32 delta0_thre_mad_fme_ratio_inter : 4; + RK_U32 delta1_thre_mad_fme_ratio_inter : 4; + RK_U32 delta2_thre_mad_fme_ratio_inter : 4; + RK_U32 delta3_thre_mad_fme_ratio_inter : 4; + RK_U32 delta4_thre_mad_fme_ratio_inter : 4; + RK_U32 delta5_thre_mad_fme_ratio_inter : 4; + RK_U32 delta6_thre_mad_fme_ratio_inter : 4; + RK_U32 delta7_thre_mad_fme_ratio_inter : 4; + } cudecis_thd11; +} H265eVepu510Sqi; typedef struct H265eV510RegSet_t { - H265eVepu510ControlCfg reg_ctl; + Vepu510ControlCfg reg_ctl; H265eVepu510Frame reg_frm; - H265eVepu510RcRoi reg_rc_roi; + Vepu510RcRoi reg_rc_roi; H265eVepu510Param reg_param; - Vepu510Sqi reg_sqi; - Vepu510Dbg reg_dbg; - H265eVepu510SubjOpt reg_subj_opt; + H265eVepu510Sqi reg_sqi; + Vepu510Dbg reg_dbg; } H265eV510RegSet; typedef struct H265eV510StatusElem_t {