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[hal_h264d][hal_h265d]: Fix ccu_mode issue

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Change method to differ bettween refers and decout

method:
The poc_height mark 3 for refers which the base addr is the same as decout.
if the base addr and decout is the same, hardware will hung work.

Change-Id: I7ab71bb0f435615aea6b722f28c7b0dd57fb9674
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
This commit is contained in:
Ding Wei 2022-03-11 16:25:16 +08:00 • committed by Herman Chen
parent 0b0d34c2db
commit 4dcc3f6134
4 changed files with 124 additions and 84 deletions
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37
mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
View file

@ -535,6 +535,7 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal
HalBuf *mv_buf = NULL;
// memset(regs, 0, sizeof(Vdpu34xH264dRegSet));
memset(&regs->h264d_highpoc, 0, sizeof(regs->h264d_highpoc));
common->reg016_str_len = p_hal->strm_len;
common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag;
common->reg012.colmv_compress_en = (pp->frame_mbs_only_flag) ? 1 : 0;
@ -580,8 +581,10 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal
mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, pp->CurrPic.Index7Bits);
regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
regs->common_addr.reg132_error_ref_base = fd;
regs->h264d_highpoc.reg204.cur_bot_field_flag = pp->CurrPic.AssociatedFlag;
regs->h264d_highpoc.reg204.cur_decout_flag = 1;
if (pp->field_pic_flag)
regs->h264d_highpoc.reg204.cur_poc_highbit = 1 << pp->CurrPic.AssociatedFlag; // top:1 bot:2
else
regs->h264d_highpoc.reg204.cur_poc_highbit = 0; // frame
}
//!< set reference
{
@ -593,16 +596,16 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal
MppFrame mframe = NULL;
for (i = 0; i < 15; i++) {
regs->h264d_param.reg67_98_ref_poc[i] = (i & 1)
? pp->FieldOrderCntList[i / 2][1] : pp->FieldOrderCntList[i / 2][0];
regs->h264d_param.reg67_98_ref_poc[15 + i] = (i & 1)
? pp->FieldOrderCntList[(i + 15) / 2][0] : pp->FieldOrderCntList[(i + 15) / 2][1];
SET_REF_INFO(regs->h264d_param, i, field, (pp->RefPicFiledFlags >> i) & 0x01);
SET_REF_INFO(regs->h264d_param, i, topfield_used, (pp->UsedForReferenceFlags >> (2 * i + 0)) & 0x01);
SET_REF_INFO(regs->h264d_param, i, botfield_used, (pp->UsedForReferenceFlags >> (2 * i + 1)) & 0x01);
RK_U32 field_flag = (pp->RefPicFiledFlags >> i) & 0x01;
RK_U32 top_used = (pp->UsedForReferenceFlags >> (2 * i + 0)) & 0x01;
RK_U32 bot_used = (pp->UsedForReferenceFlags >> (2 * i + 1)) & 0x01;
regs->h264d_param.reg67_98_ref_poc[2 * i] = pp->FieldOrderCntList[i][0];
regs->h264d_param.reg67_98_ref_poc[2 * i + 1] = pp->FieldOrderCntList[i][1];
SET_REF_INFO(regs->h264d_param, i, field, field_flag);
SET_REF_INFO(regs->h264d_param, i, topfield_used, top_used);
SET_REF_INFO(regs->h264d_param, i, botfield_used, bot_used);
SET_REF_INFO(regs->h264d_param, i, colmv_use_flag, (pp->RefPicColmvUsedFlags >> i) & 0x01);
SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i, bot_field_flag, 0);
SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i + 1, bot_field_flag, (pp->RefPicFiledFlags >> i) & 0x01);
if (pp->RefFrameList[i].bPicEntry != 0xff) {
ref_index = pp->RefFrameList[i].Index7Bits;
@ -610,6 +613,11 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal
} else {
ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
}
/* mark 3 to differ from current frame */
if (ref_index == pp->CurrPic.Index7Bits) {
SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i, poc_highbit, 3);
SET_POC_HIGNBIT_INFO(regs->h264d_highpoc, 2 * i + 1, poc_highbit, 3);
}
mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_FRAME_PTR, &mframe);
@ -633,14 +641,17 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal
regs->h264d_param.reg102.ref15_topfield_used = (pp->UsedForReferenceFlags >> 30) & 0x01;
regs->h264d_param.reg102.ref15_botfield_used = (pp->UsedForReferenceFlags >> 31) & 0x01;
regs->h264d_param.reg102.ref15_colmv_use_flag = (pp->RefPicColmvUsedFlags >> 15) & 0x01;
regs->h264d_highpoc.reg203.ref30_bot_field_flag = 0;
regs->h264d_highpoc.reg203.ref31_bot_field_flag = (pp->RefPicFiledFlags >> 15) & 0x01;
if (pp->RefFrameList[15].bPicEntry != 0xff) {
ref_index = pp->RefFrameList[15].Index7Bits;
} else {
ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
}
/* mark 3 to differ from current frame */
if (ref_index == pp->CurrPic.Index7Bits) {
regs->h264d_highpoc.reg203.ref30_poc_highbit = 3;
regs->h264d_highpoc.reg203.ref31_poc_highbit = 3;
}
mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
RK_S32 fd = mpp_buffer_get_fd(mbuffer);
regs->h264d_addr.ref_base[15] = fd;

26
mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
View file

@ -807,6 +807,28 @@ static void hal_h265d_rcb_info_update(void *hal, void *dxva,
}
}
#define SET_POC_HIGNBIT_INFO(regs, index, field, value)\
do{ \
switch(index){\
case 0: regs.reg200.ref0_##field = value; break;\
case 1: regs.reg200.ref1_##field = value; break;\
case 2: regs.reg200.ref2_##field = value; break;\
case 3: regs.reg200.ref3_##field = value; break;\
case 4: regs.reg200.ref4_##field = value; break;\
case 5: regs.reg200.ref5_##field = value; break;\
case 6: regs.reg200.ref6_##field = value; break;\
case 7: regs.reg200.ref7_##field = value; break;\
case 8: regs.reg201.ref8_##field = value; break;\
case 9: regs.reg201.ref9_##field = value; break;\
case 10: regs.reg201.ref10_##field = value; break;\
case 11: regs.reg201.ref11_##field = value; break;\
case 12: regs.reg201.ref12_##field = value; break;\
case 13: regs.reg201.ref13_##field = value; break;\
case 14: regs.reg201.ref14_##field = value; break;\
case 15: regs.reg201.ref15_##field = value; break;\
default: break;}\
}while(0)
static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
{
RK_S32 i = 0;
@ -957,7 +979,6 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
}
fd = mpp_buffer_get_fd(framebuf);
hw_regs->common_addr.reg130_decout_base = fd;
hw_regs->highpoc.reg204.cur_decout_flag = 1;
mv_buf = hal_bufs_get_buf(reg_cxt->cmv_bufs, dxva_cxt->pp.CurrPic.Index7Bits);
hw_regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
@ -1066,6 +1087,9 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
mv_buf = hal_bufs_get_buf(reg_cxt->cmv_bufs, reg_cxt->error_index);
hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base;
hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
/* mark 3 to differ from current frame */
if (reg_cxt->error_index == dxva_cxt->pp.CurrPic.Index7Bits)
SET_POC_HIGNBIT_INFO(hw_regs->highpoc, i, poc_highbit, 3);
}
}

100
mpp/hal/rkdec/inc/vdpu34x_h264d.h
View file

@ -191,81 +191,47 @@ typedef struct Vdpu34xRegH264dAddr_t {
typedef struct Vdpu34xH264dHighPoc_t {
/* SWREG200 */
struct SWREG200_REF0_7_POC_HIGHBIT {
RK_U32 ref0_bot_field_flag : 1;
RK_U32 ref0_poc_highbit : 3;
RK_U32 ref1_bot_field_flag : 1;
RK_U32 ref1_poc_highbit : 3;
RK_U32 ref2_bot_field_flag : 1;
RK_U32 ref2_poc_highbit : 3;
RK_U32 ref3_bot_field_flag : 1;
RK_U32 ref3_poc_highbit : 3;
RK_U32 ref4_bot_field_flag : 1;
RK_U32 ref4_poc_highbit : 3;
RK_U32 ref5_bot_field_flag : 1;
RK_U32 ref5_poc_highbit : 3;
RK_U32 ref6_bot_field_flag : 1;
RK_U32 ref6_poc_highbit : 3;
RK_U32 ref7_bot_field_flag : 1;
RK_U32 ref7_poc_highbit : 3;
RK_U32 ref0_poc_highbit : 4;
RK_U32 ref1_poc_highbit : 4;
RK_U32 ref2_poc_highbit : 4;
RK_U32 ref3_poc_highbit : 4;
RK_U32 ref4_poc_highbit : 4;
RK_U32 ref5_poc_highbit : 4;
RK_U32 ref6_poc_highbit : 4;
RK_U32 ref7_poc_highbit : 4;
} reg200;
struct SWREG201_REF8_15_POC_HIGHBIT {
RK_U32 ref8_bot_field_flag : 1;
RK_U32 ref8_poc_highbit : 3;
RK_U32 ref9_bot_field_flag : 1;
RK_U32 ref9_poc_highbit : 3;
RK_U32 ref10_bot_field_flag : 1;
RK_U32 ref10_poc_highbit : 3;
RK_U32 ref11_bot_field_flag : 1;
RK_U32 ref11_poc_highbit : 3;
RK_U32 ref12_bot_field_flag : 1;
RK_U32 ref12_poc_highbit : 3;
RK_U32 ref13_bot_field_flag : 1;
RK_U32 ref13_poc_highbit : 3;
RK_U32 ref14_bot_field_flag : 1;
RK_U32 ref14_poc_highbit : 3;
RK_U32 ref15_bot_field_flag : 1;
RK_U32 ref15_poc_highbit : 3;
RK_U32 ref8_poc_highbit : 4;
RK_U32 ref9_poc_highbit : 4;
RK_U32 ref10_poc_highbit : 4;
RK_U32 ref11_poc_highbit : 4;
RK_U32 ref12_poc_highbit : 4;
RK_U32 ref13_poc_highbit : 4;
RK_U32 ref14_poc_highbit : 4;
RK_U32 ref15_poc_highbit : 4;
} reg201;
struct SWREG200_REF16_23_POC_HIGHBIT {
RK_U32 ref16_bot_field_flag : 1;
RK_U32 ref16_poc_highbit : 3;
RK_U32 ref17_bot_field_flag : 1;
RK_U32 ref17_poc_highbit : 3;
RK_U32 ref18_bot_field_flag : 1;
RK_U32 ref18_poc_highbit : 3;
RK_U32 ref19_bot_field_flag : 1;
RK_U32 ref19_poc_highbit : 3;
RK_U32 ref20_bot_field_flag : 1;
RK_U32 ref20_poc_highbit : 3;
RK_U32 ref21_bot_field_flag : 1;
RK_U32 ref21_poc_highbit : 3;
RK_U32 ref22_bot_field_flag : 1;
RK_U32 ref22_poc_highbit : 3;
RK_U32 ref23_bot_field_flag : 1;
RK_U32 ref23_poc_highbit : 3;
RK_U32 ref16_poc_highbit : 4;
RK_U32 ref17_poc_highbit : 4;
RK_U32 ref18_poc_highbit : 4;
RK_U32 ref19_poc_highbit : 4;
RK_U32 ref20_poc_highbit : 4;
RK_U32 ref21_poc_highbit : 4;
RK_U32 ref22_poc_highbit : 4;
RK_U32 ref23_poc_highbit : 4;
} reg202;
struct SWREG200_REF24_31_POC_HIGHBIT {
RK_U32 ref24_bot_field_flag : 1;
RK_U32 ref24_poc_highbit : 3;
RK_U32 ref25_bot_field_flag : 1;
RK_U32 ref25_poc_highbit : 3;
RK_U32 ref26_bot_field_flag : 1;
RK_U32 ref26_poc_highbit : 3;
RK_U32 ref27_bot_field_flag : 1;
RK_U32 ref27_poc_highbit : 3;
RK_U32 ref28_bot_field_flag : 1;
RK_U32 ref28_poc_highbit : 3;
RK_U32 ref29_bot_field_flag : 1;
RK_U32 ref29_poc_highbit : 3;
RK_U32 ref30_bot_field_flag : 1;
RK_U32 ref30_poc_highbit : 3;
RK_U32 ref31_bot_field_flag : 1;
RK_U32 ref31_poc_highbit : 3;
RK_U32 ref24_poc_highbit : 4;
RK_U32 ref25_poc_highbit : 4;
RK_U32 ref26_poc_highbit : 4;
RK_U32 ref27_poc_highbit : 4;
RK_U32 ref28_poc_highbit : 4;
RK_U32 ref29_poc_highbit : 4;
RK_U32 ref30_poc_highbit : 4;
RK_U32 ref31_poc_highbit : 4;
} reg203;
struct SWREG200_CUR_POC_HIGHBIT {
RK_U32 cur_decout_flag : 1;
RK_U32 cur_bot_field_flag : 1;
RK_U32 cur_poc_highbit : 2;
RK_U32 cur_poc_highbit : 4;
RK_U32 reserver : 28;
} reg204;
} Vdpu34xH264dHighPoc_t;

45
mpp/hal/rkdec/inc/vdpu34x_h265d.h
View file

@ -128,10 +128,49 @@ typedef struct Vdpu34xRegH265dAddr_t {
} Vdpu34xRegH265dAddr;
typedef struct Vdpu34xH265dHighPoc_t {
RK_U32 reg200_203[4];
/* SWREG200 */
struct SWREG200_REF0_7_POC_HIGHBIT {
RK_U32 ref0_poc_highbit : 4;
RK_U32 ref1_poc_highbit : 4;
RK_U32 ref2_poc_highbit : 4;
RK_U32 ref3_poc_highbit : 4;
RK_U32 ref4_poc_highbit : 4;
RK_U32 ref5_poc_highbit : 4;
RK_U32 ref6_poc_highbit : 4;
RK_U32 ref7_poc_highbit : 4;
} reg200;
struct SWREG201_REF8_15_POC_HIGHBIT {
RK_U32 ref8_poc_highbit : 4;
RK_U32 ref9_poc_highbit : 4;
RK_U32 ref10_poc_highbit : 4;
RK_U32 ref11_poc_highbit : 4;
RK_U32 ref12_poc_highbit : 4;
RK_U32 ref13_poc_highbit : 4;
RK_U32 ref14_poc_highbit : 4;
RK_U32 ref15_poc_highbit : 4;
} reg201;
struct SWREG200_REF16_23_POC_HIGHBIT {
RK_U32 ref16_poc_highbit : 4;
RK_U32 ref17_poc_highbit : 4;
RK_U32 ref18_poc_highbit : 4;
RK_U32 ref19_poc_highbit : 4;
RK_U32 ref20_poc_highbit : 4;
RK_U32 ref21_poc_highbit : 4;
RK_U32 ref22_poc_highbit : 4;
RK_U32 ref23_poc_highbit : 4;
} reg202;
struct SWREG200_REF24_31_POC_HIGHBIT {
RK_U32 ref24_poc_highbit : 4;
RK_U32 ref25_poc_highbit : 4;
RK_U32 ref26_poc_highbit : 4;
RK_U32 ref27_poc_highbit : 4;
RK_U32 ref28_poc_highbit : 4;
RK_U32 ref29_poc_highbit : 4;
RK_U32 ref30_poc_highbit : 4;
RK_U32 ref31_poc_highbit : 4;
} reg203;
struct SWREG200_CUR_POC_HIGHBIT {
RK_U32 cur_decout_flag : 1;
RK_U32 cur_poc_highbit : 3;
RK_U32 cur_poc_highbit : 4;
RK_U32 reserver : 28;
} reg204;
} Vdpu34xH2645HighPoc_t;