This is the 6.1.115 stable release
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This commit is contained in:
Tao Huang
commit
96900fe2fe
2200 changed files with 33639 additions and 21718 deletions
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@ -54,11 +54,13 @@ obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
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layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o
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obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o
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skx_edac-y := skx_common.o skx_base.o
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obj-$(CONFIG_EDAC_SKX) += skx_edac.o
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skx_edac_common-y := skx_common.o
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i10nm_edac-y := skx_common.o i10nm_base.o
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obj-$(CONFIG_EDAC_I10NM) += i10nm_edac.o
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skx_edac-y := skx_base.o
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obj-$(CONFIG_EDAC_SKX) += skx_edac.o skx_edac_common.o
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i10nm_edac-y := i10nm_base.o
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obj-$(CONFIG_EDAC_I10NM) += i10nm_edac.o skx_edac_common.o
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obj-$(CONFIG_EDAC_CELL) += cell_edac.o
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obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
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@ -245,7 +245,7 @@ static u64 ehl_err_addr_to_imc_addr(u64 eaddr, int mc)
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if (igen6_tom <= _4GB)
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return eaddr + igen6_tolud - _4GB;
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if (eaddr < _4GB)
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if (eaddr >= igen6_tom)
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return eaddr + igen6_tolud - igen6_tom;
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return eaddr;
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@ -48,7 +48,7 @@ static u64 skx_tolm, skx_tohm;
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static LIST_HEAD(dev_edac_list);
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static bool skx_mem_cfg_2lm;
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int __init skx_adxl_get(void)
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int skx_adxl_get(void)
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{
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const char * const *names;
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int i, j;
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@ -110,12 +110,14 @@ err:
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return -ENODEV;
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}
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EXPORT_SYMBOL_GPL(skx_adxl_get);
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void __exit skx_adxl_put(void)
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void skx_adxl_put(void)
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{
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kfree(adxl_values);
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kfree(adxl_msg);
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}
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EXPORT_SYMBOL_GPL(skx_adxl_put);
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static bool skx_adxl_decode(struct decoded_addr *res, bool error_in_1st_level_mem)
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{
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@ -187,12 +189,14 @@ void skx_set_mem_cfg(bool mem_cfg_2lm)
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{
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skx_mem_cfg_2lm = mem_cfg_2lm;
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}
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EXPORT_SYMBOL_GPL(skx_set_mem_cfg);
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void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
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{
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driver_decode = decode;
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skx_show_retry_rd_err_log = show_retry_log;
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}
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EXPORT_SYMBOL_GPL(skx_set_decode);
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int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
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{
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@ -206,6 +210,7 @@ int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
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*id = GET_BITFIELD(reg, 12, 14);
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return 0;
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}
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EXPORT_SYMBOL_GPL(skx_get_src_id);
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int skx_get_node_id(struct skx_dev *d, u8 *id)
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{
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@ -219,6 +224,7 @@ int skx_get_node_id(struct skx_dev *d, u8 *id)
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*id = GET_BITFIELD(reg, 0, 2);
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return 0;
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}
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EXPORT_SYMBOL_GPL(skx_get_node_id);
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static int get_width(u32 mtr)
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{
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@ -284,6 +290,7 @@ int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list)
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*list = &dev_edac_list;
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return ndev;
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}
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EXPORT_SYMBOL_GPL(skx_get_all_bus_mappings);
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int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
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{
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@ -323,6 +330,7 @@ fail:
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pci_dev_put(pdev);
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return -ENODEV;
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}
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EXPORT_SYMBOL_GPL(skx_get_hi_lo);
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static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
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int minval, int maxval, const char *name)
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@ -394,6 +402,7 @@ int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
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return 1;
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}
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EXPORT_SYMBOL_GPL(skx_get_dimm_info);
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int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
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int chan, int dimmno, const char *mod_str)
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@ -442,6 +451,7 @@ unknown_size:
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return (size == 0 || size == ~0ull) ? 0 : 1;
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}
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EXPORT_SYMBOL_GPL(skx_get_nvdimm_info);
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int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
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const char *ctl_name, const char *mod_str,
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@ -512,6 +522,7 @@ fail0:
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imc->mci = NULL;
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return rc;
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}
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EXPORT_SYMBOL_GPL(skx_register_mci);
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static void skx_unregister_mci(struct skx_imc *imc)
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{
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@ -694,6 +705,7 @@ int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
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mce->kflags |= MCE_HANDLED_EDAC;
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return NOTIFY_DONE;
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}
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EXPORT_SYMBOL_GPL(skx_mce_check_error);
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void skx_remove(void)
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{
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@ -731,3 +743,8 @@ void skx_remove(void)
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kfree(d);
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}
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}
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EXPORT_SYMBOL_GPL(skx_remove);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Tony Luck");
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MODULE_DESCRIPTION("MC Driver for Intel server processors");
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@ -178,8 +178,8 @@ typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci,
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typedef bool (*skx_decode_f)(struct decoded_addr *res);
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typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err);
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int __init skx_adxl_get(void);
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void __exit skx_adxl_put(void);
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int skx_adxl_get(void);
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void skx_adxl_put(void);
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void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log);
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void skx_set_mem_cfg(bool mem_cfg_2lm);
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@ -9,6 +9,8 @@
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#include <linux/edac.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/sizes.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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@ -300,6 +302,7 @@ struct synps_ecc_status {
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/**
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* struct synps_edac_priv - DDR memory controller private instance data.
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* @baseaddr: Base address of the DDR controller.
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* @reglock: Concurrent CSRs access lock.
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* @message: Buffer for framing the event specific info.
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* @stat: ECC status information.
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* @p_data: Platform data.
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@ -314,6 +317,7 @@ struct synps_ecc_status {
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*/
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struct synps_edac_priv {
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void __iomem *baseaddr;
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spinlock_t reglock;
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char message[SYNPS_EDAC_MSG_SIZE];
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struct synps_ecc_status stat;
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const struct synps_platform_data *p_data;
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@ -335,6 +339,7 @@ struct synps_edac_priv {
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* @get_mtype: Get mtype.
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* @get_dtype: Get dtype.
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* @get_ecc_state: Get ECC state.
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* @get_mem_info: Get EDAC memory info
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* @quirks: To differentiate IPs.
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*/
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struct synps_platform_data {
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@ -342,6 +347,9 @@ struct synps_platform_data {
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enum mem_type (*get_mtype)(const void __iomem *base);
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enum dev_type (*get_dtype)(const void __iomem *base);
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bool (*get_ecc_state)(void __iomem *base);
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#ifdef CONFIG_EDAC_DEBUG
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u64 (*get_mem_info)(struct synps_edac_priv *priv);
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#endif
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int quirks;
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};
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@ -400,6 +408,25 @@ out:
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return 0;
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}
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#ifdef CONFIG_EDAC_DEBUG
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/**
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* zynqmp_get_mem_info - Get the current memory info.
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* @priv: DDR memory controller private instance data.
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*
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* Return: host interface address.
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*/
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static u64 zynqmp_get_mem_info(struct synps_edac_priv *priv)
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{
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u64 hif_addr = 0, linear_addr;
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linear_addr = priv->poison_addr;
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if (linear_addr >= SZ_32G)
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linear_addr = linear_addr - SZ_32G + SZ_2G;
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hif_addr = linear_addr >> 3;
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return hif_addr;
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}
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#endif
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/**
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* zynqmp_get_error_info - Get the current ECC error info.
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* @priv: DDR memory controller private instance data.
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@ -409,7 +436,8 @@ out:
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static int zynqmp_get_error_info(struct synps_edac_priv *priv)
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{
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struct synps_ecc_status *p;
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u32 regval, clearval = 0;
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u32 regval, clearval;
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unsigned long flags;
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void __iomem *base;
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base = priv->baseaddr;
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@ -453,10 +481,14 @@ ue_err:
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p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
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p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
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out:
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clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT;
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clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT;
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spin_lock_irqsave(&priv->reglock, flags);
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clearval = readl(base + ECC_CLR_OFST) |
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ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT |
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ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT;
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writel(clearval, base + ECC_CLR_OFST);
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writel(0x0, base + ECC_CLR_OFST);
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spin_unlock_irqrestore(&priv->reglock, flags);
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return 0;
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}
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@ -516,24 +548,41 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
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static void enable_intr(struct synps_edac_priv *priv)
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{
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unsigned long flags;
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/* Enable UE/CE Interrupts */
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if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
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writel(DDR_UE_MASK | DDR_CE_MASK,
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priv->baseaddr + ECC_CLR_OFST);
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else
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if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
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writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
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priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
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return;
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}
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spin_lock_irqsave(&priv->reglock, flags);
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writel(DDR_UE_MASK | DDR_CE_MASK,
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priv->baseaddr + ECC_CLR_OFST);
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spin_unlock_irqrestore(&priv->reglock, flags);
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}
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static void disable_intr(struct synps_edac_priv *priv)
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{
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unsigned long flags;
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/* Disable UE/CE Interrupts */
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if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
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writel(0x0, priv->baseaddr + ECC_CLR_OFST);
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else
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if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
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writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
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priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
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return;
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}
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spin_lock_irqsave(&priv->reglock, flags);
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writel(0, priv->baseaddr + ECC_CLR_OFST);
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spin_unlock_irqrestore(&priv->reglock, flags);
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}
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/**
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@ -577,8 +626,6 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
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/* v3.0 of the controller does not have this register */
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if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
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writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
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else
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enable_intr(priv);
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return IRQ_HANDLED;
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}
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@ -900,6 +947,9 @@ static const struct synps_platform_data zynqmp_edac_def = {
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.get_mtype = zynqmp_get_mtype,
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.get_dtype = zynqmp_get_dtype,
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.get_ecc_state = zynqmp_get_ecc_state,
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#ifdef CONFIG_EDAC_DEBUG
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.get_mem_info = zynqmp_get_mem_info,
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#endif
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.quirks = (DDR_ECC_INTR_SUPPORT
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#ifdef CONFIG_EDAC_DEBUG
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| DDR_ECC_DATA_POISON_SUPPORT
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@ -953,10 +1003,16 @@ MODULE_DEVICE_TABLE(of, synps_edac_match);
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static void ddr_poison_setup(struct synps_edac_priv *priv)
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{
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int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval;
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const struct synps_platform_data *p_data;
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int index;
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ulong hif_addr = 0;
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hif_addr = priv->poison_addr >> 3;
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p_data = priv->p_data;
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if (p_data->get_mem_info)
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hif_addr = p_data->get_mem_info(priv);
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else
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hif_addr = priv->poison_addr >> 3;
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for (index = 0; index < DDR_MAX_ROW_SHIFT; index++) {
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if (priv->row_shift[index])
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|
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@ -1360,6 +1416,7 @@ static int mc_probe(struct platform_device *pdev)
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priv = mci->pvt_info;
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priv->baseaddr = baseaddr;
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priv->p_data = p_data;
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spin_lock_init(&priv->reglock);
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||||
|
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mc_init(mci, pdev);
|
||||
|
||||
|
|
|
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Add a link
Reference in a new issue