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phy: rockchip: inno-usb2: Support usb wakeup system for rk3576

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1. Select the usb2 phy interrupt logic clock from OSC clock
   to support interrupt detection if VD_LOGIC is powerdown.

2. Set the linestate filter time control register depends
   on the OSC 24MHz clock during suspend.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ib265747013b0a08dc0599df25e40dce306ccb289
This commit is contained in:
William Wu 2024-11-25 17:25:59 +08:00 • committed by Tao Huang
parent 6b4f98d938
commit 95a3c34298
1 changed files with 19 additions and 4 deletions
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23
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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@ -215,11 +215,13 @@ struct rockchip_usb2phy_port_cfg {
* @clkout_ctl_phy: keep on/turn off output clk of phy via phy inner
* debug register.
* @ls_filter_con: set linestate filter time.
* @port_cfgs: usb-phy port configurations.
* @ls_filter_con: set linestate filter time.
* @refclk_fsel: reference clock frequency select,
* true - select 24 MHz
* false - select 26 MHz
* @detclk_sel: usb phy grf reference clock select,
* true - select OSC clock
* false - select pclk
* @port_cfgs: usb-phy port configurations.
* @chg_det: charger detection registers.
*/
struct rockchip_usb2phy_cfg {
@ -233,6 +235,7 @@ struct rockchip_usb2phy_cfg {
struct usb2phy_reg clkout_ctl_phy;
struct usb2phy_reg ls_filter_con;
struct usb2phy_reg refclk_fsel;
struct usb2phy_reg detclk_sel;
const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
const struct rockchip_chg_det_reg chg_det;
};
@ -3327,6 +3330,13 @@ static int rockchip_usb2phy_pm_suspend(struct device *dev)
if (wakeup_enable && rphy->irq > 0)
enable_irq_wake(rphy->irq);
/*
* Select the usb2 phy interrupt logic clock from OSC clock
* to support interrupt detection if VD_LOGIC is powerdown.
*/
if (phy_cfg->detclk_sel.enable)
property_enable(rphy->grf, &phy_cfg->detclk_sel, true);
return ret;
}
@ -3361,6 +3371,9 @@ static int rockchip_usb2phy_pm_resume(struct device *dev)
dev_err(rphy->dev, "failed to set ls filter %d\n", ret);
}
if (phy_cfg->detclk_sel.enable)
property_enable(rphy->grf, &phy_cfg->detclk_sel, false);
for (index = 0; index < phy_cfg->num_ports; index++) {
rport = &rphy->ports[index];
if (!rport->phy)
@ -4275,8 +4288,9 @@ static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
.num_ports = 1,
.phy_tuning = rk3576_usb2phy_tuning,
.clkout_ctl = { 0x0008, 0, 0, 1, 0 },
.ls_filter_con = { 0x0020, 19, 0, 0x30100, 0x00020 },
.ls_filter_con = { 0x0020, 19, 0, 0x30100, 0x06020 },
.refclk_fsel = { 0x0004, 2, 0, 0x6, 0x2 },
.detclk_sel = { 0x00d0, 0, 0, 0, 1 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
@ -4330,8 +4344,9 @@ static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
.num_ports = 1,
.phy_tuning = rk3576_usb2phy_tuning,
.clkout_ctl = { 0x2008, 0, 0, 1, 0 },
.ls_filter_con = { 0x2020, 19, 0, 0x30100, 0x00020 },
.ls_filter_con = { 0x2020, 19, 0, 0x30100, 0x06020 },
.refclk_fsel = { 0x2004, 2, 0, 0x6, 0x2 },
.detclk_sel = { 0x20d0, 0, 0, 0, 1 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x2000, 8, 0, 0, 0x1d1 },