DuDu371/linux-rockchip
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

arm64: dts: rockchip: add 10fhd overlay for rock-5t

Browse source 
Signed-off-by: Mitchell Ma <machuang@radxa.com>
This commit is contained in:
Mitchell Ma 2025-06-18 17:28:59 +08:00 • committed by Igor
parent 5271a2ffc8
commit 7ee713c95b
2 changed files with 262 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
arch/arm64/boot/dts/rockchip/overlay/Makefile
View file

@ -55,6 +55,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rock-5b-rpi-camera-v2.dtbo \
rock-5b-radxa-camera-4k.dtbo \
rock-5b-sata.dtbo \
rock-5t-radxa-display-10fhd.dtbo \
rock-5-itx-radxa-camera-4k-on-cam0.dtbo \
rock-5-itx-radxa-camera-4k-on-cam1.dtbo \
rock-5-itx-radxa-display-8hd-on-lcd0.dtbo \

261
arch/arm64/boot/dts/rockchip/overlay/rock-5t-radxa-display-10fhd.dts Normal file
View file

@ -0,0 +1,261 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/pwm/pwm.h>
/ {
metadata {
title ="Enable Radxa Display 10FHD";
compatible = "radxa,rock-5t";
category = "display";
exclusive = "dsi1", "GPIO1_A2";
description = "Enable Radxa Display 10FHD.";
};
};
/ {
fragment@0 {
target-path = "/";
__overlay__ {
vcc_lcd_mipi1: vcc-lcd-mipi1 {
status = "okay";
compatible = "regulator-fixed";
regulator-name = "vcc_lcd_mipi1";
gpio = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
dsi1_backlight: dsi1-backlight {
status = "okay";
compatible = "pwm-backlight";
pwms = <&pwm2 0 25000 PWM_POLARITY_INVERTED>;
brightness-levels = <
0 20 20 21 21 22 22 23
23 24 24 25 25 26 26 27
27 28 28 29 29 30 30 31
31 32 32 33 33 34 34 35
35 36 36 37 37 38 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255
>;
default-brightness-level = <200>;
enable-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dsi1_backlight_en>;
};
};
};
fragment@1 {
target = <&pwm2>;
__overlay__ {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm2m2_pins>;
};
};
fragment@2 {
target = <&dsi1>;
__overlay__ {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&dsi1_backlight>;
vdd-supply = <&vcc_lcd_mipi1>;
vccio-supply = <&vcc_1v8_s0>;
reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dsi1_lcd_rst_gpio>;
prepare-delay-ms = <120>;
reset-delay-ms = <120>;
init-delay-ms = <120>;
enable-delay-ms = <100>;
disable-delay-ms = <120>;
unprepare-delay-ms = <120>;
width-mm = <62>;
height-mm = <110>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
05 78 01 11
05 00 01 29
];
panel-exit-sequence = [
05 00 01 28
05 00 01 10
];
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <160000000>;
hactive = <1200>;
vactive = <1920>;
vback-porch = <25>;
vfront-porch = <35>;
hback-porch = <60>;
hfront-porch = <80>;
hsync-len = <4>;
vsync-len = <4>;
vsync-active = <0>;
hsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi1: endpoint {
remote-endpoint = <&dsi1_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi1_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi1>;
};
};
};
};
};
fragment@3 {
target = <&mipi_dcphy1>;
__overlay__ {
status = "okay";
};
};
fragment@4 {
target = <&route_dsi1>;
__overlay__ {
status = "okay";
connect = <&vp3_out_dsi1>;
};
};
fragment@5 {
target = <&dsi1_in_vp2>;
__overlay__ {
status = "disabled";
};
};
fragment@6 {
target = <&dsi1_in_vp3>;
__overlay__ {
status = "okay";
};
};
fragment@7 {
target = <&i2c6>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c6m0_xfer>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
gt9xx: gt9xx@14 {
compatible = "goodix,gt9271";
reg = <0x14>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_HIGH>;
irq-gpios = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <1200>;
touchscreen-size-y = <1920>;
status = "okay";
};
};
};
fragment@8 {
target = <&pinctrl>;
__overlay__ {
dsi1-lcd {
dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio {
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
};
dsi1_backlight_en: dsi1-backlight-en {
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
};
};