From 551c31c8214234a4501ab92364335930cda848dc Mon Sep 17 00:00:00 2001
From: mahdichi <mahdichi@gmail.com>
Date: Mon, 11 Nov 2024 20:26:54 +0330
Subject: [PATCH] dts: fxblox remove sd pwr gpio and correct bt wake gpio

---
 .../arm64/boot/dts/rockchip/rk3588-fxblox-rk1.dts | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-fxblox-rk1.dts b/arch/arm64/boot/dts/rockchip/rk3588-fxblox-rk1.dts
index 7ede0d557fae..7b09635a0853 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-fxblox-rk1.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-fxblox-rk1.dts
@@ -498,7 +498,7 @@
 };
 
 &sdmmc {
-	max-frequency = <150000000>;
+	max-frequency = <200000000>;
 	no-sdio;
 	no-mmc;
 	bus-width = <4>;
@@ -506,8 +506,10 @@
 	cap-sd-highspeed;
 	disable-wp;
 	sd-uhs-sdr104;
-	//vmmc-supply = <&vcc_3v3_sd_s3>;
+	vmmc-supply = <&vcc_3v3_s3>;
 	vqmmc-supply = <&vccio_sd_s0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
 	status = "okay";
 };
 
@@ -1129,7 +1131,7 @@
 // pcie3x4
 &pcie3x4 {
 	reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
-	//vpcie3v3-supply = <&vcc3v3_pcie30>;
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
 	status = "okay";
 };
 
@@ -1292,7 +1294,7 @@
 		};
 
 		bt_host_wake_l: bt-host-wake-l {
-			rockchip,pins = <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+			rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
 		bt_wake_l: bt-wake-l {
@@ -1300,11 +1302,6 @@
 		};
 	};
 
-	sdmmc {
-		sd_s0_pwr: sd-s0-pwr {
-			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
 };
 
 &edp0 {