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This is the 6.1.99 stable release

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Merge tag 'v6.1.99'

This is the 6.1.99 stable release

* tag 'v6.1.99': (1975 commits)
  Linux 6.1.99
  Revert "usb: xhci: prevent potential failure in handle_tx_event() for Transfer events without TRB"
  Linux 6.1.98
  nilfs2: fix incorrect inode allocation from reserved inodes
  null_blk: Do not allow runt zone with zone capacity smaller then zone size
  spi: cadence: Ensure data lines set to low during dummy-cycle period
  nfc/nci: Add the inconsistency check between the input data length and count
  kbuild: fix short log for AS in link-vmlinux.sh
  nvmet: fix a possible leak when destroy a ctrl during qp establishment
  platform/x86: touchscreen_dmi: Add info for the EZpad 6s Pro
  platform/x86: touchscreen_dmi: Add info for GlobalSpace SolT IVW 11.6" tablet
  regmap-i2c: Subtract reg size from max_write
  nvme: adjust multiples of NVME_CTRL_PAGE_SIZE in offset
  dma-mapping: benchmark: avoid needless copy_to_user if benchmark fails
  nvme-multipath: find NUMA path only for online numa-node
  ALSA: hda/realtek: Enable headset mic of JP-IK LEAP W502 with ALC897
  fs/ntfs3: Mark volume as dirty if xattr is broken
  i2c: pnx: Fix potential deadlock warning from del_timer_sync() call in isr
  clk: mediatek: mt8183: Only enable runtime PM on mt8183-mfgcfg
  clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe()
  ...

Change-Id: Ibf9c2caa3bbffb7a960e82ec6c2b0b497753778c

Conflicts:
	arch/arm64/boot/dts/rockchip/rk3328.dtsi
	drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
	drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
	drivers/pinctrl/pinctrl-rockchip.c
	drivers/usb/gadget/function/u_audio.c
	include/linux/usb/quirks.h
	mm/cma.c
	sound/soc/rockchip/rockchip_i2s_tdm.c
This commit is contained in:
Tao Huang 2024-10-25 17:50:43 +08:00
commit 495fe343ce
1822 changed files with 20361 additions and 12465 deletions
Download patch file Download diff file Expand all files Collapse all files

4
Documentation/admin-guide/hw-vuln/core-scheduling.rst
View file

@ -67,8 +67,8 @@ arg4:
will be performed for all tasks in the task group of ``pid``.
arg5:
userspace pointer to an unsigned long for storing the cookie returned by
``PR_SCHED_CORE_GET`` command. Should be 0 for all other commands.
userspace pointer to an unsigned long long for storing the cookie returned
by ``PR_SCHED_CORE_GET`` command. Should be 0 for all other commands.
In order for a process to push a cookie to, or pull a cookie from a process, it
is required to have the ptrace access mode: `PTRACE_MODE_READ_REALCREDS` to the

44
Documentation/admin-guide/hw-vuln/spectre.rst
View file

@ -138,11 +138,10 @@ associated with the source address of the indirect branch. Specifically,
the BHB might be shared across privilege levels even in the presence of
Enhanced IBRS.
Currently the only known real-world BHB attack vector is via
unprivileged eBPF. Therefore, it's highly recommended to not enable
unprivileged eBPF, especially when eIBRS is used (without retpolines).
For a full mitigation against BHB attacks, it's recommended to use
retpolines (or eIBRS combined with retpolines).
Previously the only known real-world BHB attack vector was via unprivileged
eBPF. Further research has found attacks that don't require unprivileged eBPF.
For a full mitigation against BHB attacks it is recommended to set BHI_DIS_S or
use the BHB clearing sequence.
Attack scenarios
----------------
@ -430,6 +429,23 @@ The possible values in this file are:
'PBRSB-eIBRS: Not affected' CPU is not affected by PBRSB
=========================== =======================================================
- Branch History Injection (BHI) protection status:
.. list-table::
* - BHI: Not affected
- System is not affected
* - BHI: Retpoline
- System is protected by retpoline
* - BHI: BHI_DIS_S
- System is protected by BHI_DIS_S
* - BHI: SW loop, KVM SW loop
- System is protected by software clearing sequence
* - BHI: Vulnerable
- System is vulnerable to BHI
* - BHI: Vulnerable, KVM: SW loop
- System is vulnerable; KVM is protected by software clearing sequence
Full mitigation might require a microcode update from the CPU
vendor. When the necessary microcode is not available, the kernel will
report vulnerability.
@ -484,7 +500,11 @@ Spectre variant 2
Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at
boot, by setting the IBRS bit, and they're automatically protected against
Spectre v2 variant attacks.
some Spectre v2 variant attacks. The BHB can still influence the choice of
indirect branch predictor entry, and although branch predictor entries are
isolated between modes when eIBRS is enabled, the BHB itself is not isolated
between modes. Systems which support BHI_DIS_S will set it to protect against
BHI attacks.
On Intel's enhanced IBRS systems, this includes cross-thread branch target
injections on SMT systems (STIBP). In other words, Intel eIBRS enables
@ -638,6 +658,18 @@ kernel command line.
spectre_v2=off. Spectre variant 1 mitigations
cannot be disabled.
spectre_bhi=
[X86] Control mitigation of Branch History Injection
(BHI) vulnerability. This setting affects the deployment
of the HW BHI control and the SW BHB clearing sequence.
on
(default) Enable the HW or SW mitigation as
needed.
off
Disable the mitigation.
For spectre_v2_user see Documentation/admin-guide/kernel-parameters.txt
Mitigation selection guide

13
Documentation/admin-guide/kernel-parameters.txt
View file

@ -3283,6 +3283,7 @@
reg_file_data_sampling=off [X86]
retbleed=off [X86]
spec_store_bypass_disable=off [X86,PPC]
spectre_bhi=off [X86]
spectre_v2_user=off [X86]
srbds=off [X86,INTEL]
ssbd=force-off [ARM64]
@ -5733,6 +5734,15 @@
sonypi.*= [HW] Sony Programmable I/O Control Device driver
See Documentation/admin-guide/laptops/sonypi.rst
spectre_bhi= [X86] Control mitigation of Branch History Injection
(BHI) vulnerability. This setting affects the
deployment of the HW BHI control and the SW BHB
clearing sequence.
on - (default) Enable the HW or SW mitigation
as needed.
off - Disable the mitigation.
spectre_v2= [X86] Control mitigation of Spectre variant 2
(indirect branch speculation) vulnerability.
The default operation protects the kernel from
@ -6593,6 +6603,9 @@
pause after every control message);
o = USB_QUIRK_HUB_SLOW_RESET (Hub needs extra
delay after resetting its port);
p = USB_QUIRK_SHORT_SET_ADDRESS_REQ_TIMEOUT
(Reduce timeout of the SET_ADDRESS
request from 5000 ms to 500 ms);
Example: quirks=0781:5580:bk,0a5c:5834:gij
usbhid.mousepoll=

5
Documentation/admin-guide/sysctl/net.rst
View file

@ -205,6 +205,11 @@ Will increase power usage.
Default: 0 (off)
mem_pcpu_rsv
------------
Per-cpu reserved forward alloc cache size in page units. Default 1MB per CPU.
rmem_default
------------

4
Documentation/devicetree/bindings/i2c/amlogic,meson6-i2c.yaml
View file

@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/amlogic,meson6-i2c.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/i2c/amlogic,meson6-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson I2C Controller

4
Documentation/devicetree/bindings/i2c/apple,i2c.yaml
View file

@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/apple,i2c.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/i2c/apple,i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple/PASemi I2C controller

2
Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml
View file

@ -75,7 +75,7 @@ required:
- clocks
allOf:
- $ref: "i2c-controller.yaml"
- $ref: /schemas/i2c/i2c-controller.yaml#
- if:
properties:
compatible:

4
Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
View file

@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence I2C controller

2
Documentation/devicetree/bindings/i2c/google,cros-ec-i2c-tunnel.yaml
View file

@ -21,7 +21,7 @@ description: |
google,cros-ec-spi or google,cros-ec-i2c.
allOf:
- $ref: i2c-controller.yaml#
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:

4
Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml
View file

@ -45,7 +45,7 @@ properties:
i2c-parent:
description: phandle of the I2C bus that this multiplexer's master-side port is connected to
$ref: "/schemas/types.yaml#/definitions/phandle"
$ref: /schemas/types.yaml#/definitions/phandle
mux-gpios:
description: list of GPIOs used to control the muxer
@ -55,7 +55,7 @@ properties:
idle-state:
description: Value to set the muxer to when idle. When no value is given, it defaults to the
last value used.
$ref: "/schemas/types.yaml#/definitions/uint32"
$ref: /schemas/types.yaml#/definitions/uint32
allOf:
- $ref: i2c-mux.yaml

4
Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
View file

@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Geni based QUP I2C Controller

2
Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
View file

@ -90,7 +90,7 @@ properties:
st,syscfg-fmp:
description: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
Plus speed is selected by slave.
$ref: "/schemas/types.yaml#/definitions/phandle-array"
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to syscfg

4
Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
View file

@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx IIC controller

2
Documentation/devicetree/bindings/iio/health/maxim,max30102.yaml
View file

@ -42,7 +42,7 @@ allOf:
properties:
compatible:
contains:
const: maxim,max30100
const: maxim,max30102
then:
properties:
maxim,green-led-current-microamp: false

18
Documentation/devicetree/bindings/media/i2c/ovti,ov2680.yaml
View file

@ -37,15 +37,15 @@ properties:
active low.
maxItems: 1
dovdd-supply:
DOVDD-supply:
description:
Definition of the regulator used as interface power supply.
avdd-supply:
AVDD-supply:
description:
Definition of the regulator used as analog power supply.
dvdd-supply:
DVDD-supply:
description:
Definition of the regulator used as digital power supply.
@ -59,9 +59,9 @@ required:
- reg
- clocks
- clock-names
- dovdd-supply
- avdd-supply
- dvdd-supply
- DOVDD-supply
- AVDD-supply
- DVDD-supply
- reset-gpios
- port
@ -82,9 +82,9 @@ examples:
clock-names = "xvclk";
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
dovdd-supply = <&sw2_reg>;
dvdd-supply = <&sw2_reg>;
avdd-supply = <&reg_peri_3p15v>;
DOVDD-supply = <&sw2_reg>;
DVDD-supply = <&sw2_reg>;
AVDD-supply = <&reg_peri_3p15v>;
port {
ov2680_to_mipi: endpoint {

14
Documentation/devicetree/bindings/pci/rcar-pci-host.yaml
View file

@ -68,6 +68,18 @@ properties:
phy-names:
const: pcie
vpcie1v5-supply:
description: The 1.5v regulator to use for PCIe.
vpcie3v3-supply:
description: The 3.3v regulator to use for PCIe.
vpcie12v-supply:
description: The 12v regulator to use for PCIe.
iommu-map: true
iommu-map-mask: true
required:
- compatible
- reg
@ -121,5 +133,7 @@ examples:
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 319>;
vpcie3v3-supply = <&pcie_3v3>;
vpcie12v-supply = <&pcie_12v>;
};
};

92
Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml
View file

@ -97,7 +97,8 @@ patternProperties:
then:
properties:
groups:
enum: [emmc, emmc_rst]
items:
enum: [emmc, emmc_rst]
- if:
properties:
function:
@ -105,8 +106,9 @@ patternProperties:
then:
properties:
groups:
enum: [esw, esw_p0_p1, esw_p2_p3_p4, rgmii_via_esw,
rgmii_via_gmac1, rgmii_via_gmac2, mdc_mdio]
items:
enum: [esw, esw_p0_p1, esw_p2_p3_p4, rgmii_via_esw,
rgmii_via_gmac1, rgmii_via_gmac2, mdc_mdio]
- if:
properties:
function:
@ -123,10 +125,11 @@ patternProperties:
then:
properties:
groups:
enum: [i2s_in_mclk_bclk_ws, i2s1_in_data, i2s2_in_data,
i2s3_in_data, i2s4_in_data, i2s_out_mclk_bclk_ws,
i2s1_out_data, i2s2_out_data, i2s3_out_data,
i2s4_out_data]
items:
enum: [i2s_in_mclk_bclk_ws, i2s1_in_data, i2s2_in_data,
i2s3_in_data, i2s4_in_data, i2s_out_mclk_bclk_ws,
i2s1_out_data, i2s2_out_data, i2s3_out_data,
i2s4_out_data]
- if:
properties:
function:
@ -159,10 +162,11 @@ patternProperties:
then:
properties:
groups:
enum: [pcie0_0_waken, pcie0_1_waken, pcie1_0_waken,
pcie0_0_clkreq, pcie0_1_clkreq, pcie1_0_clkreq,
pcie0_pad_perst, pcie1_pad_perst, pcie_pereset,
pcie_wake, pcie_clkreq]
items:
enum: [pcie0_0_waken, pcie0_1_waken, pcie1_0_waken,
pcie0_0_clkreq, pcie0_1_clkreq, pcie1_0_clkreq,
pcie0_pad_perst, pcie1_pad_perst, pcie_pereset,
pcie_wake, pcie_clkreq]
- if:
properties:
function:
@ -178,11 +182,12 @@ patternProperties:
then:
properties:
groups:
enum: [pwm_ch1_0, pwm_ch1_1, pwm_ch1_2, pwm_ch2_0, pwm_ch2_1,
pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0,
pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1,
pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3,
pwm_ch7_0, pwm_0, pwm_1]
items:
enum: [pwm_ch1_0, pwm_ch1_1, pwm_ch1_2, pwm_ch2_0, pwm_ch2_1,
pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0,
pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1,
pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3,
pwm_ch7_0, pwm_0, pwm_1]
- if:
properties:
function:
@ -260,33 +265,34 @@ patternProperties:
pins:
description: |
An array of strings. Each string contains the name of a pin.
enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0,
RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS,
I2C_SDA, I2C_SCL, I2S2_IN, I2S3_IN, I2S4_IN, I2S2_OUT,
I2S3_OUT, I2S4_OUT, GPIO_B, MDC, MDIO, G2_TXD0, G2_TXD1,
G2_TXD2, G2_TXD3, G2_TXEN, G2_TXC, G2_RXD0, G2_RXD1, G2_RXD2,
G2_RXD3, G2_RXDV, G2_RXC, NCEB, NWEB, NREB, NDL4, NDL5, NDL6,
NDL7, NRB, NCLE, NALE, NDL0, NDL1, NDL2, NDL3, MDI_TP_P0,
MDI_TN_P0, MDI_RP_P0, MDI_RN_P0, MDI_TP_P1, MDI_TN_P1,
MDI_RP_P1, MDI_RN_P1, MDI_RP_P2, MDI_RN_P2, MDI_TP_P2,
MDI_TN_P2, MDI_TP_P3, MDI_TN_P3, MDI_RP_P3, MDI_RN_P3,
MDI_RP_P4, MDI_RN_P4, MDI_TP_P4, MDI_TN_P4, PMIC_SCL,
PMIC_SDA, SPIC1_CLK, SPIC1_MOSI, SPIC1_MISO, SPIC1_CS,
GPIO_D, WATCHDOG, RTS3_N, CTS3_N, TXD3, RXD3, PERST0_N,
PERST1_N, WLED_N, EPHY_LED0_N, AUXIN0, AUXIN1, AUXIN2,
AUXIN3, TXD4, RXD4, RTS4_N, CST4_N, PWM1, PWM2, PWM3, PWM4,
PWM5, PWM6, PWM7, GPIO_E, TOP_5G_CLK, TOP_5G_DATA,
WF0_5G_HB0, WF0_5G_HB1, WF0_5G_HB2, WF0_5G_HB3, WF0_5G_HB4,
WF0_5G_HB5, WF0_5G_HB6, XO_REQ, TOP_RST_N, SYS_WATCHDOG,
EPHY_LED0_N_JTDO, EPHY_LED1_N_JTDI, EPHY_LED2_N_JTMS,
EPHY_LED3_N_JTCLK, EPHY_LED4_N_JTRST_N, WF2G_LED_N,
WF5G_LED_N, GPIO_9, GPIO_10, GPIO_11, GPIO_12, UART1_TXD,
UART1_RXD, UART1_CTS, UART1_RTS, UART2_TXD, UART2_RXD,
UART2_CTS, UART2_RTS, SMI_MDC, SMI_MDIO, PCIE_PERESET_N,
PWM_0, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5,
GPIO_6, GPIO_7, GPIO_8, UART0_TXD, UART0_RXD, TOP_2G_CLK,
TOP_2G_DATA, WF0_2G_HB0, WF0_2G_HB1, WF0_2G_HB2, WF0_2G_HB3,
WF0_2G_HB4, WF0_2G_HB5, WF0_2G_HB6]
items:
enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0,
RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS,
I2C_SDA, I2C_SCL, I2S2_IN, I2S3_IN, I2S4_IN, I2S2_OUT,
I2S3_OUT, I2S4_OUT, GPIO_B, MDC, MDIO, G2_TXD0, G2_TXD1,
G2_TXD2, G2_TXD3, G2_TXEN, G2_TXC, G2_RXD0, G2_RXD1, G2_RXD2,
G2_RXD3, G2_RXDV, G2_RXC, NCEB, NWEB, NREB, NDL4, NDL5, NDL6,
NDL7, NRB, NCLE, NALE, NDL0, NDL1, NDL2, NDL3, MDI_TP_P0,
MDI_TN_P0, MDI_RP_P0, MDI_RN_P0, MDI_TP_P1, MDI_TN_P1,
MDI_RP_P1, MDI_RN_P1, MDI_RP_P2, MDI_RN_P2, MDI_TP_P2,
MDI_TN_P2, MDI_TP_P3, MDI_TN_P3, MDI_RP_P3, MDI_RN_P3,
MDI_RP_P4, MDI_RN_P4, MDI_TP_P4, MDI_TN_P4, PMIC_SCL,
PMIC_SDA, SPIC1_CLK, SPIC1_MOSI, SPIC1_MISO, SPIC1_CS,
GPIO_D, WATCHDOG, RTS3_N, CTS3_N, TXD3, RXD3, PERST0_N,
PERST1_N, WLED_N, EPHY_LED0_N, AUXIN0, AUXIN1, AUXIN2,
AUXIN3, TXD4, RXD4, RTS4_N, CST4_N, PWM1, PWM2, PWM3, PWM4,
PWM5, PWM6, PWM7, GPIO_E, TOP_5G_CLK, TOP_5G_DATA,
WF0_5G_HB0, WF0_5G_HB1, WF0_5G_HB2, WF0_5G_HB3, WF0_5G_HB4,
WF0_5G_HB5, WF0_5G_HB6, XO_REQ, TOP_RST_N, SYS_WATCHDOG,
EPHY_LED0_N_JTDO, EPHY_LED1_N_JTDI, EPHY_LED2_N_JTMS,
EPHY_LED3_N_JTCLK, EPHY_LED4_N_JTRST_N, WF2G_LED_N,
WF5G_LED_N, GPIO_9, GPIO_10, GPIO_11, GPIO_12, UART1_TXD,
UART1_RXD, UART1_CTS, UART1_RTS, UART2_TXD, UART2_RXD,
UART2_CTS, UART2_RTS, SMI_MDC, SMI_MDIO, PCIE_PERESET_N,
PWM_0, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5,
GPIO_6, GPIO_7, GPIO_8, UART0_TXD, UART0_RXD, TOP_2G_CLK,
TOP_2G_DATA, WF0_2G_HB0, WF0_2G_HB1, WF0_2G_HB2, WF0_2G_HB3,
WF0_2G_HB4, WF0_2G_HB5, WF0_2G_HB6]
bias-disable: true

1
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
View file

@ -151,6 +151,7 @@ allOf:
unevaluatedProperties: false
pcie-phy:
type: object
description:
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt

6
Documentation/devicetree/bindings/sound/rt5645.txt
View file

@ -20,6 +20,11 @@ Optional properties:
a GPIO spec for the external headphone detect pin. If jd-mode = 0,
we will get the JD status by getting the value of hp-detect-gpios.
- cbj-sleeve-gpios:
a GPIO spec to control the external combo jack circuit to tie the sleeve/ring2
contacts to the ground or floating. It could avoid some electric noise from the
active speaker jacks.
- realtek,in2-differential
Boolean. Indicate MIC2 input are differential, rather than single-ended.
@ -68,6 +73,7 @@ codec: rt5650@1a {
compatible = "realtek,rt5650";
reg = <0x1a>;
hp-detect-gpios = <&gpio 19 0>;
cbj-sleeve-gpios = <&gpio 20 0>;
interrupt-parent = <&gpio>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
realtek,dmic-en = "true";

13
Documentation/driver-api/fpga/fpga-region.rst
View file

@ -46,13 +46,16 @@ API to add a new FPGA region
----------------------------
* struct fpga_region - The FPGA region struct
* struct fpga_region_info - Parameter structure for fpga_region_register_full()
* fpga_region_register_full() - Create and register an FPGA region using the
* struct fpga_region_info - Parameter structure for __fpga_region_register_full()
* __fpga_region_register_full() - Create and register an FPGA region using the
fpga_region_info structure to provide the full flexibility of options
* fpga_region_register() - Create and register an FPGA region using standard
* __fpga_region_register() - Create and register an FPGA region using standard
arguments
* fpga_region_unregister() - Unregister an FPGA region
Helper macros ``fpga_region_register()`` and ``fpga_region_register_full()``
automatically set the module that registers the FPGA region as the owner.
The FPGA region's probe function will need to get a reference to the FPGA
Manager it will be using to do the programming. This usually would happen
during the region's probe function.
@ -82,10 +85,10 @@ following APIs to handle building or tearing down that list.
:functions: fpga_region_info
.. kernel-doc:: drivers/fpga/fpga-region.c
:functions: fpga_region_register_full
:functions: __fpga_region_register_full
.. kernel-doc:: drivers/fpga/fpga-region.c
:functions: fpga_region_register
:functions: __fpga_region_register
.. kernel-doc:: drivers/fpga/fpga-region.c
:functions: fpga_region_unregister

6
Documentation/mm/arch_pgtable_helpers.rst
View file

@ -136,7 +136,8 @@ PMD Page Table Helpers
+---------------------------+--------------------------------------------------+
| pmd_swp_clear_soft_dirty | Clears a soft dirty swapped PMD |
+---------------------------+--------------------------------------------------+
| pmd_mkinvalid | Invalidates a mapped PMD [1] |
| pmd_mkinvalid | Invalidates a present PMD; do not call for |
| | non-present PMD [1] |
+---------------------------+--------------------------------------------------+
| pmd_set_huge | Creates a PMD huge mapping |
+---------------------------+--------------------------------------------------+
@ -192,7 +193,8 @@ PUD Page Table Helpers
+---------------------------+--------------------------------------------------+
| pud_mkdevmap | Creates a ZONE_DEVICE mapped PUD |
+---------------------------+--------------------------------------------------+
| pud_mkinvalid | Invalidates a mapped PUD [1] |
| pud_mkinvalid | Invalidates a present PUD; do not call for |
| | non-present PUD [1] |
+---------------------------+--------------------------------------------------+
| pud_set_huge | Creates a PUD huge mapping |
+---------------------------+--------------------------------------------------+

32
Documentation/networking/device_drivers/ethernet/amazon/ena.rst
View file

@ -205,6 +205,7 @@ Adaptive coalescing can be switched on/off through `ethtool(8)`'s
More information about Adaptive Interrupt Moderation (DIM) can be found in
Documentation/networking/net_dim.rst
.. _`RX copybreak`:
RX copybreak
============
The rx_copybreak is initialized by default to ENA_DEFAULT_RX_COPYBREAK
@ -315,3 +316,34 @@ Rx
- The new SKB is updated with the necessary information (protocol,
checksum hw verify result, etc), and then passed to the network
stack, using the NAPI interface function :code:`napi_gro_receive()`.
Dynamic RX Buffers (DRB)
------------------------
Each RX descriptor in the RX ring is a single memory page (which is either 4KB
or 16KB long depending on system's configurations).
To reduce the memory allocations required when dealing with a high rate of small
packets, the driver tries to reuse the remaining RX descriptor's space if more
than 2KB of this page remain unused.
A simple example of this mechanism is the following sequence of events:
::
1. Driver allocates page-sized RX buffer and passes it to hardware
+----------------------+
|4KB RX Buffer |
+----------------------+
2. A 300Bytes packet is received on this buffer
3. The driver increases the ref count on this page and returns it back to
HW as an RX buffer of size 4KB - 300Bytes = 3796 Bytes
+----+--------------------+
|****|3796 Bytes RX Buffer|
+----+--------------------+
This mechanism isn't used when an XDP program is loaded, or when the
RX packet is less than rx_copybreak bytes (in which case the packet is
copied out of the RX buffer into the linear part of a new skb allocated
for it and the RX buffer remains the same size, see `RX copybreak`_).

1
Documentation/sphinx/kernel_include.py
View file

@ -97,7 +97,6 @@ class KernelInclude(Include):
# HINT: this is the only line I had to change / commented out:
#path = utils.relative_path(None, path)
path = nodes.reprunicode(path)
encoding = self.options.get(
'encoding', self.state.document.settings.input_encoding)
e_handler=self.state.document.settings.input_encoding_error_handler

3
MAINTAINERS
View file

@ -8031,7 +8031,7 @@ M: Geoffrey D. Bennett <g@b4.vu>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git
F: sound/usb/mixer_scarlett_gen2.c
F: sound/usb/mixer_scarlett2.c
FORCEDETH GIGABIT ETHERNET DRIVER
M: Rain River <rain.1986.08.12@gmail.com>
@ -22557,6 +22557,7 @@ F: include/xen/swiotlb-xen.h
XFS FILESYSTEM
C: irc://irc.oftc.net/xfs
M: Leah Rumancik <leah.rumancik@gmail.com>
M: Darrick J. Wong <djwong@kernel.org>
L: linux-xfs@vger.kernel.org
S: Supported

7
Makefile
View file

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 1
SUBLEVEL = 84
SUBLEVEL = 99
EXTRAVERSION =
NAME = Curry Ramen
@ -980,7 +980,6 @@ endif
ifdef CONFIG_LTO_CLANG
ifdef CONFIG_LTO_CLANG_THIN
CC_FLAGS_LTO := -flto=thin -fsplit-lto-unit
KBUILD_LDFLAGS += --thinlto-cache-dir=$(extmod_prefix).thinlto-cache
else
CC_FLAGS_LTO := -flto
endif
@ -1588,7 +1587,7 @@ endif # CONFIG_MODULES
# Directories & files removed with 'make clean'
CLEAN_FILES += include/ksym vmlinux.symvers modules-only.symvers \
modules.builtin modules.builtin.modinfo modules.nsdeps \
compile_commands.json .thinlto-cache rust/test rust/doc \
compile_commands.json rust/test rust/doc \
.vmlinux.objs .vmlinux.export.c
# Directories & files removed with 'make mrproper'
@ -1884,7 +1883,7 @@ PHONY += compile_commands.json
clean-dirs := $(KBUILD_EXTMOD)
clean: rm-files := $(KBUILD_EXTMOD)/Module.symvers $(KBUILD_EXTMOD)/modules.nsdeps \
$(KBUILD_EXTMOD)/compile_commands.json $(KBUILD_EXTMOD)/.thinlto-cache
$(KBUILD_EXTMOD)/compile_commands.json
PHONY += prepare
# now expand this into a simple variable to reduce the cost of shell evaluations

8
arch/Kconfig
View file

@ -9,6 +9,14 @@
#
source "arch/$(SRCARCH)/Kconfig"
config ARCH_CONFIGURES_CPU_MITIGATIONS
bool
if !ARCH_CONFIGURES_CPU_MITIGATIONS
config CPU_MITIGATIONS
def_bool y
endif
menu "General architecture-dependent options"
config CRASH_CORE

1
arch/arc/boot/dts/hsdk.dts
View file

@ -205,7 +205,6 @@
};
gmac: ethernet@8000 {
#interrupt-cells = <1>;
compatible = "snps,dwmac";
reg = <0x8000 0x2000>;
interrupts = <10>;

8
arch/arm/boot/dts/at91-sama7g5ek.dts
View file

@ -293,7 +293,7 @@
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-voltage = <1150000>;
regulator-suspend-microvolt = <1150000>;
regulator-mode = <4>;
};
@ -314,7 +314,7 @@
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-voltage = <1050000>;
regulator-suspend-microvolt = <1050000>;
regulator-mode = <4>;
};
@ -331,7 +331,7 @@
regulator-always-on;
regulator-state-standby {
regulator-suspend-voltage = <1800000>;
regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};
@ -346,7 +346,7 @@
regulator-max-microvolt = <3700000>;
regulator-state-standby {
regulator-suspend-voltage = <1800000>;
regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};

2
arch/arm/boot/dts/exynos4210-smdkv310.dts
View file

@ -84,7 +84,7 @@
&keypad {
samsung,keypad-num-rows = <2>;
samsung,keypad-num-columns = <8>;
linux,keypad-no-autorepeat;
linux,input-no-autorepeat;
wakeup-source;
pinctrl-names = "default";
pinctrl-0 = <&keypad_rows &keypad_cols>;

2
arch/arm/boot/dts/exynos4412-origen.dts
View file

@ -448,7 +448,7 @@
&keypad {
samsung,keypad-num-rows = <3>;
samsung,keypad-num-columns = <2>;
linux,keypad-no-autorepeat;
linux,input-no-autorepeat;
wakeup-source;
pinctrl-0 = <&keypad_rows &keypad_cols>;
pinctrl-names = "default";

2
arch/arm/boot/dts/exynos4412-smdk4412.dts
View file

@ -65,7 +65,7 @@
&keypad {
samsung,keypad-num-rows = <3>;
samsung,keypad-num-columns = <8>;
linux,keypad-no-autorepeat;
linux,input-no-autorepeat;
wakeup-source;
pinctrl-0 = <&keypad_rows &keypad_cols>;
pinctrl-names = "default";

1
arch/arm/boot/dts/rk3066a.dtsi
View file

@ -231,6 +231,7 @@
pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
power-domains = <&power RK3066_PD_VIO>;
rockchip,grf = <&grf>;
#sound-dai-cells = <0>;
status = "disabled";
ports {

1
arch/arm/configs/sunxi_defconfig
View file

@ -110,6 +110,7 @@ CONFIG_DRM_PANEL_LVDS=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_EDP=y
CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_DW_HDMI=y
CONFIG_DRM_LIMA=y
CONFIG_FB_SIMPLE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y

4
arch/arm/kernel/sleep.S
View file

@ -127,6 +127,10 @@ cpu_resume_after_mmu:
instr_sync
#endif
bl cpu_init @ restore the und/abt/irq banked regs
#if defined(CONFIG_KASAN) && defined(CONFIG_KASAN_STACK)
mov r0, sp
bl kasan_unpoison_task_stack_below
#endif
mov r0, #0 @ return zero on success
ldmfd sp!, {r4 - r11, pc}
ENDPROC(cpu_resume_after_mmu)

5
arch/arm/mach-omap2/board-n8x0.c
View file

@ -22,7 +22,6 @@
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/mmc-omap.h>
#include <linux/mfd/menelaus.h>
#include <sound/tlv320aic3x.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@ -567,10 +566,6 @@ struct menelaus_platform_data n8x0_menelaus_platform_data = {
.late_init = n8x0_menelaus_late_init,
};
struct aic3x_pdata n810_aic33_data = {
.gpio_reset = 118,
};
static int __init n8x0_late_initcall(void)
{
if (!board_caps)

2
arch/arm/mach-omap2/common-board-devices.h
View file

@ -2,12 +2,10 @@
#ifndef __OMAP_COMMON_BOARD_DEVICES__
#define __OMAP_COMMON_BOARD_DEVICES__
#include <sound/tlv320aic3x.h>
#include <linux/mfd/menelaus.h>
void *n8x0_legacy_init(void);
extern struct menelaus_platform_data n8x0_menelaus_platform_data;
extern struct aic3x_pdata n810_aic33_data;
#endif /* __OMAP_COMMON_BOARD_DEVICES__ */

1
arch/arm/mach-omap2/pdata-quirks.c
View file

@ -440,7 +440,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
#ifdef CONFIG_MACH_NOKIA_N8X0
OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data),
OF_DEV_AUXDATA("tlv320aic3x", 0x18, "2-0018", &n810_aic33_data),
#endif
#ifdef CONFIG_ARCH_OMAP3
OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",

1
arch/arm64/Kconfig
View file

@ -1752,7 +1752,6 @@ config ARM64_LSE_ATOMICS
config ARM64_USE_LSE_ATOMICS
bool "Atomic instructions"
depends on JUMP_LABEL
default y
help
As part of the Large System Extensions, ARMv8.1 introduces new

13
arch/arm64/boot/dts/amlogic/meson-s4.dtsi
View file

@ -61,10 +61,15 @@
#clock-cells = <0>;
};
pwrc: power-controller {
compatible = "amlogic,meson-s4-pwrc";
#power-domain-cells = <1>;
status = "okay";
firmware {
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
pwrc: power-controller {
compatible = "amlogic,meson-s4-pwrc";
#power-domain-cells = <1>;
};
};
};
soc {

12
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
View file

@ -38,8 +38,8 @@ conn_subsys: bus@5b000000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
<&sdhc0_lpcg IMX_LPCG_CLK_0>,
<&sdhc0_lpcg IMX_LPCG_CLK_5>;
<&sdhc0_lpcg IMX_LPCG_CLK_5>,
<&sdhc0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled";
@ -49,8 +49,8 @@ conn_subsys: bus@5b000000 {
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
<&sdhc1_lpcg IMX_LPCG_CLK_0>,
<&sdhc1_lpcg IMX_LPCG_CLK_5>;
<&sdhc1_lpcg IMX_LPCG_CLK_5>,
<&sdhc1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
@ -62,8 +62,8 @@ conn_subsys: bus@5b000000 {
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
<&sdhc2_lpcg IMX_LPCG_CLK_0>,
<&sdhc2_lpcg IMX_LPCG_CLK_5>;
<&sdhc2_lpcg IMX_LPCG_CLK_5>,
<&sdhc2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled";

2
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View file

@ -930,7 +930,7 @@
/* Verdin GPIO_9_DSI (pulled-up as active-low) */
pinctrl_gpio_9_dsi: gpio9dsigrp {
fsl,pins =
<MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */
<MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */
};
/* Verdin GPIO_10_DSI (pulled-up as active-low) */

2
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View file

@ -32,7 +32,7 @@
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

1
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
View file

@ -60,7 +60,6 @@
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
no-sdio;
no-mmc;
};

2
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
View file

@ -58,7 +58,7 @@
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
<0x0 0xf1002000 0x0 0x100>; /* GICC */
<0x0 0xf1002000 0x0 0x2000>; /* GICC */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;

8
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
View file

@ -128,7 +128,7 @@
};
&pio {
eth_default: eth_default {
eth_default: eth-default-pins {
tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
@ -155,7 +155,7 @@
};
};
eth_sleep: eth_sleep {
eth_sleep: eth-sleep-pins {
tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
@ -181,14 +181,14 @@
};
};
usb0_id_pins_float: usb0_iddig {
usb0_id_pins_float: usb0-iddig-pins {
pins_iddig {
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
bias-pull-up;
};
};
usb1_id_pins_float: usb1_iddig {
usb1_id_pins_float: usb1-iddig-pins {
pins_iddig {
pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
bias-pull-up;

3
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View file

@ -249,10 +249,11 @@
#clock-cells = <1>;
};
infracfg: syscon@10001000 {
infracfg: clock-controller@10001000 {
compatible = "mediatek,mt2712-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pericfg: syscon@10003000 {

34
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View file

@ -251,7 +251,7 @@
clock-names = "hif_sel";
};
cir: cir@10009000 {
cir: ir-receiver@10009000 {
compatible = "mediatek,mt7622-cir";
reg = <0 0x10009000 0 0x1000>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
@ -282,16 +282,14 @@
};
};
apmixedsys: apmixedsys@10209000 {
compatible = "mediatek,mt7622-apmixedsys",
"syscon";
apmixedsys: clock-controller@10209000 {
compatible = "mediatek,mt7622-apmixedsys";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
topckgen: topckgen@10210000 {
compatible = "mediatek,mt7622-topckgen",
"syscon";
topckgen: clock-controller@10210000 {
compatible = "mediatek,mt7622-topckgen";
reg = <0 0x10210000 0 0x1000>;
#clock-cells = <1>;
};
@ -514,7 +512,6 @@
<&pericfg CLK_PERI_AUXADC_PD>;
clock-names = "therm", "auxadc";
resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
reset-names = "therm";
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration>;
@ -734,9 +731,8 @@
power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
};
ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys",
"syscon";
ssusbsys: clock-controller@1a000000 {
compatible = "mediatek,mt7622-ssusbsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -793,9 +789,8 @@
};
};
pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys",
"syscon";
pciesys: clock-controller@1a100800 {
compatible = "mediatek,mt7622-pciesys";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -921,12 +916,13 @@
};
};
hifsys: syscon@1af00000 {
compatible = "mediatek,mt7622-hifsys", "syscon";
hifsys: clock-controller@1af00000 {
compatible = "mediatek,mt7622-hifsys";
reg = <0 0x1af00000 0 0x70>;
#clock-cells = <1>;
};
ethsys: syscon@1b000000 {
ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt7622-ethsys",
"syscon";
reg = <0 0x1b000000 0 0x1000>;
@ -966,9 +962,7 @@
};
eth: ethernet@1b100000 {
compatible = "mediatek,mt7622-eth",
"mediatek,mt2701-eth",
"syscon";
compatible = "mediatek,mt7622-eth";
reg = <0 0x1b100000 0 0x20000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,

1
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View file

@ -1554,6 +1554,7 @@
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>;
};
gpu: gpu@13040000 {

6
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
View file

@ -903,7 +903,7 @@
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
@ -913,7 +913,7 @@
mt6315_6_vbuck3: vbuck3 {
regulator-compatible = "vbuck3";
regulator-name = "Vlcpu";
regulator-min-microvolt = <300000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
@ -930,7 +930,7 @@
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <606250>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <800000>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;

1
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View file

@ -1240,6 +1240,7 @@
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
<CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;

4
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View file

@ -845,7 +845,7 @@
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>;
@ -863,7 +863,7 @@
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <625000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>;

4
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View file

@ -1492,6 +1492,7 @@
compatible = "mediatek,mt8195-vppsys0";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
};
smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
@ -1597,6 +1598,7 @@
compatible = "mediatek,mt8195-vppsys1";
reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
};
larb5: larb@14f02000 {
@ -1982,6 +1984,7 @@
reg = <0 0x1c01a000 0 0x1000>;
mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
};
larb20: larb@1b010000 {
@ -2085,6 +2088,7 @@
interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
};

4
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
View file

@ -9,8 +9,8 @@
compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124";
aliases {
rtc0 = "/i2c@7000d000/as3722@40";
rtc1 = "/rtc@7000e000";
rtc0 = &as3722;
rtc1 = &tegra_rtc;
serial0 = &uarta;
};

2
arch/arm64/boot/dts/nvidia/tegra132.dtsi
View file

@ -579,7 +579,7 @@
status = "disabled";
};
rtc@7000e000 {
tegra_rtc: rtc@7000e000 {
compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
reg = <0x0 0x7000e000 0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
View file

@ -60,7 +60,7 @@
vddrf-supply = <&vreg_l1_1p3>;
vddch0-supply = <&vdd_ch0_3p3>;
local-bd-address = [ 02 00 00 00 5a ad ];
local-bd-address = [ 00 00 00 00 00 00 ];
max-speed = <3200000>;
};

86
arch/arm64/boot/dts/qcom/sa8155p-adp.dts
View file

@ -372,6 +372,16 @@
};
};
&pmm8155au_1_gpios {
pmm8155au_1_sdc2_cd: sdc2-cd-default-state {
pins = "gpio4";
function = "normal";
input-enable;
bias-pull-up;
power-source = <0>;
};
};
&qupv3_id_1 {
status = "okay";
};
@ -389,10 +399,10 @@
&sdhc_2 {
status = "okay";
cd-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
cd-gpios = <&pmm8155au_1_gpios 4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
pinctrl-0 = <&sdc2_on &pmm8155au_1_sdc2_cd>;
pinctrl-1 = <&sdc2_off &pmm8155au_1_sdc2_cd>;
vqmmc-supply = <&vreg_l13c_2p96>; /* IO line power */
vmmc-supply = <&vreg_l17a_2p96>; /* Card power line */
bus-width = <4>;
@ -488,120 +498,102 @@
&tlmm {
gpio-reserved-ranges = <0 4>;
sdc2_on: sdc2_on {
clk {
sdc2_on: sdc2-on-state {
clk-pins {
pins = "sdc2_clk";
bias-disable; /* No pull */
drive-strength = <16>; /* 16 MA */
};
cmd {
cmd-pins {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
data {
data-pins {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
sd-cd {
pins = "gpio96";
function = "gpio";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
sdc2_off: sdc2_off {
clk {
sdc2_off: sdc2-off-state {
clk-pins {
pins = "sdc2_clk";
bias-disable; /* No pull */
drive-strength = <2>; /* 2 MA */
};
cmd {
cmd-pins {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
data {
data-pins {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
sd-cd {
pins = "gpio96";
function = "gpio";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
usb2phy_ac_en1_default: usb2phy_ac_en1_default {
mux {
pins = "gpio113";
function = "usb2phy_ac";
bias-disable;
drive-strength = <2>;
};
usb2phy_ac_en1_default: usb2phy-ac-en1-default-state {
pins = "gpio113";
function = "usb2phy_ac";
bias-disable;
drive-strength = <2>;
};
usb2phy_ac_en2_default: usb2phy_ac_en2_default {
mux {
pins = "gpio123";
function = "usb2phy_ac";
bias-disable;
drive-strength = <2>;
};
usb2phy_ac_en2_default: usb2phy-ac-en2-default-state {
pins = "gpio123";
function = "usb2phy_ac";
bias-disable;
drive-strength = <2>;
};
ethernet_defaults: ethernet-defaults {
mdc {
ethernet_defaults: ethernet-defaults-state {
mdc-pins {
pins = "gpio7";
function = "rgmii";
bias-pull-up;
};
mdio {
mdio-pins {
pins = "gpio59";
function = "rgmii";
bias-pull-up;
};
rgmii-rx {
rgmii-rx-pins {
pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116";
function = "rgmii";
bias-disable;
drive-strength = <2>;
};
rgmii-tx {
rgmii-tx-pins {
pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121";
function = "rgmii";
bias-pull-up;
drive-strength = <16>;
};
phy-intr {
phy-intr-pins {
pins = "gpio124";
function = "emac_phy";
bias-disable;
drive-strength = <8>;
};
pps {
pps-pins {
pins = "gpio81";
function = "emac_pps";
bias-disable;
drive-strength = <8>;
};
phy-reset {
phy-reset-pins {
pins = "gpio79";
function = "gpio";
bias-pull-up;

2
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View file

@ -923,6 +923,8 @@ ap_spi_fp: &spi10 {
vddrf-supply = <&pp1300_l2c>;
vddch0-supply = <&pp3300_l10c>;
max-speed = <3200000>;
qcom,local-bd-address-broken;
};
};

2
arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
View file

@ -475,7 +475,7 @@
&tlmm {
gpio-reserved-ranges = <126 4>;
da7280_intr_default: da7280-intr-default {
da7280_intr_default: da7280-intr-default-state {
pins = "gpio42";
function = "gpio";
bias-pull-up;

376
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file

@ -2284,422 +2284,302 @@
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
qup_i2c0_default: qup-i2c0-default {
mux {
pins = "gpio0", "gpio1";
function = "qup0";
};
config {
pins = "gpio0", "gpio1";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c0_default: qup-i2c0-default-state {
pins = "gpio0", "gpio1";
function = "qup0";
drive-strength = <0x02>;
bias-disable;
};
qup_spi0_default: qup-spi0-default {
qup_spi0_default: qup-spi0-default-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "qup0";
drive-strength = <6>;
bias-disable;
};
qup_i2c1_default: qup-i2c1-default {
mux {
pins = "gpio114", "gpio115";
function = "qup1";
};
config {
pins = "gpio114", "gpio115";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c1_default: qup-i2c1-default-state {
pins = "gpio114", "gpio115";
function = "qup1";
drive-strength = <2>;
bias-disable;
};
qup_spi1_default: qup-spi1-default {
qup_spi1_default: qup-spi1-default-state {
pins = "gpio114", "gpio115", "gpio116", "gpio117";
function = "qup1";
drive-strength = <6>;
bias-disable;
};
qup_i2c2_default: qup-i2c2-default {
mux {
pins = "gpio126", "gpio127";
function = "qup2";
};
config {
pins = "gpio126", "gpio127";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c2_default: qup-i2c2-default-state {
pins = "gpio126", "gpio127";
function = "qup2";
drive-strength = <2>;
bias-disable;
};
qup_spi2_default: qup-spi2-default {
qup_spi2_default: qup-spi2-default-state {
pins = "gpio126", "gpio127", "gpio128", "gpio129";
function = "qup2";
drive-strength = <6>;
bias-disable;
};
qup_i2c3_default: qup-i2c3-default {
mux {
pins = "gpio144", "gpio145";
function = "qup3";
};
config {
pins = "gpio144", "gpio145";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c3_default: qup-i2c3-default-state {
pins = "gpio144", "gpio145";
function = "qup3";
drive-strength = <2>;
bias-disable;
};
qup_spi3_default: qup-spi3-default {
qup_spi3_default: qup-spi3-default-state {
pins = "gpio144", "gpio145", "gpio146", "gpio147";
function = "qup3";
drive-strength = <6>;
bias-disable;
};
qup_i2c4_default: qup-i2c4-default {
mux {
pins = "gpio51", "gpio52";
function = "qup4";
};
config {
pins = "gpio51", "gpio52";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c4_default: qup-i2c4-default-state {
pins = "gpio51", "gpio52";
function = "qup4";
drive-strength = <2>;
bias-disable;
};
qup_spi4_default: qup-spi4-default {
qup_spi4_default: qup-spi4-default-state {
pins = "gpio51", "gpio52", "gpio53", "gpio54";
function = "qup4";
drive-strength = <6>;
bias-disable;
};
qup_i2c5_default: qup-i2c5-default {
mux {
pins = "gpio121", "gpio122";
function = "qup5";
};
config {
pins = "gpio121", "gpio122";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c5_default: qup-i2c5-default-state {
pins = "gpio121", "gpio122";
function = "qup5";
drive-strength = <2>;
bias-disable;
};
qup_spi5_default: qup-spi5-default {
qup_spi5_default: qup-spi5-default-state {
pins = "gpio119", "gpio120", "gpio121", "gpio122";
function = "qup5";
drive-strength = <6>;
bias-disable;
};
qup_i2c6_default: qup-i2c6-default {
mux {
pins = "gpio6", "gpio7";
function = "qup6";
};
config {
pins = "gpio6", "gpio7";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c6_default: qup-i2c6-default-state {
pins = "gpio6", "gpio7";
function = "qup6";
drive-strength = <2>;
bias-disable;
};
qup_spi6_default: qup-spi6_default {
qup_spi6_default: qup-spi6_default-state {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "qup6";
drive-strength = <6>;
bias-disable;
};
qup_i2c7_default: qup-i2c7-default {
mux {
pins = "gpio98", "gpio99";
function = "qup7";
};
config {
pins = "gpio98", "gpio99";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c7_default: qup-i2c7-default-state {
pins = "gpio98", "gpio99";
function = "qup7";
drive-strength = <2>;
bias-disable;
};
qup_spi7_default: qup-spi7_default {
qup_spi7_default: qup-spi7_default-state {
pins = "gpio98", "gpio99", "gpio100", "gpio101";
function = "qup7";
drive-strength = <6>;
bias-disable;
};
qup_i2c8_default: qup-i2c8-default {
mux {
pins = "gpio88", "gpio89";
function = "qup8";
};
config {
pins = "gpio88", "gpio89";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c8_default: qup-i2c8-default-state {
pins = "gpio88", "gpio89";
function = "qup8";
drive-strength = <2>;
bias-disable;
};
qup_spi8_default: qup-spi8-default {
qup_spi8_default: qup-spi8-default-state {
pins = "gpio88", "gpio89", "gpio90", "gpio91";
function = "qup8";
drive-strength = <6>;
bias-disable;
};
qup_i2c9_default: qup-i2c9-default {
mux {
pins = "gpio39", "gpio40";
function = "qup9";
};
config {
pins = "gpio39", "gpio40";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c9_default: qup-i2c9-default-state {
pins = "gpio39", "gpio40";
function = "qup9";
drive-strength = <2>;
bias-disable;
};
qup_spi9_default: qup-spi9-default {
qup_spi9_default: qup-spi9-default-state {
pins = "gpio39", "gpio40", "gpio41", "gpio42";
function = "qup9";
drive-strength = <6>;
bias-disable;
};
qup_i2c10_default: qup-i2c10-default {
mux {
pins = "gpio9", "gpio10";
function = "qup10";
};
config {
pins = "gpio9", "gpio10";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c10_default: qup-i2c10-default-state {
pins = "gpio9", "gpio10";
function = "qup10";
drive-strength = <2>;
bias-disable;
};
qup_spi10_default: qup-spi10-default {
qup_spi10_default: qup-spi10-default-state {
pins = "gpio9", "gpio10", "gpio11", "gpio12";
function = "qup10";
drive-strength = <6>;
bias-disable;
};
qup_i2c11_default: qup-i2c11-default {
mux {
pins = "gpio94", "gpio95";
function = "qup11";
};
config {
pins = "gpio94", "gpio95";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c11_default: qup-i2c11-default-state {
pins = "gpio94", "gpio95";
function = "qup11";
drive-strength = <2>;
bias-disable;
};
qup_spi11_default: qup-spi11-default {
qup_spi11_default: qup-spi11-default-state {
pins = "gpio92", "gpio93", "gpio94", "gpio95";
function = "qup11";
drive-strength = <6>;
bias-disable;
};
qup_i2c12_default: qup-i2c12-default {
mux {
pins = "gpio83", "gpio84";
function = "qup12";
};
config {
pins = "gpio83", "gpio84";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c12_default: qup-i2c12-default-state {
pins = "gpio83", "gpio84";
function = "qup12";
drive-strength = <2>;
bias-disable;
};
qup_spi12_default: qup-spi12-default {
qup_spi12_default: qup-spi12-default-state {
pins = "gpio83", "gpio84", "gpio85", "gpio86";
function = "qup12";
drive-strength = <6>;
bias-disable;
};
qup_i2c13_default: qup-i2c13-default {
mux {
pins = "gpio43", "gpio44";
function = "qup13";
};
config {
pins = "gpio43", "gpio44";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c13_default: qup-i2c13-default-state {
pins = "gpio43", "gpio44";
function = "qup13";
drive-strength = <2>;
bias-disable;
};
qup_spi13_default: qup-spi13-default {
qup_spi13_default: qup-spi13-default-state {
pins = "gpio43", "gpio44", "gpio45", "gpio46";
function = "qup13";
drive-strength = <6>;
bias-disable;
};
qup_i2c14_default: qup-i2c14-default {
mux {
pins = "gpio47", "gpio48";
function = "qup14";
};
config {
pins = "gpio47", "gpio48";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c14_default: qup-i2c14-default-state {
pins = "gpio47", "gpio48";
function = "qup14";
drive-strength = <2>;
bias-disable;
};
qup_spi14_default: qup-spi14-default {
qup_spi14_default: qup-spi14-default-state {
pins = "gpio47", "gpio48", "gpio49", "gpio50";
function = "qup14";
drive-strength = <6>;
bias-disable;
};
qup_i2c15_default: qup-i2c15-default {
mux {
pins = "gpio27", "gpio28";
function = "qup15";
};
config {
pins = "gpio27", "gpio28";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c15_default: qup-i2c15-default-state {
pins = "gpio27", "gpio28";
function = "qup15";
drive-strength = <2>;
bias-disable;
};
qup_spi15_default: qup-spi15-default {
qup_spi15_default: qup-spi15-default-state {
pins = "gpio27", "gpio28", "gpio29", "gpio30";
function = "qup15";
drive-strength = <6>;
bias-disable;
};
qup_i2c16_default: qup-i2c16-default {
mux {
pins = "gpio86", "gpio85";
function = "qup16";
};
config {
pins = "gpio86", "gpio85";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c16_default: qup-i2c16-default-state {
pins = "gpio86", "gpio85";
function = "qup16";
drive-strength = <2>;
bias-disable;
};
qup_spi16_default: qup-spi16-default {
qup_spi16_default: qup-spi16-default-state {
pins = "gpio83", "gpio84", "gpio85", "gpio86";
function = "qup16";
drive-strength = <6>;
bias-disable;
};
qup_i2c17_default: qup-i2c17-default {
mux {
pins = "gpio55", "gpio56";
function = "qup17";
};
config {
pins = "gpio55", "gpio56";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c17_default: qup-i2c17-default-state {
pins = "gpio55", "gpio56";
function = "qup17";
drive-strength = <2>;
bias-disable;
};
qup_spi17_default: qup-spi17-default {
qup_spi17_default: qup-spi17-default-state {
pins = "gpio55", "gpio56", "gpio57", "gpio58";
function = "qup17";
drive-strength = <6>;
bias-disable;
};
qup_i2c18_default: qup-i2c18-default {
mux {
pins = "gpio23", "gpio24";
function = "qup18";
};
config {
pins = "gpio23", "gpio24";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c18_default: qup-i2c18-default-state {
pins = "gpio23", "gpio24";
function = "qup18";
drive-strength = <2>;
bias-disable;
};
qup_spi18_default: qup-spi18-default {
qup_spi18_default: qup-spi18-default-state {
pins = "gpio23", "gpio24", "gpio25", "gpio26";
function = "qup18";
drive-strength = <6>;
bias-disable;
};
qup_i2c19_default: qup-i2c19-default {
mux {
pins = "gpio57", "gpio58";
function = "qup19";
};
config {
pins = "gpio57", "gpio58";
drive-strength = <0x02>;
bias-disable;
};
qup_i2c19_default: qup-i2c19-default-state {
pins = "gpio57", "gpio58";
function = "qup19";
drive-strength = <2>;
bias-disable;
};
qup_spi19_default: qup-spi19-default {
qup_spi19_default: qup-spi19-default-state {
pins = "gpio55", "gpio56", "gpio57", "gpio58";
function = "qup19";
drive-strength = <6>;
bias-disable;
};
pcie0_default_state: pcie0-default {
perst {
pcie0_default_state: pcie0-default-state {
perst-pins {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq {
clkreq-pins {
pins = "gpio36";
function = "pci_e0";
drive-strength = <2>;
bias-pull-up;
};
wake {
wake-pins {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
@ -2707,22 +2587,22 @@
};
};
pcie1_default_state: pcie1-default {
perst {
pcie1_default_state: pcie1-default-state {
perst-pins {
pins = "gpio102";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq {
clkreq-pins {
pins = "gpio103";
function = "pci_e1";
drive-strength = <2>;
bias-pull-up;
};
wake {
wake-pins {
pins = "gpio104";
function = "gpio";
drive-strength = <2>;

18
arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
View file

@ -5,6 +5,8 @@
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "rk3308.dtsi"
/ {
@ -24,17 +26,21 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>;
pinctrl-0 = <&green_led>, <&heartbeat_led>;
green-led {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_POWER;
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
label = "rockpis:green:power";
linux,default-trigger = "default-on";
};
blue-led {
color = <LED_COLOR_ID_BLUE>;
default-state = "on";
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
label = "rockpis:blue:user";
linux,default-trigger = "heartbeat";
@ -127,10 +133,12 @@
};
&emmc {
bus-width = <4>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
cap-sd-highspeed;
no-sdio;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
vmmc-supply = <&vcc_io>;
status = "okay";
};
@ -153,11 +161,11 @@
pinctrl-0 = <&rtc_32k>;
leds {
green_led_gio: green-led-gpio {
green_led: green-led {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
heartbeat_led_gpio: heartbeat-led-gpio {
heartbeat_led: heartbeat-led {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
View file

@ -186,8 +186,8 @@
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;

3
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View file

@ -794,6 +794,7 @@
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx>;
#sound-dai-cells = <0>;
status = "disabled";
};
@ -805,6 +806,7 @@
clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
dmas = <&dmac_bus 6>, <&dmac_bus 7>;
dma-names = "tx", "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
@ -818,6 +820,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_bus>;
#sound-dai-cells = <0>;
status = "disabled";
};

1
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
View file

@ -789,7 +789,6 @@
};
&pcie0 {
bus-scan-delay-ms = <1000>;
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";

31
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
View file

@ -401,16 +401,22 @@
gpio1830-supply = <&vcc_1v8>;
};
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&vcc_1v8>;
};
&pwm2 {
status = "okay";
&pcie_clkreqn_cpm {
rockchip,pins =
<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&q7_thermal_pin>;
gpios {
q7_thermal_pin: q7-thermal-pin {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
i2c8 {
i2c8_xfer_a: i2c8-xfer {
rockchip,pins =
@ -443,11 +449,20 @@
usb3 {
usb3_id: usb3-id {
rockchip,pins =
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&vcc_1v8>;
};
&pwm2 {
status = "okay";
};
&sdhci {
/*
* Signal integrity isn't great at 200MHz but 100MHz has proven stable

12
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View file

@ -2181,6 +2181,7 @@
hdmi: hdmi@ff940000 {
compatible = "rockchip,rk3399-dw-hdmi";
reg = <0x0 0xff940000 0x0 0x20000>;
reg-io-width = <4>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_HDMI_CTRL>,
<&cru SCLK_HDMI_SFR>,
@ -2189,7 +2190,6 @@
<&cru PLL_VPLL>;
clock-names = "iahb", "isfr", "cec", "grf", "ref";
power-domains = <&power RK3399_PD_HDCP>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
@ -2197,7 +2197,11 @@
status = "disabled";
ports {
hdmi_in: port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
@ -2210,6 +2214,10 @@
remote-endpoint = <&vopl_out_hdmi>;
};
};
hdmi_out: port@1 {
reg = <1>;
};
};
};

2
arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
View file

@ -290,7 +290,7 @@
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;

6
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
View file

@ -412,6 +412,8 @@
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@ -521,9 +523,9 @@
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
switch@1f {
compatible = "mediatek,mt7531";
reg = <0>;
reg = <0x1f>;
ports {
#address-cells = <1>;

1
arch/arm64/include/asm/asm-bug.h
View file

@ -28,6 +28,7 @@
14470: .long 14471f - .; \
_BUGVERBOSE_LOCATION(__FILE__, __LINE__) \
.short flags; \
.align 2; \
.popsection; \
14471:
#else

1
arch/arm64/include/asm/lse.h
View file

@ -10,7 +10,6 @@
#include <linux/compiler_types.h>
#include <linux/export.h>
#include <linux/jump_label.h>
#include <linux/stringify.h>
#include <asm/alternative.h>
#include <asm/alternative-macros.h>

2
arch/arm64/include/asm/unistd32.h
View file

@ -840,7 +840,7 @@ __SYSCALL(__NR_pselect6_time64, compat_sys_pselect6_time64)
#define __NR_ppoll_time64 414
__SYSCALL(__NR_ppoll_time64, compat_sys_ppoll_time64)
#define __NR_io_pgetevents_time64 416
__SYSCALL(__NR_io_pgetevents_time64, sys_io_pgetevents)
__SYSCALL(__NR_io_pgetevents_time64, compat_sys_io_pgetevents_time64)
#define __NR_recvmmsg_time64 417
__SYSCALL(__NR_recvmmsg_time64, compat_sys_recvmmsg_time64)
#define __NR_mq_timedsend_time64 418

16
arch/arm64/kernel/syscall.c
View file

@ -57,17 +57,15 @@ static void invoke_syscall(struct pt_regs *regs, unsigned int scno,
syscall_set_return_value(current, regs, 0, ret);
/*
* Ultimately, this value will get limited by KSTACK_OFFSET_MAX(),
* but not enough for arm64 stack utilization comfort. To keep
* reasonable stack head room, reduce the maximum offset to 9 bits.
* This value will get limited by KSTACK_OFFSET_MAX(), which is 10
* bits. The actual entropy will be further reduced by the compiler
* when applying stack alignment constraints: the AAPCS mandates a
* 16-byte aligned SP at function boundaries, which will remove the
* 4 low bits from any entropy chosen here.
*
* The actual entropy will be further reduced by the compiler when
* applying stack alignment constraints: the AAPCS mandates a
* 16-byte (i.e. 4-bit) aligned SP at function boundaries.
*
* The resulting 5 bits of entropy is seen in SP[8:4].
* The resulting 6 bits of entropy is seen in SP[9:4].
*/
choose_random_kstack_offset(get_random_u16() & 0x1FF);
choose_random_kstack_offset(get_random_u16());
}
static inline bool has_syscall_work(unsigned long flags)

3
arch/arm64/kvm/guest.c
View file

@ -250,6 +250,7 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
case PSR_AA32_MODE_SVC:
case PSR_AA32_MODE_ABT:
case PSR_AA32_MODE_UND:
case PSR_AA32_MODE_SYS:
if (!vcpu_el1_is_32bit(vcpu))
return -EINVAL;
break;
@ -270,7 +271,7 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
if (*vcpu_cpsr(vcpu) & PSR_MODE32_BIT) {
int i, nr_reg;
switch (*vcpu_cpsr(vcpu)) {
switch (*vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK) {
/*
* Either we are dealing with user mode, and only the
* first 15 registers (+ PC) must be narrowed to 32bit.

18
arch/arm64/kvm/hyp/aarch32.c
View file

@ -50,9 +50,23 @@ bool kvm_condition_valid32(const struct kvm_vcpu *vcpu)
u32 cpsr_cond;
int cond;
/* Top two bits non-zero? Unconditional. */
if (kvm_vcpu_get_esr(vcpu) >> 30)
/*
* These are the exception classes that could fire with a
* conditional instruction.
*/
switch (kvm_vcpu_trap_get_class(vcpu)) {
case ESR_ELx_EC_CP15_32:
case ESR_ELx_EC_CP15_64:
case ESR_ELx_EC_CP14_MR:
case ESR_ELx_EC_CP14_LS:
case ESR_ELx_EC_FP_ASIMD:
case ESR_ELx_EC_CP10_ID:
case ESR_ELx_EC_CP14_64:
case ESR_ELx_EC_SVC32:
break;
default:
return true;
}
/* Is condition field valid? */
cond = kvm_vcpu_get_condition(vcpu);

2
arch/arm64/kvm/vgic/vgic-init.c
View file

@ -355,7 +355,7 @@ static void kvm_vgic_dist_destroy(struct kvm *kvm)
if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
list_for_each_entry_safe(rdreg, next, &dist->rd_regions, list)
vgic_v3_free_redist_region(rdreg);
vgic_v3_free_redist_region(kvm, rdreg);
INIT_LIST_HEAD(&dist->rd_regions);
} else {
dist->vgic_cpu_base = VGIC_ADDR_UNDEF;

12
arch/arm64/kvm/vgic/vgic-kvm-device.c
View file

@ -337,16 +337,12 @@ int kvm_register_vgic_device(unsigned long type)
int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
struct vgic_reg_attr *reg_attr)
{
int cpuid;
int cpuid = FIELD_GET(KVM_DEV_ARM_VGIC_CPUID_MASK, attr->attr);
cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
KVM_DEV_ARM_VGIC_CPUID_SHIFT;
if (cpuid >= atomic_read(&dev->kvm->online_vcpus))
return -EINVAL;
reg_attr->vcpu = kvm_get_vcpu(dev->kvm, cpuid);
reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
reg_attr->vcpu = kvm_get_vcpu_by_id(dev->kvm, cpuid);
if (!reg_attr->vcpu)
return -EINVAL;
return 0;
}

15
arch/arm64/kvm/vgic/vgic-mmio-v3.c
View file

@ -942,8 +942,19 @@ free:
return ret;
}
void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg)
void vgic_v3_free_redist_region(struct kvm *kvm, struct vgic_redist_region *rdreg)
{
struct kvm_vcpu *vcpu;
unsigned long c;
lockdep_assert_held(&kvm->arch.config_lock);
/* Garbage collect the region */
kvm_for_each_vcpu(c, vcpu, kvm) {
if (vcpu->arch.vgic_cpu.rdreg == rdreg)
vcpu->arch.vgic_cpu.rdreg = NULL;
}
list_del(&rdreg->list);
kfree(rdreg);
}
@ -968,7 +979,7 @@ int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
mutex_lock(&kvm->arch.config_lock);
rdreg = vgic_v3_rdist_region_from_index(kvm, index);
vgic_v3_free_redist_region(rdreg);
vgic_v3_free_redist_region(kvm, rdreg);
mutex_unlock(&kvm->arch.config_lock);
return ret;
}

2
arch/arm64/kvm/vgic/vgic.h
View file

@ -301,7 +301,7 @@ vgic_v3_rd_region_size(struct kvm *kvm, struct vgic_redist_region *rdreg)
struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
u32 index);
void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg);
void vgic_v3_free_redist_region(struct kvm *kvm, struct vgic_redist_region *rdreg);
bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size);

3
arch/arm64/mm/pageattr.c
View file

@ -220,9 +220,6 @@ bool kernel_page_present(struct page *page)
pte_t *ptep;
unsigned long addr = (unsigned long)page_address(page);
if (!can_set_direct_map())
return true;
pgdp = pgd_offset_k(addr);
if (pgd_none(READ_ONCE(*pgdp)))
return false;

6
arch/arm64/net/bpf_jit_comp.c
View file

@ -1679,15 +1679,15 @@ static void invoke_bpf_prog(struct jit_ctx *ctx, struct bpf_tramp_link *l,
emit_call(enter_prog, ctx);
/* save return value to callee saved register x20 */
emit(A64_MOV(1, A64_R(20), A64_R(0)), ctx);
/* if (__bpf_prog_enter(prog) == 0)
* goto skip_exec_of_prog;
*/
branch = ctx->image + ctx->idx;
emit(A64_NOP, ctx);
/* save return value to callee saved register x20 */
emit(A64_MOV(1, A64_R(20), A64_R(0)), ctx);
emit(A64_ADD_I(1, A64_R(0), A64_SP, args_off), ctx);
if (!p->jited)
emit_addr_mov_i64(A64_R(1), (const u64)p->insnsi, ctx);

1
arch/csky/include/uapi/asm/unistd.h
View file

@ -6,6 +6,7 @@
#define __ARCH_WANT_SYS_CLONE3
#define __ARCH_WANT_SET_GET_RLIMIT
#define __ARCH_WANT_TIME32_SYSCALLS
#define __ARCH_WANT_SYNC_FILE_RANGE2
#include <asm-generic/unistd.h>
#define __NR_set_thread_area (__NR_arch_specific_syscall + 0)

6
arch/hexagon/include/asm/syscalls.h Normal file
View file

@ -0,0 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <asm-generic/syscalls.h>
asmlinkage long sys_hexagon_fadvise64_64(int fd, int advice,
u32 a2, u32 a3, u32 a4, u32 a5);

1
arch/hexagon/include/uapi/asm/unistd.h
View file

@ -36,5 +36,6 @@
#define __ARCH_WANT_SYS_VFORK
#define __ARCH_WANT_SYS_FORK
#define __ARCH_WANT_TIME32_SYSCALLS
#define __ARCH_WANT_SYNC_FILE_RANGE2
#include <asm-generic/unistd.h>

7
arch/hexagon/kernel/syscalltab.c
View file

@ -14,6 +14,13 @@
#undef __SYSCALL
#define __SYSCALL(nr, call) [nr] = (call),
SYSCALL_DEFINE6(hexagon_fadvise64_64, int, fd, int, advice,
SC_ARG64(offset), SC_ARG64(len))
{
return ksys_fadvise64_64(fd, SC_VAL64(loff_t, offset), SC_VAL64(loff_t, len), advice);
}
#define sys_fadvise64_64 sys_hexagon_fadvise64_64
void *sys_call_table[__NR_syscalls] = {
#include <asm/unistd.h>
};

7
arch/loongarch/include/asm/perf_event.h
View file

@ -7,6 +7,13 @@
#ifndef __LOONGARCH_PERF_EVENT_H__
#define __LOONGARCH_PERF_EVENT_H__
#include <asm/ptrace.h>
#define perf_arch_bpf_user_pt_regs(regs) (struct user_pt_regs *)regs
#define perf_arch_fetch_caller_regs(regs, __ip) { \
(regs)->csr_era = (__ip); \
(regs)->regs[3] = (unsigned long) __builtin_frame_address(0); \
}
#endif /* __LOONGARCH_PERF_EVENT_H__ */

2
arch/loongarch/kernel/perf_event.c
View file

@ -884,4 +884,4 @@ static int __init init_hw_perf_events(void)
return 0;
}
early_initcall(init_hw_perf_events);
pure_initcall(init_hw_perf_events);

4
arch/loongarch/mm/fault.c
View file

@ -193,10 +193,10 @@ good_area:
if (!(vma->vm_flags & VM_WRITE))
goto bad_area;
} else {
if (!(vma->vm_flags & VM_READ) && address != exception_era(regs))
goto bad_area;
if (!(vma->vm_flags & VM_EXEC) && address == exception_era(regs))
goto bad_area;
if (!(vma->vm_flags & (VM_READ | VM_WRITE)) && address != exception_era(regs))
goto bad_area;
}
/*

4
arch/m68k/kernel/entry.S
View file

@ -430,7 +430,9 @@ resume:
movec %a0,%dfc
/* restore status register */
movew %a1@(TASK_THREAD+THREAD_SR),%sr
movew %a1@(TASK_THREAD+THREAD_SR),%d0
oriw #0x0700,%d0
movew %d0,%sr
rts

36
arch/m68k/mac/misc.c
View file

@ -451,30 +451,18 @@ void mac_poweroff(void)
void mac_reset(void)
{
if (macintosh_config->adb_type == MAC_ADB_II &&
macintosh_config->ident != MAC_MODEL_SE30) {
/* need ROMBASE in booter */
/* indeed, plus need to MAP THE ROM !! */
if (mac_bi_data.rombase == 0)
mac_bi_data.rombase = 0x40800000;
/* works on some */
rom_reset = (void *) (mac_bi_data.rombase + 0xa);
local_irq_disable();
rom_reset();
#ifdef CONFIG_ADB_CUDA
} else if (macintosh_config->adb_type == MAC_ADB_EGRET ||
macintosh_config->adb_type == MAC_ADB_CUDA) {
if (macintosh_config->adb_type == MAC_ADB_EGRET ||
macintosh_config->adb_type == MAC_ADB_CUDA) {
cuda_restart();
} else
#endif
#ifdef CONFIG_ADB_PMU
} else if (macintosh_config->adb_type == MAC_ADB_PB2) {
if (macintosh_config->adb_type == MAC_ADB_PB2) {
pmu_restart();
} else
#endif
} else if (CPU_IS_030) {
if (CPU_IS_030) {
/* 030-specific reset routine. The idea is general, but the
* specific registers to reset are '030-specific. Until I
* have a non-030 machine, I can't test anything else.
@ -522,6 +510,18 @@ void mac_reset(void)
"jmp %/a0@\n\t" /* jump to the reset vector */
".chip 68k"
: : "r" (offset), "a" (rombase) : "a0");
} else {
/* need ROMBASE in booter */
/* indeed, plus need to MAP THE ROM !! */
if (mac_bi_data.rombase == 0)
mac_bi_data.rombase = 0x40800000;
/* works on some */
rom_reset = (void *)(mac_bi_data.rombase + 0xa);
local_irq_disable();
rom_reset();
}
/* should never get here */

1
arch/microblaze/kernel/Makefile
View file

@ -7,7 +7,6 @@ ifdef CONFIG_FUNCTION_TRACER
# Do not trace early boot code and low level code
CFLAGS_REMOVE_timer.o = -pg
CFLAGS_REMOVE_intc.o = -pg
CFLAGS_REMOVE_early_printk.o = -pg
CFLAGS_REMOVE_ftrace.o = -pg
CFLAGS_REMOVE_process.o = -pg
endif

2
arch/microblaze/kernel/cpu/cpuinfo-static.c
View file

@ -18,7 +18,7 @@ static const char family_string[] = CONFIG_XILINX_MICROBLAZE0_FAMILY;
static const char cpu_ver_string[] = CONFIG_XILINX_MICROBLAZE0_HW_VER;
#define err_printk(x) \
early_printk("ERROR: Microblaze " x "-different for kernel and DTS\n");
pr_err("ERROR: Microblaze " x "-different for kernel and DTS\n");
void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
{

3
arch/mips/bmips/setup.c
View file

@ -111,7 +111,8 @@ static void bcm6358_quirks(void)
* RAC flush causes kernel panics on BCM6358 when booting from TP1
* because the bootloader is not initializing it properly.
*/
bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31));
bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) ||
!!BMIPS_GET_CBR();
}
static void bcm6368_quirks(void)

2
arch/mips/boot/dts/brcm/bcm63268.dtsi
View file

@ -109,6 +109,8 @@
compatible = "brcm,bcm7038-twd", "simple-mfd", "syscon";
reg = <0x10000080 0x30>;
ranges = <0x0 0x10000080 0x30>;
#address-cells = <1>;
#size-cells = <1>;
wdt: watchdog@1c {
compatible = "brcm,bcm7038-wdt";

2
arch/mips/include/asm/ptrace.h
View file

@ -157,7 +157,7 @@ static inline long regs_return_value(struct pt_regs *regs)
#define instruction_pointer(regs) ((regs)->cp0_epc)
#define profile_pc(regs) instruction_pointer(regs)
extern asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall);
extern asmlinkage long syscall_trace_enter(struct pt_regs *regs);
extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
extern void die(const char *, struct pt_regs *) __noreturn;

1
arch/mips/kernel/asm-offsets.c
View file

@ -98,6 +98,7 @@ void output_thread_info_defines(void)
OFFSET(TI_CPU, thread_info, cpu);
OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
OFFSET(TI_REGS, thread_info, regs);
OFFSET(TI_SYSCALL, thread_info, syscall);
DEFINE(_THREAD_SIZE, THREAD_SIZE);
DEFINE(_THREAD_MASK, THREAD_MASK);
DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);

15
arch/mips/kernel/ptrace.c
View file

@ -1309,16 +1309,13 @@ long arch_ptrace(struct task_struct *child, long request,
* Notification of system call entry/exit
* - triggered by current->work.syscall_trace
*/
asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
asmlinkage long syscall_trace_enter(struct pt_regs *regs)
{
user_exit();
current_thread_info()->syscall = syscall;
if (test_thread_flag(TIF_SYSCALL_TRACE)) {
if (ptrace_report_syscall_entry(regs))
return -1;
syscall = current_thread_info()->syscall;
}
#ifdef CONFIG_SECCOMP
@ -1327,7 +1324,7 @@ asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
struct seccomp_data sd;
unsigned long args[6];
sd.nr = syscall;
sd.nr = current_thread_info()->syscall;
sd.arch = syscall_get_arch(current);
syscall_get_arguments(current, regs, args);
for (i = 0; i < 6; i++)
@ -1337,23 +1334,23 @@ asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
ret = __secure_computing(&sd);
if (ret == -1)
return ret;
syscall = current_thread_info()->syscall;
}
#endif
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
trace_sys_enter(regs, regs->regs[2]);
audit_syscall_entry(syscall, regs->regs[4], regs->regs[5],
audit_syscall_entry(current_thread_info()->syscall,
regs->regs[4], regs->regs[5],
regs->regs[6], regs->regs[7]);
/*
* Negative syscall numbers are mistaken for rejected syscalls, but
* won't have had the return value set appropriately, so we do so now.
*/
if (syscall < 0)
if (current_thread_info()->syscall < 0)
syscall_set_return_value(current, regs, -ENOSYS, 0);
return syscall;
return current_thread_info()->syscall;
}
/*

23
arch/mips/kernel/scall32-o32.S
View file

@ -77,6 +77,18 @@ loads_done:
PTR_WD load_a7, bad_stack_a7
.previous
/*
* syscall number is in v0 unless we called syscall(__NR_###)
* where the real syscall number is in a0
*/
subu t2, v0, __NR_O32_Linux
bnez t2, 1f /* __NR_syscall at offset 0 */
LONG_S a0, TI_SYSCALL($28) # Save a0 as syscall number
b 2f
1:
LONG_S v0, TI_SYSCALL($28) # Save v0 as syscall number
2:
lw t0, TI_FLAGS($28) # syscall tracing enabled?
li t1, _TIF_WORK_SYSCALL_ENTRY
and t0, t1
@ -114,16 +126,7 @@ syscall_trace_entry:
SAVE_STATIC
move a0, sp
/*
* syscall number is in v0 unless we called syscall(__NR_###)
* where the real syscall number is in a0
*/
move a1, v0
subu t2, v0, __NR_O32_Linux
bnez t2, 1f /* __NR_syscall at offset 0 */
lw a1, PT_R4(sp)
1: jal syscall_trace_enter
jal syscall_trace_enter
bltz v0, 1f # seccomp failed? Skip syscall

3
arch/mips/kernel/scall64-n32.S
View file

@ -44,6 +44,8 @@ NESTED(handle_sysn32, PT_SIZE, sp)
sd a3, PT_R26(sp) # save a3 for syscall restarting
LONG_S v0, TI_SYSCALL($28) # Store syscall number
li t1, _TIF_WORK_SYSCALL_ENTRY
LONG_L t0, TI_FLAGS($28) # syscall tracing enabled?
and t0, t1, t0
@ -72,7 +74,6 @@ syscall_common:
n32_syscall_trace_entry:
SAVE_STATIC
move a0, sp
move a1, v0
jal syscall_trace_enter
bltz v0, 1f # seccomp failed? Skip syscall

3
arch/mips/kernel/scall64-n64.S
View file

@ -46,6 +46,8 @@ NESTED(handle_sys64, PT_SIZE, sp)
sd a3, PT_R26(sp) # save a3 for syscall restarting
LONG_S v0, TI_SYSCALL($28) # Store syscall number
li t1, _TIF_WORK_SYSCALL_ENTRY
LONG_L t0, TI_FLAGS($28) # syscall tracing enabled?
and t0, t1, t0
@ -82,7 +84,6 @@ n64_syscall_exit:
syscall_trace_entry:
SAVE_STATIC
move a0, sp
move a1, v0
jal syscall_trace_enter
bltz v0, 1f # seccomp failed? Skip syscall

33
arch/mips/kernel/scall64-o32.S
View file

@ -79,6 +79,22 @@ loads_done:
PTR_WD load_a7, bad_stack_a7
.previous
/*
* absolute syscall number is in v0 unless we called syscall(__NR_###)
* where the real syscall number is in a0
* note: NR_syscall is the first O32 syscall but the macro is
* only defined when compiling with -mabi=32 (CONFIG_32BIT)
* therefore __NR_O32_Linux is used (4000)
*/
subu t2, v0, __NR_O32_Linux
bnez t2, 1f /* __NR_syscall at offset 0 */
LONG_S a0, TI_SYSCALL($28) # Save a0 as syscall number
b 2f
1:
LONG_S v0, TI_SYSCALL($28) # Save v0 as syscall number
2:
li t1, _TIF_WORK_SYSCALL_ENTRY
LONG_L t0, TI_FLAGS($28) # syscall tracing enabled?
and t0, t1, t0
@ -113,22 +129,7 @@ trace_a_syscall:
sd a7, PT_R11(sp) # For indirect syscalls
move a0, sp
/*
* absolute syscall number is in v0 unless we called syscall(__NR_###)
* where the real syscall number is in a0
* note: NR_syscall is the first O32 syscall but the macro is
* only defined when compiling with -mabi=32 (CONFIG_32BIT)
* therefore __NR_O32_Linux is used (4000)
*/
.set push
.set reorder
subu t1, v0, __NR_O32_Linux
move a1, v0
bnez t1, 1f /* __NR_syscall at offset 0 */
ld a1, PT_R4(sp) /* Arg1 for __NR_syscall case */
.set pop
1: jal syscall_trace_enter
jal syscall_trace_enter
bltz v0, 1f # seccomp failed? Skip syscall

2
arch/mips/kernel/syscalls/syscall_n32.tbl
View file

@ -354,7 +354,7 @@
412 n32 utimensat_time64 sys_utimensat
413 n32 pselect6_time64 compat_sys_pselect6_time64
414 n32 ppoll_time64 compat_sys_ppoll_time64
416 n32 io_pgetevents_time64 sys_io_pgetevents
416 n32 io_pgetevents_time64 compat_sys_io_pgetevents_time64
417 n32 recvmmsg_time64 compat_sys_recvmmsg_time64
418 n32 mq_timedsend_time64 sys_mq_timedsend
419 n32 mq_timedreceive_time64 sys_mq_timedreceive

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