From 1b2222254f78048324c4419b88b8aa4145464bb4 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 19 Aug 2024 08:49:52 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Update external clk parameters for better SI Signed-off-by: Shawn Lin Change-Id: Ic121a29ddc00357b069b27b0fe5e8f4654677ae1 --- .../rockchip/phy-rockchip-naneng-combphy.c | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 630c5765d516..2daa3a688ee0 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -554,9 +554,15 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) { - val = readl(priv->mmio + 0x108); - val |= BIT(29) | (0x3 << 4 | 0x1 << 7); - writel(val, priv->mmio + 0x108); + /* + * PLL charge pump current adjust = 111 + * PLL LPF R1 adjust = 1001 + * PLL KVCO adjust = 000 (min) + * PLL KVCO fine tuning signals = 01 + */ + rockchip_combphy_updatel(priv, GENMASK(2, 0), + BIT(29) | (0x7 << 4 | 0x9 << 7), 0x108); + rockchip_combphy_updatel(priv, GENMASK(12, 10), 0x2 << 10, 0x18); } } @@ -890,6 +896,15 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) { + /* + * PLL charge pump current adjust = 111 + * PLL LPF R1 adjust = 1001 + * PLL KVCO adjust = 000 (min) + * PLL KVCO fine tuning signals = 01 + */ + rockchip_combphy_updatel(priv, GENMASK(2, 0), 0xf << 4, 0xa << 2); + rockchip_combphy_updatel(priv, GENMASK(2, 0), 0x4, 0xb << 2); + rockchip_combphy_updatel(priv, GENMASK(4, 2), 0x2 << 2, 0x20 << 2); rockchip_combphy_updatel(priv, 0x3 << 4 | 0x1 << 7, 0x3 << 4 | 0x1 << 7, 0xc << 2);